The control unit pre-charge the output buffer unit for dynamic memory cells
(57) Abstract:The invention relates to computing. Its use in memory devices, random access allows you to increase the speed and reduce the switching noise. The device comprises a buffer memory element 1, the key elements of M 11 and M 12 output buffer unit 5, the key elements of M 5 and M 6 unit 9 pre-charge buffer key elements M 7 and M 8 elements, AND NOT N D 1 and N D 2, the elements are NOT 17 and 18 and the control block 10 of the preliminary charge. The technical result is achieved due to the introduction of buffer elements 11 and 12 memory formers 2 and 3 levels and the execution of the block 10 on the shaper 6 allow pulse and the imaging unit 7 of the control pulses. 1 C. p. F.-ly, 2 Il. The invention relates to control devices in the output buffer of data from the storage device, in particular to devices for controlling the pre-charge the output buffer unit for use in the detection of changes of address, in which, before the real data are given to the output, the output terminal is shifted to a desired level due to the fact that the circuit for pre-charging is subdivided in accordance with the W and if the inverse output data is "0", the output terminal is charged.Semiconductor memory device writes data from the input terminals in the internal memory cells and, if necessary, reads the stored data from the internal memory to the output terminal, and when doing this read or write, you must perform a number of internal stages. The output data consists of many stages: signal address column Gating input/output select line I/o line selection signal resolution of the data, select the data bus and data output.If signal address column, you will see the gate pulse to select the terminal I/o, and then select the line input/output. Then on the steps of selecting a line and I/o lines signal the resolution of the data is the second reading, in order to improve the low line voltage input/output to a higher voltage, to select the data bus and to output data.Between the data bus and the output terminal of the data requires conversion of the data signal so that the signal level, which was before the data bus CMOS level at its output became TTL-level. Accordingly the output was used schemes, in which the circuit for pre-charging due to the action of the control pulse of the preliminary charge is held together by the MOS transistors M1, M2 in the on or off state, resulting in a DC circuit.Known designs in which the scattering constant current can be prevented by Gating pulse control pre-charge DCPP, but in this case, when the inverted data are at the level "0", the output terminal of the data can not be pre-charged to a high impedance level, and in addition, in the section pre-charge requires the use of a MOS transistor is large in size.The aim of the invention is a device control pre-charge the output buffer unit in which the noise occurring on the output side section of the preliminary charge, can be eliminated and the speed of data processing in the circuit controlled by the detection of changes of address may be increased.Another objective of the invention is to provide a control device of the prior charge, in which section of the preliminary charge, given the reliability of the latch on the output side, can the state is s data ("1" or "0") instituted various MOS transistors, the components of the circuit for pre-charging. Feeding level L ("0") inverted data section pre-charge forms a charge circuit, so that the overall level should be increased and the signal TTL-level will be output at high speed.When the above objectives, in the control device pre-charge in accordance with the state of the inverted data on the output side, the output side of the output buffer is charged or discharged in accordance with the inverse of the data from section generating a data signal, and an output terminal decreases or increases in advance before through the output terminal of the output buffer is served then the true data.In Fig. 1 shows a control circuit pre-charge output buffer in accordance with the invention; Fig. 2A and b timing diagrams showing the operation for pre-charging the output buffer in accordance with the invention.The control unit pre-charge contains an output buffer 1 memory element to which the signal data from the data bus DB , the first and second formers 2 and 3 level for delivery to the output data "1" or "0" after receiving the output signal of block 1 and whitefish the m output signals of these formers 2 and 3, unit 10 controls the preliminary charge, which includes the imaging unit 6 permitting pulses to generate in response to the signal change of address control signals TRST tristate and shaper 7 pulses of the Board for submission to the output of the control pulses of the preliminary charge, and block 9 of the provisional charge for receiving output signals DOUT block 5.The device comprises a further section 15 to generate a signal change data to signal data DDPP, DIP to the specified unit 9 pre-charge buffer consisting of key elements M 7 and M 8 for supplying the data signals DB , second and third buffer elements 11 and 12 memory for latching output signals from the specified buffer key elements M 7 and M 8 elements NOT 17 and 8, AND NOT ND 1 and ND 2 to match the signals specified buffer elements 11, 12 memory and these pulses control the pre-charge DCCP from the control block 10 of the preliminary charge.Unit 9 pre-charge consists of the key elements of M 5 and M 6, which is connected to the output terminal DOUT buffer unit 5, and the specified unit 9 pre-charging is connected to the output of the buffer unit 5.As shown in Fig.2A, the control signal TRST goes from high to low when the signal changes of address subsides. Through falling edge of the signal pulse is generated, the control pre-charge DCP pulse with auto width AUTO.The charge pulse line data bus DOP has the function of pre-charge terminal line data bus DB and line feed enable signal data D1 at the time when the signal changes of address has a level L.First, in General terms be described excitation circuit according to the invention. In the case when the data bus is in the buffer unit 5 loads the data "0" and the data bus DB to load the data "1", the output of the element OR NOT ND 1 through the memory element 1 becomes equal to A, and the output element 2 ND OR becomes equal to "0".Therefore, in the formers 2 and 3 level signal is output level N.If is driven by the first imaging unit 2 having data "1", then the signal of level H is supplied to key the I in the second imaging unit 3, having data "0", then the level of N signal comprises a key element of M 12, so that the output terminal DOUT acquires the status of level N.Now, referring to Fig.2A, will be described operation of the circuit according to the invention for the case of "1" inverted data.When the signal permission circuits , which is a mechanical machine cycle is enabled (state N) signal TRST (C) control buffer unit 5. In this case, the column address CAi is the inverse of the address, and CAj is true address column. If the cell data corresponding to the inverted column address CAi is "1", and the cell data corresponding to the true column address CAj is "0", the output terminal DOUT, when the signal TRST (1) increases from the high-impedance level to a high voltage. At this point, buffer included key elements M 7 and M 8 and item 11 of the memory goes to level H, and the memory element 12 in the level L. Then, the column address is changed from CAi to CAj and, therefore, the signal change of address during the duration of the pulse goes to level L. As shown earlier, if the signal transferred from level H to level L indicated by the block 10 is generated inhabitat thus, when the flow control signal tri-state TRST, due to the action of the elements AND NOT ND 1 and ND 2 and item NO 17 and 18, the data of the data bus DB and must be submitted through the buffer key elements M 7 and M 8, and DIP data, DDPP should be output through the elements 11 and 12 of the memory.When the control pulse pre-charge DCPP, data DDPP, DIP is generated in accordance with the state of the inverted data, which are supplied through the data bus DB. If the inverse of the data are 1, the DIP will have level N, as long DDPP will have level L, while if the inverse data represents "0", the data DDP P will generate a signal of level H, and the data DIP will generate a signal of level L is supplied to the key elements of M 5, M 6, unit 9 of the provisional charge.The data signals that are fed through the data bus DB, and served through the memory element 1 consisting of elements OR NOT NO1, NO2 and items 11 and 12 of the memory on the formers 2 and 3 level, where key elements of M 11 and M 12 are control signals tri-state TRST.As a result, if the inverse data represents "1", the data signal DIP will have level N, including the key element of M 6 block 9 predvaril inverse voltage DOUT before achieving true data "1".On the other hand, if the inverse data represents "0", the data signal DDPP will have level N, including the key element of M 6. Accordingly, the output terminal DOUT is charged via a key element of M 5, thereby increasing the inverse voltage DOUT before achieving true data N.The result can largely reduce noise and greatly improve the speed.If the inverse of the data are at the level H, the output terminal DOUT (Fig.2A) produces an output signal consisting of a combination of the control signal TRST and a status signal of the data bus DB. If the inverse of the data are "1" during the standing time is included a key element of M 6, initially lowering together with the signal DIP.Accordingly, the true data submitted in the following address segment CAj, loaded at a lower level, thereby reducing the noise and increasing the speed.Now, description will be given of the level of the output terminal DOUT for the case when the inverse of the data are at the level L, as shown in Fig.2B.In this case, as in the case shown in Fig.2A, the inverse data "0" will be loaded into the segment address CAi address columns Ai, and the true data "1" by of combinations of control signal tri-state TRST and a status signal bus , moreover, the inverse of the data are of level L, and a key element of M 5 is included in the state "0" inverted data to improve the original level together with the data signal DDP P.Accordingly, the true data is loaded into the next segment address Aj loaded at a higher level, thereby reducing the noise and increasing the speed.As shown above, in accordance with the invention the output side is charged or discharged in accordance with the fact whether the state of the inverted data "1" or "0", resulting in the transition from the inverted data to the real data and the noise can be reduced and the true data submitted to the state charged or discharged in advance, so that the processing speed can be increased.In particular, unit 9 pre-charge in accordance with the proposed invention uses an n-channel MOS transistors, resulting in guaranteed reliability during operation of the latch, and the like, making it possible to use in the output buffer MOSFET small size. 1. The CONTROL UNIT PRE-CHARGE the OUTPUT BUFFER UNIT CELLS of the DYNAMIC MEMORY, steriade the inputs of the device, the first and second key elements of the output buffer unit, connected in series between the first and second sources of supply voltages, the first and second key elements of pre-charge, connected in series between the first and second sources of supply voltages, the junction point of the key elements of the output buffer unit and a unit for pre-charging are combined and output devices, the control unit pre-charge the input which is the input signal changes the address of the device, and the output is connected with the first inputs of the first and second elements AND the outputs are through the same elements are NOT connected to the control inputs of the same name the key elements of the pre-charge the first and second buffer core elements that control inputs are combined, characterized in that it introduced the first and the second shaper level and the second and third buffer memory elements, and the control unit preliminary charge made on the shaper allow pulses and the pulse shaper control preparada, the output of which is connected to prohibit the input of the shaper allow pulses and is vyhoda control unit pre-charge, the output of shaper allow pulses connected to the input of the shaper pulse control preparada, control inputs of the first and second shapers level and joint control inputs of the first and second buffer key elements of the information inputs of the first and second buffer key elements connected respectively to the forward and the inverse of the information input device, the outputs of the first and second buffer key elements respectively through the second and third buffer memory elements are connected to second inputs of the first and second elements AND IS NOT, direct and inverted outputs of the first buffer memory element connected to information inputs respectively of the first and second shapers level, the outputs are connected to control inputs of the same name the key elements of the output buffer block.2. The device under item 1, characterized in that the buffer key elements and key elements of the pre-charge and the output buffer unit is made on the MOS transistors.
FIELD: physics, computer facilities.
SUBSTANCE: invention concerns a storage device and to the leading device using this storage device. The storage device contains semiconductor storage, the controller which is carrying out the instruction for data recording in semiconductor storage according to inquiry which accepts the controller, and the register provided in the controller and retaining the information of a class of speed, showing one of classes of speed classified on speed, and mentioned one of speed classes specifies, that the storage device provides a guaranteed minimum of speed designated mentioned by one of speed classes, thus the storage device is executed with possibility of delivery the information of a class of speed in reply to the instruction, exterior in relation to a storage device.
EFFECT: obtaining of possibility of predicting of of a storage device speed.
14 cl, 24 dwg
FIELD: information technology.
SUBSTANCE: method of refreshing a dynamic random-access memory (DRAM) array in form of independently refreshable memory units, comprising: associating an indicator with each independently refreshable memory unit; upon writing data to an independently refreshable memory unit, setting the associated indicator to reflect valid data; increasing delay between refreshing operations in proportion to the zero number of suppressed refreshing cycles, wherein a refreshing cycle is suppressed if the associated indicator reflects invalid data, so that only all independently refreshable memory units, which contain valid data, can be refreshed with maximum period of refreshing; and refreshing with said maximum period of refreshing only the independently refreshable memory units whose associated indicator reflects valid data stored therein.
EFFECT: reducing DRAM power consumption.
26 cl, 6 dwg
FIELD: information technology.
SUBSTANCE: method for regeneration and failure protection of dynamic memory, involving serial reading of data, detecting errors in the data contained in memory, modifying the data by correcting the detected errors at each memory address and reading with a period of time which is not greater than the memory regeneration time, wherein the modified data are recorded at the same memory address with a lower priority, and during the recording latency period, access to the same memory address is listened and stability errors are then analysed.
EFFECT: faster operation and failure safety of the system.
4 cl, 2 dwg