The processing unit signals faber-sauder

 

(57) Abstract:

The invention relates to automatic control and computer engineering. The technical result is to expand the functionality of the device, such as the ability to form a complete independent system signals Faber-saudara, and its simplification. The device includes a counter, m -1 modulo two, a clock generator, an integrator, m block level offset of the first group, m-1 sign multiplier, m-1 groups of keys and m-2 blocks the bias level of the second group. 1 Il.

The invention relates to automatic control and computer engineering and can be used in devices of spectral analysis and communication to generate orthogonal signals.

The aim of the invention is the simplification of the device generating signals Faber-Sauder.

For this purpose, the device for generating signals Faber-Sauder containing m-bit counter (2m-1 number of functions, clock generator, m-1 adders modulo two, integrator, m block level offset of the first group and m-1 sign multiplier products, and the output of the clock generator is connected to the counter input of the i-th and (i+1) th straight bit outputs (i=) is connected to input the information input connected to the output of the th block of the level shifter, the input of the j-th block level offset (j= ) is connected to the output of the i-th landmark multiplier, the input of the first block level shifter connected to the output of the integrator, the input of which is connected to m-m direct bit output of the counter contains m-1 groups of keys and m-2 blocks the bias level of the second group, and the control inputs (2i+12k+1+ 2p 1)-th and (2i+12k+1+ 2p)-th i-th group (k , p ) are connected respectively with the k-th direct and inverse bit outputs of the counter information inputs (2i+12k+1+ 2p 1)-th and (2i+12k+1+ 2p)-th i-th group, excluding k 1, is connected with the output (2i+12k+ p)-th key of the i-th group, the output of the l-th block of the bias level of the first group (l ) is connected to the input of the s-th block of the level shifter of the second group (s ), the output of which is connected to information inputs (2i+13)-th and the (2i+12)-th s-th group, the output of the m-th block of the bias level of the first group connected to information inputs (2m-3)-th and the (2m-2)-th key (m-1)-th group, the output of the integrator and the key outputs from the first to the 2i-th i-th group are the outputs of the device.

A device for generating signals Faber-saudara for the case of the formation of the seven signals are represented in the drawing.

A device for generating signals Faber-Sauder works as follows.

In the beginning of his work the clock pulses from the output of the generator 1 are received at the counting input a three-digit binary counter 2, which is under their influence generates signals Rademacher taken respectively from the outputs of the third, second and first digits of the counter 2. The signal Rademacher R1with an output of the third digit counter 2 is supplied to the input of the integrator 4, and output 8 which remove the first signal Faber-chowder, which is the triangular function on the interval of definition. The basis of the invention is the possibility of obtaining piecewise linear orthogonal (or linearly-independent signals that form the basis of a signal (in this case a triangle) is the bookmark part of the interval of their definition with the help of keys. Therefore, the triangular signal from the output of the integrator 4 is shifted by the level and turns into a bipolar signal, which is multiplied by the sign of the multiplier signal Walsh R1,R2taken from the output of the adder 3 modulo two. This received signal is sent to the next level shifter, where it turns into two series-connected triangular signal which is fed to the inputs of the 7 keys of the first group of keys. Due to the fact that these keys are managed direct and inverse output signal of the third digit counter 2, is the separation of the two triangular signals. With exit 9 off the second signal Faber-saudara, and third output 10. Similarly the acquisition of the fourth, fifth, sixth and seventh signals Faber-Sauder retiring outputs 11-14 with the only difference that the 7 keys of the second group is a successive division of the input signal representing the four series-connected triangles, first two, then another two. Through eight stages of the counter 2, the device for generating signals Faber-Sauder quit.

Comparison of the known technical solutions proposed by the I SIGNAL FABER-SAUDER, containing m-bit counter (2m1 the number of functions), clock generator, m-1 adders modulo two, integrator, m block level offset of the first group and m is 1 sign multiplier, and the output of the clock generator is connected to the counter input i - and (i + 1) th straight bit outputs of the counter (i 1, m 1) are connected to the inputs of the i-th modulo two, the output of which is connected with the iconic sign of the i-th landmark multiplier, an information input connected to the output of the i-th block of the level shifter, the input of the j-th block level offset (j 2, m) is connected to the output of the i-th landmark multiplier, the input of the first block level shifter connected to the output of the integrator, the input of which is connected to m-m direct bit output of the counter, characterized in that it contains m-1 groups of keys and M 2 blocks level shifter of the second group, and the control inputs (2i+12k+1+ 2p 1)-th and (2i+12k+1+ 2p)-th i-th group are connected respectively with the k-th direct and inverse bit outputs of the counter information inputs (2i+1- 2k+1+ 2p 1)-th and (2i+1- 2k+1+ 2p)-th i-th group, excluding k 1, soeding connected to the input of the S-th block of the level shifter of the second group, the output of which is connected to information inputs (2i+13)- and (2i+12)-th S-th group, the output of the m-th block of the bias level of the first group connected to information inputs (2m3)-and (2m2)-th key (m 1)-th group, the output of the integrator and the key outputs from the first to the 2i-th i-th group are the outputs of the device.

 

Same patents:

The invention relates to automation and computer engineering and can be used to generate linearly independent functions

The invention relates to automatic control and computer engineering and is intended to generate orthogonal signals

The invention relates to automation and computer engineering and can be used in stochastic functional converters, stochastic computing devices in a probabilistic modeling and stochastic data processing

The invention relates to automatic control and computer engineering

The invention relates to automatic control and computer engineering and can be used in the devices of spectral analysis and communication to generate orthogonal signals

The invention relates to automation and computer engineering and can be used to create a generator equipment multi-channel communication systems

The invention relates to automation and computer engineering and can be used to create a generator equipment multi-channel communication systems

The invention relates to automatic control and computer engineering and can be used to build generators systems discrete orthogonal signals

The invention relates to automatic control and computer engineering

The invention relates to automatic control and computer engineering and is intended to generate orthogonal signals

FIELD: physics, computation equipment.

SUBSTANCE: generator of discrete orthogonal multilevel signals includes pacing generator, frequency splitter, Walsh function generation unit, three multiplier groups, 'NOT' element, switchboard, two control signal generation units, and amplifiers with variable amplification gain. Pacer generator output is connected to input of frequency splitter, output of which is connected to clock input of Walsh function generation unit, to first input of each multiplier of first group, and via 'NOT' element to first input of each amplifier of second group, to clock inputs of control signal generation units. Outputs of Walsh function generation unit are connected to first input of corresponding amplifier from third group, to master input of switchboard, and to data input of switchboard respectively. Switchboard output is connected to second inputs of all third group amplifiers. Output of one of the third group amplifiers is connected to second outputs of respective amplifiers from the first and second groups. Outputs of amplifiers from the first and second groups are connected to inputs of respective amplifiers with variable amplification gain. Outputs of control signal generation units are connected to master inputs of amplifiers with variable amplification gain, outputs of which are the device outputs.

EFFECT: enhanced jamming resistance of generated discrete orthogonal signals.

4 dwg, 2 tbl

FIELD: information technology.

SUBSTANCE: device has two counters, a group of AND elements, two half adders, a flip flop, four AND elements, two OR elements, two registers, three random pulse sequence generators, a bidirectional counter and a memory element.

EFFECT: broader functional capabilities owing to successive generation of Walsh functions with a random number, random pause between functions, with random phase shift of the generated Walsh functions and with random polarisation of Walsh functions in direct or inverted form.

1 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: generator of discrete orthogonal signals comprises a driving oscillator, a unit of Walsh functions generation, an element of single-sided conductivity, a four-digit cyclic shift register, a double-input commutator, a controller inverter and 2n group multipliers.

EFFECT: increased energetic security of signals generated by a generator.

8 dwg, 3 tbl

FIELD: radio engineering, communication.

SUBSTANCE: shaping device of discrete orthogonal multilevel signals includes two switching devices and a signal delay unit. The fifth output of the Walsh function shaping unit is connected to control inputs of the first and the second switching devices, the fifth and the fifteenth outputs of the Walsh function shaping unit are connected to upper and lower information inputs of the first switching device respectively, the fifth and the thirteenth outputs of the Walsh function shaping unit are connected to upper and lower information inputs of the second switching device respectively; output of the second switching device is connected to input of the signal delay unit; the second output of the Walsh function shaping unit is connected to control input of the third switching device; outputs of the first switching device and the signal delay unit are connected to information inputs of the third switching device; output of the third switching device is connected to the first inputs of all multipliers; output of Walsh i-function of the Walsh function shaping unit is connected to the second inputs of all the multipliers; outputs of the multipliers are outputs of the shaper of discrete orthogonal functions.

EFFECT: increasing interference immunity of shaped discrete orthogonal signals.

3 dwg

FIELD: physics.

SUBSTANCE: generator contains a clock generator (1), a Walsh function generating unit (2), a pulse driver (3), a trigger (4), the first switch (5), the second switch (6), an adder (7), 2n multipliers (8) of the first group,2n multipliers (9) of the second group,2n-1-bit cyclic shift register (10), a controlled inverter (11), a frequency divider (12), a four-bit cyclic shift register (13), the first additional key (14), the second additional key (15), the third additional key (16), the fourth additional key (17), and a four-input adder (18).

EFFECT: expansion of functionality.

1 dwg

Up!