A device for calculating a two-dimensional convolution

 

(57) Abstract:

The invention relates to computer technology and can be used in specialized computer systems to calculate the two-dimensional convolution. The purpose of the invention reduce hardware costs, increase reliability at the expense of control and redundancy and enhanced functions by solving problems of different dimensions. This objective is achieved in that the conveyor device for processing information contains L processing units, where L Q + R, Q - order tasks, R the number of spare blocks, two blocks of summation, L adders, L 1 registers, a group of L nodes comparison, node comparison, the L groups of elements, OR L groups of elements And the element OR NOT and OR. 2 C. p. F.-ly, 3 ill. 6 table.

The invention relates to computer technology and can be used in specialized computer systems to calculate the two-dimensional convolution.

Usually to ensure the accuracy obtained by the data processing results using the test periodic monitoring conducted by using external software and hardware. When the periodic test control is ontrol), the volume of erroneous information, the issuance of which occurs between the test checks, is also proportional to the control period. Time spent on test validation are determined by the volume of the test, so the bandwidth range of the processing units of the known devices is inversely proportional to the time spent on test validation. The probability of a failure is detected using the test checks is determined by the resolution of the test and the amount of equipment covered by the control. The recovery time of failure using a test inspections is determined by the resolution of the test and the amount of equipment covered by the control. The recovery time computing process after detection of the failure processing unit (obtaining a reliable result on the output device) is proportional to the number n of processing units of the device (length n line device).

The purpose of the invention reduce hardware costs, increase reliability at the expense of control and redundancy and enhanced functions by solving problems of different dimensions.

This objective is achieved in that the device contains paudie inputs 16 and 17 are connected respectively to the information inputs of the first and second groups, the first and second control inputs of the first processing unit outputs the first and second groups, the first and second outputs of the i-th processing unit (where i1, Q-1) are connected respectively to the information inputs of the first and second groups, the first and second control inputs of the (i+1)-th processing unit, the input 21 of clock pulses devices are connected to the clock inputs of the processing units from the first to Q-th entered with (Q+1)-th to L-th processing units 1, where L Q + R, R the number of redundant processing units 1, the first and second summation blocks 2 and 3, L adders 4, L-1 registers 5, the group of L nodes comparison 6, node 7 comparison with the first (L+1)-th group elements OR 8 and 9, L groups of elements And 10, the element OR NOT element 11 and OR 12, and outputs the first and second groups, the first and second outputs of the j-th processing unit (where j Q, L-1) connected respectively to the information inputs of the first and second groups, the first and second control inputs (j+1)-th processing unit, a clock input device 21 is connected to the clock inputs of summation blocks 2 and 3, processing units with (Q+1)-th to L-th inputs of the read/write registers 3, the information inputs of the third group of 15 devices connected respectively to the information inputs of the third group of the first processing unit, VK-th group and respectively to the control inputs of the first group (K+1)-th processing unit, the outputs of the third group of L-th processing unit connected respectively to the first inputs of elements And 10 L-th group, control inputs 19 of the first group are connected respectively to the control inputs of the first group of the first processing unit, the outputs of the fourth group of K-th processing unit connected respectively to the first inputs of the elements OR 8 K-th group, the outputs of which are connected respectively to the control inputs of the first group (K+1)-th processing unit, the outputs of the fifth group of l-th processing unit (where l 1,L) connected respectively to the information inputs of the group of l-th adder 4, the outputs of the K-th adder 4 is connected respectively to the information inputs of the K-th register 5 and respectively to the inputs of the first group of K-th node comparison 6, the outputs of the L-th combinational adder 4 is connected respectively to the inputs of the first group of L-th node 6 comparison group, control inputs of the second group 20 of the device connected to the control inputs of the second groups of processing units from the first to the L-th and the inputs of the second group of nodes comparison 6 groups, the output of the l-th node 6 comparison group connected to the second inputs of elements And 10 l-th group and the l-th input element OR NOT 11, the output of which is connected to the first input element OR 12, the output Karim inputs elements OR 8 K-th group, the third output of the l-th processing unit connected to the information input of the l-th adder 4 and the l-th output 26 group characteristic failure of the device, the third control input 18 which is connected to the control inputs of summation blocks 2 and 3, the outputs of the elements And 10 groups from the first to the L-th connected respectively to the inputs of elements OR 9 L-th group, the outputs of which are connected to information inputs of summation blocks 2 and 3, the outputs of the first summation block 2 is connected to the outputs 28 of the device and the inputs of the first group (L+1)on site compare 7, the inverted output of which is connected to the second input of the OR element 12, the outputs of the second summation block 3 are connected respectively to the inputs of the second group (L+1)-th node comparison 7, the l-th input set of the first group 22, the l-th input set of the second group 23, the l-th input set of the third group 24 and the l-th entry lock device 25 are connected respectively to the first, second, third input setup and input lock l-th processing unit.

Each processing unit 1 includes first and second computing nodes 29 and 30, the node comparison 31, the trigger 32, the first to the third element nodes And 33-35, the node elements OR element 36 and 37, and in each processing unit of the information in the group block is connected respectively to the inputs of the group of the first node elements And 33 and outputs the second group of node elements And 34, the outputs of the first group of the first node elements And 33 are connected respectively to the inputs of the first group of node elements OR 36 whose outputs are connected respectively to the outputs of the first group 52, the second group 53, the third group 54, the first 55 and second 56 outputs of the block, the outputs of the first group to the second node elements And 34 are connected to information inputs of the first group, second group, third group, the first and second control inputs of the first and second computing nodes, the outputs of the first, second and third groups, the first and second outputs of the first computing node 29 is connected to the inputs of the first node group comparison 31 and input group of the third node elements And 35, the outputs of which are connected respectively to the inputs of the second group of node elements OR 36, the outputs of the first, second and third groups, the first and second outputs of the second computing node 30 connected respectively to the inputs of the second node group comparison 31, the output of which is connected to the information input of the trigger 32, the output of which is connected to the input of the third node elements And 35, the third output 50 of the processing unit, inverted input of the first node elements and 33 and the input of the second node elements And 34, the outputs of the second groups of the first and second nodes of the elements ka processing connected respectively to the control inputs of the group of the first compute node and the control input group of the second computing node, the first and second inputs installation 45 and 46 of the processing unit are connected respectively to the inputs setup to "zero" and "unit" trigger 32, the third input set 44 processing unit connected to the inputs of the installation to its original state of the first and second computing nodes, the clock input 48 and the input 47 of the lock processing unit connected respectively to the first and second (inverse) input element And 37, the output of which is connected to the clock inputs of the first and second computing nodes and trigger.

Each unit summation 2(3) contains two registers 97, 98 and the adder 99, and the clock input 102 of the summation block is connected to the inputs of the read/write of the first and second registers 97 and 98, the outputs of which are connected respectively to the information inputs of the adder 99, the outputs of which are connected to the outputs 103 unit summation and information inputs of the second register 98, informational inputs 100 and the control input unit 101 summation connected respectively to the information inputs of the first register 97 and the input set to zero second register 98.

Each compute node contains four groups of registers 57-60, register 61, a multiplier 62, an adder 63, a group of trigger 64, the trigger 65, M + 3P + 7 g is and informational inputs of the first group of 84 computing node connected to information inputs of the first register of the first group 571and the first inputs of elements And the first group 70, the outputs are connected to first inputs of elements OR first group 76, the outputs of which are connected to information inputs of the first register of the second group 591the outputs of the m-th register 57 of the first group (where m 1, M-1) connected to information inputs (m+1)-th register 57 of the first group and the first inputs of elements And (m+1)-th group 66, the outputs of the elements And groups 66 from the second to the (M+1)-th connected to respective inputs of the elements OR the second group 74, the outputs of which are connected to the outputs of the first group 92 computing node, the information inputs of the second group 85 which is connected to information inputs of the first register of the third group 581and the first inputs of elements And (M+2)-th group 72, the outputs are connected to first inputs of the elements OR the third group 79 whose output is connected to information inputs of the first register of the fourth group 601the outputs of the first register of the second group 591connected to information inputs of the first group of multiplier 62, the first inputs of elements AND 68,1(M+3)-th group and the information inputs of the second register of the second group 592the outputs of the n-th register 59 of the second group (where n is 2, R) is connected to the information input is) th to (M+3+P)-th connected to respective inputs of the elements OR 77 of the fourth group, the outputs are connected to first inputs of elements And 71 (M+P+4)-th group, the outputs of which are connected respectively to the second inputs of the elements OR 76 of the first group, the outputs of the S-th register 58 of the third group (where S 1,P) is connected to information inputs (S+1)-th register 58 and to the first inputs of elements And 67 (M+P + 4 + +S)-th group, the outputs of the elements And 67 groups with (M+P+5)th to (M+2P+5)-th connected to respective inputs of the elements OR 75 of the fifth group, the outputs of which are connected respectively to the outputs of the second group of compute nodes, the outputs of the first register 60 of the fourth group are connected to first inputs of elements AND 691(M + 2P + 6)-th group of information inputs of the second register of the fourth group 602and information inputs of the second group of multiplier 62, the outputs of which are connected respectively to the information inputs of the first group of the adder 63, the outputs of which are connected respectively to the outputs of the group 94 computing node, the information inputs of the third group 86 which are connected respectively to the information inputs of the register 61, the outputs of which are connected respectively to the information inputs of the second group of the adder 63, the outputs of the r-th register 60 of the fourth group (where r 2, R) is connected to informationgroup with (M+2P+7)-th through (M+3P+7)th is connected to the corresponding inputs of the elements OR 78 of the sixth group, the outputs are connected respectively to the first inputs of elements AND 73 (M+3P+8)-th group, the outputs of which are connected respectively to the second inputs of the elements OR 79 of the third group, the first control input 87 of the device connected to the second inputs of elements And 70 of the first group, the second (inverted) inputs of elements And 71 (M+P+4)-th group and the information input of the first flip-flop 641group, the output of the v-th flip-flop 64 groups (where v 1, M-1) connected to the information input (v+1)-th flip-flop group 64 and the first input of the v-th element 80, the outputs of the elements And 80 from the first to the M-th connected respectively to the inputs of the OR element 81, the output of which is connected to the first output of the computing node 95, the second control input 88 which is connected to the second inputs of elements And 72 (M+2)-th group, the second (inverse) the inputs of elements AND 73 (M+3P+8)-th group and the information input of the trigger 65, the output of which is connected to the second output 96 compute nodes, the control inputs of 89 group from the first to a-th (where a log2M) which are connected respectively to the inputs of the first decoder 82, the i-th output of which (where i 1,M) is connected to the second inputs of elements And 66 (i+1)-th group and the second input of the i-th element 80, the control inputs of 89 group (a+1)-th to N-th (where otklyuchen to the second inputs of elements And (M+P+4+j)-th group 67, (M+2+j)-th group 68 and (M+2P+6+j)-th group 69, clock input 90 of the computing node is connected to the clock inputs of registers and triggers, input 91 of the installation to its original state computing node connected to the inputs setup to zero all registers and flip-flops.

In Fig. 1 shows a block diagram of the device of Fig. 2 block diagram of the processing unit of Fig. 3 is a structural diagram of a computing node.

A device for calculating a two-dimensional convolution contains L processing units 1, where L Q + R, Q the dimension of the window of the two-dimensional convolution (P x Q), R the number of spare blocks, the summation blocks 2 and 3, L adders 4, L-1 registers 5, L nodes comparison 6, the node comparison 7, L groups of elements, OR 8 and 9, L groups of elements And 10, the element OR NOT 11, item, OR 12, informational inputs 13-15, control inputs 16-20, clock input 21, the inputs setup 22-24, the inputs of the block 25, the outputs 26, 27 of the sign of failure, the output of the 28.

Each processing unit 1 includes compute nodes 29 and 30, the node 31 of the comparison, the trigger 32, the element nodes And 33-35, the node elements OR 36, information inputs 37-39, control inputs 40-43, inputs installation 44-46, entrance lock 47, a clock input 48, the outputs 49-56.

Each compute node 29 (30) contains groups of the s elements OR 74-79, element 80, item, OR 81, decoders 82 and 83, information inputs 84-86, control inputs 87-89, clock input 90, entry 91 installation to its original state, the outputs 92-96.

Each unit summation 2(3) contains the registers 97 and 98, the adder 99, informational inputs 100, the control input 101, a clock input 102 and the outlet 103.

The basis of operation of the device based on the algorithm for computing the two-dimensional convolution

Yij= xi-p,j-q, i , j , which consists of two parts:

1. Zoijp= 0, i , j , p ;

Zq+1ijp= Zqijp+pqxi-p,j-q, q

2. Yoij= 0, i , j ;

Yp+ij1= Ypij+ ZQijpp

The first part of the algorithm is the calculation of

ZQijp=xi-p,j-qthe second part of the calculation is

Yij= Ypij= Zijp.

When describing the operation of the device in the notation xij(k)index (K) in parentheses indicates the number of operation cycle of the device, and the index To without parentheses the number of recurrent step.

Compute node 29 (30) has the ability to implement the following functions:

Xi+Ip+1xi;

i+p+1=i< / BR>
Zi+1Zii+12iwhere xiiandivalues respectively on the information inputs 84, 85 and 86 of the computing node at i-th step;

Xi,iand Zivalues respectively at the outputs 92, 93 and 94 of the computing node at i-th step;

1iand2ivalues respectively to the control inputs 87 and 88 of the computing node at i-th step;

T1iand T2ivalues respectively at the outputs 95 and 96 compute nodes to the i-th step.

The summation block 2(3) has the ability to implement the following functions:

Yi+1= where Zithe value on the information inputs 100 block summation on i-th step;

Yithe value on the output unit 103 summation on i-th step;

3ithe value of the control input unit 101 summation on i-th step.

Compute node 29(30) works as follows.

The inputs 13-17 served, respectively, the values x, , Z1and2. When11 the value of x is written to the registers 571and 591and issued to the output 92 is delayed by IP+1 clock cycles. When10 the contents of register 59R+1is overwritten in the register 591. When21 the value of the recordings is of egistra 60R+1is overwritten in the register 601. Outputs of registers 591and 601the values of x and act on the information inputs combinational multiplier 62, the outputs of which piece x goes to one data input of the combinational adder 63, on the other information the input of which receives the contents of register 61, as a result, the output of the adder 63 is formed, the value of xi+ z. The control signal1available at the output 95 delay IP+1 clock cycles, the control signal2available at the output 96 is delayed by one clock.

The values of M IP+1 and P+1 are fed to the inputs 20 of the device and through the outputs 43 processing units 1 through 89 outputs of computational nodes 29, 30 are received respectively to the inputs of the decoders 82 and 83. In the decode values of M with the corresponding output of the decoder 82 is given a single valueiwhere i M, which opens the elements AND 66iand 80i. As a result of this information with output register 57iand trigger 64iaccordingly, through the elements AND 66iand 80iand respectively through the elements OR 74 and 81 is output on 92 and 95. In the decode values R + 1 with the corresponding output of the decoder 83 generates the e this information with output registers 58i, 59iand 60iaccordingly, through the elements AND 67i, 68iand 69iand respectively through the elements 74, 75 and 77 is fed to the outputs 92, 93 and outputs elements And 71. Thus, the device implements the possibility of solving the problems of computing a two-dimensional convolution of different dimensions for different values of I , P and Q).

The summation blocks 2(3) works as follows. When31 register 98 is reset and the output of adder 99 is formed 0+Z, where Z the contents of register 97. When30 unit summation mode is accumulating adder at the output of adder 99 is formed by the sum of the Zi+ Zi+1which is issued at the output 103 of the summation block.

Input and output data streams are specified by the following expressions.

Xklserved on exit 13 at time

t=

Valuespqserved on exit 14 at time

t to+ p Pq,

p ,

q ,

toI p(Q-1)

Values11 is input to 16 at time t=txklin other moments in time10. The value of t21 is input to 17 at time t to+ where 0, R-1. When >p20. The value of3=1 podes>3=0to+ ip + jIP + Q + V, where i , j , v .

The output 28 of the values of Yijformed at the moments t to+ iP + jIP + Q + P - 1, where i , j . The period of calculation of the elements of Yijequal (IP +Q-1)-P clock cycles. The time for solving N problems of two-dimensional convolution is NIP ( +Q-1)-NP+P+Q quanta.

Each processing unit 1 is duplication of operations performed by the computational nodes 29 and 30. The results of operations, beginning at the trailing edge of the clock signal generated at the output of the combinational adder 63 upon completion of transients in combinational circuits 62 and 63 and are issued on the outputs 94 compute nodes 29 and 30, where these results come on the corresponding input node of the comparison 31. When the coincidence of the information received at the input node 31 comparison of computational nodes 29 and 30, the processing unit 1jis considered healthy and one output node of the comparison 31 is written in the trigger 32, which is used for fixing the sign of the health of this processing unit 1j. Output trigger unit 32 is supplied to the corresponding inputs of the And elements 34, 35 and inverted inputs of elements And 33, as a result of this information with outputs 92-96 computing node 29 che was also fed to the inverse of the input elements And 33 blocks and bypass this block processing 1j. As a result, the value of g at the input 42 of the block 1j, available at the output 49 of the block 1j. A single value is given also to the output 50 of the block 1jand respectively to the output 26jsign of failure. A single signal at the output 26jdevice specifies the means of external control on the health of block 1j. If there is a mismatch of information received at the input node 31 comparison of computational nodes 29 and 30, the processing unit 1jis considered faulty, and the zero signal from the output node of the comparison 31 is written in the trigger 32. Output trigger 32 zero signal is supplied to the corresponding inputs of the And elements 34 and 35 and the inverted inputs of elements And 33, as a result of this issue with outputs 92-96 computing node 29 is blocked. Zero, the outputs of the trigger 32 is also provided on the inverted inputs of elements And 33, as a result, the flow of information in the computing nodes 29 and 30 through the elements And 34 and grant information from node 29 is blocked and offers a way of bypassing this processing unit 1j. In this case, the information coming from the previous processing unit 1j-1through the elements 33 and 36 are issued respectively by the outputs 52-56 this BL is Evoe is available at the output 50 of the block 1 and respectively to the output 26jsign of failure. Zero signal at the output 26 of the device indicates the means of external control on detection of the failure block 1j.

In order in certain situations force the display unit 1jfrom the device, use the installation log 22jdevice. In this case, the external controls on the input 22jthe device is formed of a single signal through the input 45 of the processing unit 1jis supplied to the input set to zero trigger 32. In order to force the processing unit 1jthe structure of the device, for example, after his forced withdrawal or after fixation of false rejection, using input 23jdevice. In this case, the external controls on the input 23ja signal is generated, which through the inlet 46 of the processing unit 1jis fed to the input of the installation unit of the trigger 32. Thus, the operation processing unit 1jcan be blocked by an input 25jdevice single signal. In this case, the unit via an input 25junit 1 is supplied to an inverse input element And 37, which blocks the passage of clock pulses to the clock inputs will calculate the 1 andjin the initial state at the start and restarts the device uses the input 24jdevice. For unit 1jin the initial state at the input 24jthe device is a single signal through the inlet 44 of the block 1jarrives at the inputs of the installation to its original state computing nodes 29 and 30. The input set to the initial state of the computing nodes 29 and 30 are connected to the inputs installed in the zero state of all registers and triggers nodes 29 and 30 (Fig. 3 not shown).

To the input 19 of the device is zero value for g. In the presence of intact blocks 11,1Qwith outputs 261, 26Qsigns of failure are given individual signals which are fed to the inputs of the corresponding combinational adders 41,4Q. The value of g at the input 42 of the block 1iwhere 1, Q, in the case of health blocks 11, 1i-1is i-1. In the case of the health unit 1ithis is available at the output 49 of the block 1iand is supplied to the corresponding input of the adder 4ifrom the output of which is removed is g=i, which is recorded in the register 5iand is fed to the input node of the comparison 6ion the other entrance which Postup given the value of g i. If the values match, g and Q output of the corresponding node comparison 6i given individual signal which is supplied to the corresponding input element OR NOT 11, with which a null signal is supplied to one input of the OR element 12. The coincidence of the results obtained at the outputs of blocks 2 and 3 summarize, the zero output signal from the node comparison 7 is supplied to the corresponding input of the OR element 12. The zero signals at the inputs of the OR element 12 corresponds health units 2 and 3 and the preservation of health (or health) of the line block 1 processing. In this case, the zero output signal from the OR element 12 is output 27 sign of failure. Zero signal at the output 27 of the device indicates the preservation of the health of the device in this step.

In case of failure of the unit 1TOhappens bypass this block. In the case of health the previous blocks 11, 1K-1at the output 42 of the block 1Kreceives the value of g K-1, which is passed on to the output 51 of the block 1Kwith outputs 49 and 50 of the block 1TOremoved zero values and, thus, from the output of the adder 4TOremoved zero g. As a result, the output node of the CPA is that the value of g is Q-1, output 49 of block 1Q+1given a single signal and therefore, the output of the combinational adder 2Q+1removed the value g=Q. as a result, output node 6 comparisonQ+1removed individual signal which is supplied to the corresponding input element OR NOT 11, with which the corresponding input element OR 12 is thrown zero signal. A zero value of g generated by the adder 4TOon subsequent cycles, is fed to the corresponding inputs of the elements OR 8TOand further does not affect the value of g generated at the input 42 of the block 1K+1. Thus, the processing unit 1TOderived from the computational process by bypassing, and the first of defective spare blocks, for example 1Q+1enter in the calculation process, the length of the line of well-functioning processing units of 1 device.

Upon detection of S bounce blocks 1 is bypassing the failed blocks. Let the number of the last failed block-1 line, then the output 51 of the block 1TOwill be given the value of g Q-S, which is fed to the input 42 of the block 1K+1. Because the block 1K+1is considered healthy, the output 49 of the block 1K+1issued adinin and so on, When you hit the g-values at the input 42 operable unit 1iat the output of the adder 4iformed a value equal to g+1. When you hit the g-values to the input 42 of the defective block 1iat the output of the adder 4iformed to zero, and the value of g from the output 51 of the block 1iis fed to the input 42 of the next block 1i+1the ruler. From the output of the adder 4Q+Sto the input node of the comparison 6Q+Sserved value g=0, output node 6 comparisonQ+Sgiven a single signal, which is supplied to the corresponding input element OR NOT 11. Through the open items And 10 and the elements OR 9 the result is supplied to the summation blocks 2 and 3. The coincidence of the results at the outputs of blocks 2 and 3 with inverted output node comparison 7 is given a zero signal which is fed to the input element OR 12 and, thus, output node comparison 7 is given a zero signal which is fed to the input element OR 12, and the output element OR 12 at the output 27 of the sign of failure is given a zero signal, which testifies to the truth of the issued from the output of the summation block 2 to the output of the device 28. When R<S on the outputs of the nodes comparison 6 will be zero, the output of the element OR NOT 11 Butera blocks 1. When the discrepancy between the outputs of summation blocks 2 and 3 with inverted output node 7 comparison will be given a single value, which will be transferred to the corresponding input of the OR element 12. Therefore, when R<S, or upon detection of a failure of the summation block 2(3) with the output element OR 12 at the output 27 sign of failure will be given a single value, which indicates failure.

Thus, the accumulation of R bounce processing units 1 the efficiency of the device is stored and the length of the line of well-functioning processing units 1 device remains constant. Upon detection of (R+1)-th failure or refusal of the summation block 2(3) from the output 27 of the device is given a sign of failure, which then enters the external controls.

When the device is unlocked backup processing units 1 automatically operate in a control mode duplication. In this case, the inputs of the first processing unit 1pwhere R Q+1, which are in reserve, with the operating range of the device receives the calculated value. As a result of processing this value in the compute nodes 29 and 30 and the subsequent comparison of the results of inasea use these backup processing units 1pwill occur, taking into account their health.

Consider the operation of the device for a specific case I P Q 2 and R 1. Organization of input and output data streams is given by the expressions:

to4

t= 4+

t= 4+p-Pq, p , q

t txkl< / BR>
t 4 + ; = 0,1;

t 1 6 + 2i + 4j; i, j 0, 1

t 7 + 2i + 4j, i, j 0, 1.

Organization of input and output data flows, control signals, the contents of the triggers and registers, the values generated at the output of the combinational adder processing units 11and 12shown in the table. 1 and 2. In table. 3 describes the operation of summation blocks 2(3) for the case in question.

May 8th cycle of the device detected the failure processing unit 12. In this case, the organization of the input and output data flows, control signals, registers, and triggers and values generated at the output of the combinational adders processing units 11, 12and 13shown in the table. 4-6.

Also t 8 detected failure of the unit 12at step t 9 lock block 12(further information under its nodes does not affect the remainder of the process) and zeroing block 11at step t 10 previsualise bypass block 12and included in the backup unit 13. The length of the ruler of the device remains the same.

A possible algorithm for the recovery process after a failure is detected, block 1jinvolves the following steps:

cycle i: the fixing block 1jwith the detected failure, the lock block 1jreading information from block 1j+1in block 1j+2, zeroing block 1j+1and locking block 1j+1.

cycle i+1: read data from block 1j+2in block 1j+3, lock, and reset block 1j+2zeroing blocks 11,1j-1.

cycle i+2: read data from block 1j+3in block 1j+4, lock, and reset block 1j+3, unlock block 1j+1.

cycle i+3: read data from block 1j+4in block 1j+5, lock, and reset block 1j+4, unlock block 1j+2.

cycle i+K: reading information from block 1j+k+1in block 1j+k+2, lock, and reset block 1j+k-1.

If tntime (number of cycles) required to prepare for the restart of the device by means of external control, the time reinit line will be j + tnstrike is that with the help of external control apparatus or environment.

Due to technological crystal structure of IP health or failure of its various fractions are interrelated. The degree of connection between the failures of different shares the IP is measured by the correlation coefficient, the value of which is greater than the higher level of technology and the degree of integration of IP. The presence of not less than 16-bit multiplier 62 Raman-type adders 63 and 99 Raman type and groups of registers 57-60, registers 61, 97 and 98 cause the degree of integration and the level of technology, sufficient for the manifestation of a high degree of correlation of failures. When the control duplication of computational nodes need to bounce these nodes were independent. For this purpose, nodes 29 and 30 of the processing unit 1, and the summation blocks 2 and 3 were implemented on different crystals of IP. Similarly, on the basis of the correlation of failures inside the crystal IP, you need to excess or redundant processing units 1 did not appear on some crystals of IP together with the workers.

Technical and economic effect of the proposed device is as follows.

In the proposed device is continuous hardware monitoring throughout time and block the more complete hardware control, focused on the detection of all types of failures, the time control is comparable with a clock period. Reliability operation processing unit systolic device will be determined as: Dcp(t) PCR(t) + P0,0(t), where RCR(t) the probability of correct operation of the processing unit 1,

P0,0(t) the probability of correct operation of the processing unit 1 and issuing from the outlet 50 of the block 1 signal failure.

For the considered systolic devices

PCR(t) PU32(t)

P0,0(t) 2PU3(t)(1-PU3(t)), where RU3(t) the probability of trouble-free operation of the computing node 29 and 30.

The reliability of operation of the device is determined by the expression:

Dcf(2PU3(t) PU32(t))Q. When Ruz(t) 0,99, Q 3 Dcf0,996,

Puz(t) 0,99, Q 10 Dcf0,9891,

Puz(t) 0,999, Q 3 Dcf0,999997,

Puz(t) 0,999, Q 10 Dcf0,999989,

Puz(t) 0,9999 and above Dcfalmost equal to 1.

The recovery time of the computational process (obtaining the reliability of the output device) is proportional to the value of nOTCwhere nOTCQ, nOTCminimum nomerami CONVOLUTION, containing from first to Q-th processing units, each of which contains the first compute node, and information inputs of the first and second groups, the first and second control inputs connected respectively to the information inputs of the first and second groups, the first and second control inputs of the first processing unit outputs the first and second groups, the first and second outputs of the i-th processing unit (where i=1, Q 1) are connected respectively to the information inputs of the first and second groups, the first and second control inputs of the (i + 1)-th processing unit, the clock input devices are connected to the clock inputs of the processing units from the first to Q-th, characterized in that it introduced with (Q + 1)-th to L-th processing units, where L Q + R, R the number of redundant processing units, the first and second summation blocks, L adders, L 1 registers, a group of L sites comparison site compare with the first (L + 1)-th group elements, OR L groups of elements And the element OR NOT and item OR moreover, the outputs of the first and second groups, the first and second outputs of the j-th processing unit (where j Q, L 1) are connected respectively to the information inputs of the first and second groups, the first and second control inputs (j + 1)-th processing unit, a clock input impul is ICI-read registers the information inputs of the third group are connected respectively to the information inputs of the third group of the first processing unit outputs the third group of the K-th processing unit (where K=1, L 1) are connected respectively to the first inputs of elements And K-th group and respectively to the control inputs of the first group (K + 1)-th processing unit outputs the third group of L-th processing unit connected respectively to the first inputs of elements And L-th group, the control inputs of the first group are connected respectively to the control inputs of the first group of the first processing unit, the outputs of the fourth group of the K-th processing unit connected respectively to the first inputs of the elements OR the K-th group, the outputs of which are connected respectively to the control inputs of the first group (K + 1)-th processing unit, the outputs of the fifth group of l-th processing unit (where l=1, L) are connected respectively to the information inputs of the group of l-th combinational adder, the outputs of the K-th combinational adder connected respectively to the information blocks of the K-th register and respectively to the inputs of the first group of the K-th node of the comparison, the outputs of the L-th combinational adder, the outputs of the K-th combinational adder connected respectively to the I is the shining inputs of the second groups of processing units from the first to the L-th and the inputs of the second group of nodes comparison groups, the output of the l-th node of the comparison group connected to the second inputs of elements And l-th group and the l-th input element OR NOT, the output of which is connected to the first input member OR the output of which is connected to the output of the sign of failure, the outputs of the K-th register connected respectively to the second inputs of the elements OR the K-th group, the third output of the l-th processing unit connected to the information input of the l-th adder and the l-th output group characteristic failure of the device, the third control input of which is connected to the control inputs of summation blocks, the outputs of the elements And groups from the first to the L-th connected respectively to the inputs of the elements OR L-th group, the outputs of which are connected to information inputs of summation blocks, the outputs of the first summation block connected to the outputs of the devices and the inputs of the first group (L + 1)-th node comparison, the inverted output of which is connected to the second input of the OR element, the outputs of the second unit summation connected respectively to the inputs of the second group (L + 1)-th node comparison, the l-th input set of the first group, the l-th input set of the second group, l-th input set of the third group and the l-th entry lock devices are connected respectively to the first, second, and third inputs usteal node, node comparison, the trigger, the first to the third element nodes And node elements OR element And, with each processing unit of the information inputs of the first, second and third groups, the first and second upravljajushhie inputs and control outputs of the first group unit connected respectively to the inputs of the group of the first node elements And the inputs of the second node elements And the outputs of the first group of the first node elements And connected respectively to the inputs of the first group of node elements OR whose outputs are connected respectively to the outputs of the first group, second group, third group, the first and second outputs of the block, the outputs of the first group to the second node elements And connected to information inputs of the first group, second group, third group, the first and second control inputs of the first and second computing nodes, the outputs of the first, second and third groups, the first and second outputs of the first computing node connected to the inputs of the first group of node comparisons and input group of the third node elements And whose outputs are connected respectively to the inputs of the second group of node elements OR, the outputs of the first, second and third groups, the first and second outputs of the second computing node connected respectively to the th is connected to the input of the third node elements And, a third output of the processing unit, the inverse input of the first node elements And the input of the second node elements And the outputs of the second groups of the first and second nodes And connected respectively to the outputs of the fourth and fifth groups, control inputs of the second group of processing unit connected respectively to the control inputs of the group of the first compute node and the control input group of the second computing node, the first and second inputs of the installation processing unit connected respectively to the inputs setup to "0" and "1" of the trigger, the third input set processing unit connected to the inputs of the installation to its original state of the first and second computing nodes, clock input and the input block processing unit connected respectively to the first and second (inverse) input element And the output of which is connected to the clock inputs of the first and second computing nodes and trigger.

2. The device under item 1, characterized in that each block summation contains two registers and combinational adder, and the clock input of the summation block is connected to the inputs of the recording-reading out of the first and second registers, the outputs of which are connected respectively to the information inputs of the adder, the outputs will also have a control input of the summation block is connected respectively to the information inputs of the first register and setup in the "0" of the second register.

3. The device according to p. 1, wherein each compute node contains four groups of registers, the register, the multiplier and the adder, trigger group, trigger, M + 3P + 7 groups of elements And, where M=IP + 1, six groups of elements OR element And a element OR two decoder, and information inputs of the first group of compute nodes connected to information inputs of the first register of the first group and the first inputs of elements And the first group, the outputs are connected to first inputs of elements OR first group, the outputs are connected to information inputs of the first register of the second group, the outputs of the m-th register of the first group (where m=1, M-1) connected to information inputs (m+1)-th register of the first group and the first inputs of elements And (m+1)-th group, the outputs of the elements And groups second (M+1)-th connected to respective inputs of the elements OR the second group, the outputs of which are connected to the outputs of the first group of compute nodes, the information inputs of the second group which is connected to information inputs of the first register of the third group and the first inputs of elements And (M + 2)-th group, the outputs are connected to first inputs of the elements OR the third group, the outputs of which are connected to the information whoda the first group of the multiplier, the first inputs of elements And (M + 3)-th group and the information inputs of the second register of the second group, the outputs of the n-th register of the second group (where n 2, P) is connected to information inputs of the (n+1)-th register of the second group and the first inputs of elements And (M + 2 +n)-th group, the outputs of the elements And groups with (M+3) th to (M + 3+ P)-th podklucheni to respective inputs of the elements OR the fourth group, the outputs are connected to first inputs of elements And (M+P+4)-th group, the outputs of which are connected respectively to the second inputs of the elements OR of the first group, the outputs of the S-th register of the third group (where S= 1, P) is connected to information inputs (S + 1)-th register and the first input element And (M + P + 4 + S)-th group, o (P + 1)-th register of the third group are connected to first inputs of elements And (M+2P+5)the second group, the outputs of the elements And groups with (M+P+5) th to (M+2P+5)-th connected to respective inputs of the elements OR the fifth group, the outputs of which are connected respectively to the outputs of the second group of compute nodes, the outputs of the first register of the fourth group are connected to first inputs of elements And (M+2P+6)-th group of information inputs of the second register of the fourth group of information inputs of the second multiplier, the outputs of which are connected respectively to the info the dust computing node, the information inputs of the third group which are connected respectively to the information inputs of the register whose outputs are connected respectively to the information inputs of the second adder, the outputs of the r-th register of the fourth group (where r= 2, P) is connected to information inputs (r + 1)-th register of the fourth group and the first inputs of elements And (M + 2P + 6 + r)-th group, the outputs of the elements And groups with (M + 2P + 7)-th through (M + 3P + 7)th is connected to the corresponding inputs of the elements OR the sixth group, the outputs of which are connected respectively to the first inputs of elements And (M + 3P + 8)-th group, the outputs of which are connected respectively to the second inputs of the elements OR the third group, the first control input device connected to the second inputs of elements And the first group, the second (inverted) inputs of elements And (M + P + 4)-th group and the information input of the first trigger group, the output of the V-th flip-flop group (where V=1, M-1) connected to the information input (V + 1)-th flip-flop group and the first input of the V-th element And the outputs of the elements And first to M-th connected respectively to the inputs of the OR element, the output of which is connected respectively to the inputs of the OR element, the output of which is connected to the first output of the computing node, the second driving is+ 8)-th group and the information input trigger the output of which is connected to the second output of the computing node, the control inputs of the group from the first to a-th (where a=log2M) which are connected respectively to the inputs of the first decoder, the i-th output of which (where i=1, M) is connected to the second inputs of elements And (i + 1)-th group and the second input of the i-th element And the control inputs of the group (a+1)-th through H th [where H is a log2(P + 1] compute node connected to the inputs of the second decoder, the j-th output of which (where j= 1, P + 1) is connected to the second inputs of elements And (M + P + 4 + j)-th group, (M + 2 + j)-th group m (M + 2P + 6 + j)-th group, the clock input of the computing node is connected to the clock inputs of registers and triggers, the input set to the initial state of the computing node connected to the inputs setup to "0" all registers and flip-flops.

 

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