Device for programming flash memory

 

(57) Abstract:

The invention relates to automatic control and computer engineering, in particular to a device write binary information into permanent memory chip with ultraviolet erasing and fused jumper. The device comprises a block 1 of the pair, the information input-output 2, input 3 connection unit, the imaging unit 4 control signals, matching a four-channel receiver 5 signals, control inputs 6 9, matching single-channel transmitter 10 signal synchronizes the output 11, the selector decoder 12, a register 13, the block elements And 14, the element OR 15, the delay element 16, the trigger 17, block 18 of delay elements, the first 19 and second 20 registers, programmable source 21 of the power unit 22 keys, programming, block 23 address key block 24 key management the outputs 25 and 27. The programming cycle of the memory chips consists of operations preliminary control, recording information in the memory cell and the output of the control record. 2 Il.

The invention relates to automatic control and computer engineering, in particular to a device write binary information into permanent memory chip with ultraviolet erasing, so skim to the invention is a device for programming flash memory, containing driver control signals, the first outputs of which are the control inputs and the first output clock, the second outputs control outputs of the device, the first and second registers, the interface block, the inputs and outputs of which are information input-output device, the output interface block connected to the first inputs of the first and second registers, the second inputs of the driver control signals, the third and fourth outputs of which are connected to second inputs of the first and second registers, respectively, the second inputs of the interface block connected to the outputs of the first register and the address are output devices [2]

A disadvantage of this device is the limited class of programmable memory chips due to the lack of choices necessary voltages corresponding to the recording mode different class of memory chips. The invention extends the application of the device by increasing class of programmable memory chips.

In Fig.1 presents a functional diagram of the device for programming of Fig.2 timing diagrams of the signals at the inputs of the device during one cycle management e inputs-outputs 2, inputs 3 connection unit, the imaging unit 4 control signals, consisting of a matching four-channel receiver 5 signal inputs 6-9 which are control inputs of the device, matching single-channel transmitter 10 signal output 11 which is synchronizing the output device selector-decoder 12, a register 13 block 14 And the OR element 15, the delay element 16, the trigger 17, block 18 of delay elements whose outputs are the control outputs of the shaper 4 control signals, the first 19 and second 20 registers, programmable source 21 of the power unit 22 keys programming unit 2 address keys, block 24 keys control outputs 25-27. The operation of the device for programming is carried out using a device (not shown) generating and reading sixteen-bit binary code and five pulse control signals. All signals must be synchronized with each other. In particular, this control device can serve as a microcomputer, to which examines the operation of the device for programming. In this case, as the synchronization signal used by the signal output device 11, FD is a single-channel transmitter 10 signal shaper 4.

Device for programming works as follows.

After inclusion of all the elements of the device are set in the initial state, and the trigger 17 is set in one state. 2 unit 1 pair at time 1 (Fig.1) is supplied from the control unit 16 bit binary address code, which is output from the transceiver is fed to the inputs of register 20 and its byte to the input of the selector decoder 12 and contains the code of the grounds of appeal to this unit.

At time t2input 8 5 receiver pulse signals supplied to the clock pulse from the control unit, a negative front of this signal is recorded in the register 13 output status selector-decoder 12, and the register 20 binary address code. As a result, the output of the register 13 to the input of block elements And 14 signal resolution signal 6 and 7 on the control input unit 1 pair, to the input of the OR element 15 will follow the signal to the input of delay element 16 to generate sync and transfer it through the transmitter 10 to the control device. At time t3on bus 2 unit 1 passes the information to be written into the register 19 and 1. Negative front of this signal is recorded in the register 19 lower byte of information to be written into the cells of the permanent memory and the register of the source 21 of the high byte of information that sets its outputs are a set of highly stable voltage needed to supply the chip when recording information. Installed on the 26 outputs the addresses of the cells by using the register 20 and the block 23 of the address keys of the cell case 19 opens one or more bit keys programming unit 22, setting the outputs 25 required level voltage and outputs 27 using block 18 and block 24 keys control electric power in accordance with the requirements of the programming manual. At time t5on the input 9 of the receiver 5 signal reset, which sets the trigger 17 in one state, and the device is ready to record the information at the following address or control of recorded information. The control content of the memory chips is performed on the signal received at the input 6 at time t4instead of a signal 7. The input 6 through the receiver 5 and the block elements And 14 is fed to the input unit 1 pair and manages p. the memory consists of preliminary operations (input) control, recording information in the memory cell and the output of the control record. In the beginning of the cycle, it reads information from the memory chips according to a fixed address. Then alternate install all of the addresses in the memory chip and read information on each address. The results of the input control is displayed, for example, on the video display and the decision on further use of the memory chips.

The operation of recording information starts with a consistent set cell address at the outputs 26, setup data lower byte of information at the outputs 25 to be written to the cell by the set address and the installation of electric mode signals at the outputs 27 in accordance with the requirements of the programming manual.

The control circuits after recording the information (output control) is equivalent to the input control.

DEVICE FOR PROGRAMMING flash MEMORY that contains the driver control signals, the first input of which is a control input and first output clock output devices, the first and second registers and the interface block, the inputs and outputs of which are INFI inputs of the registers and the inputs of the group of driver control signals, the second and third outputs of which are connected respectively to the inputs of the write-enable the first and second registers, and the fourth output driver control signals connected to the first input of the interface block, the first and second inputs of the driver control signals are inputs resolution recording device, the third input is synchronator, and the fourth input of the reset device, characterized in that it introduced the block address of the keys, unit keys, programming, block key control, programmable power supply, the inputs of which are connected to the corresponding outputs of the interface block, the first input of the programmable power source connected to the second output driver control signals, the first and second outputs programmable power source is connected to the control inputs, respectively, of the block address keys and unit keys programming, and the third and fourth outputs programmable power source connected to the first and second control inputs of the unit key management information the input of which is connected to respective outputs of the driver control signals, and the outputs are the control output device outputs the second address are the outputs of the device, the outputs of the first register connected to the corresponding information input unit key programming whose outputs are connected to respective inputs of the interface block and are informational outputs of the device.

 

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