# Device for error correction of fibonacci p-codes

(57) Abstract:

The invention relates to computer technology and can be used for error correction. The technical result is to increase speed. It is due to the fact that the device includes first and second elements And p 2 groups of elements And n 3p groups of elements And p 2 groups of elements And a group of n p 2 XOR and relevant links. The device can be used to build highly reliable electronic storage and processing of information in systems with high demands on reliability and can also be used in systems with a high level of noise. 1 Il.

The invention relates to computer technology and can be used for error correction of Fibonacci p-codes.

A device for control of the Fibonacci p-code containing a n-bit register, the element OR n-p units of fixation failure [1] the Disadvantage of this device is its low noise immunity.

The closest in technical essence to the present invention is a device for correction of single errors of Fibonacci p-codes [2] containing elemets information input device, and outputs information output devices, a second group of n-p-2 elements And the third group of n-p-3 elements OR outputs Junior p bits are connected to the corresponding inputs of the OR element whose output is the error output device, the output of the i-th digit of the n-bit register (i=p+2,n) connected to the first input (i-p+1)-th element And the first group and the j-th input (i-p-2+j)-the first element OR the second group (j=1,p), the output of the k-th (k=1, n-p-3) element OR the second group is connected to the second input of the (k+1)-th element And the first group of output (p+1)-th digit of the n-bit register connected to the second input of the first element And the first group, the outputs of the elements And the first group are connected to respective inputs of the element OR the reset inputs (p+1)th and n-th bits of the n-bit register is connected to the reset input of the device, the output of the i-th element (i=1,n-p-3) And the first group connected to the first input of the corresponding element And the second group and the j-th (j=1,p) input (i-j)-th element OR the third group, the output of which is connected to the second input of the corresponding element And the second group, the output of the last element And the first group is connected to the second input of the last element And the second group, the output of the k-th element And the second group (k=1,n-p-2) connected to the first input (k+p outputs of the first p bits of the n-bit register connected to the first inputs of the respective elements OR the first group, the outputs are connected to the reset inputs of the respective bits of the n-bit register, a second input elements OR the first group is connected to the reset input of the device. A disadvantage of the known device is low speed.

The technical objective of this invention is to improve performance.

This objective is achieved in that the device containing the group of elements OR, further comprises first and second trehochkovye elements And p-2 groups of (k+2) trehshipovyh elements And (k=1,p-2), n-3p groups of (p+1) trehshipovyh elements And p-2 groups of (n-p-m-1) trehshipovyh elements And (m= n-2p-1,n-p-4) and the group of n-p-2 XOR, and the first input of each [(k- ) b+c]-th (b=o. k; c=b+1,k+1) Tregubova element And the k-th group is connected to (p+b+1)-th input of the second input of this element is connected with (2p+c+1)-th input device, and a third input of C (p+k+2)-th input device, the first input of each [(p-)i+j]-th (i=0,p-1; j= i+1, p) Tregubova element And the l-th group (l=p-1,n-2p-2) is connected to (l+i+2) th input of the second input of this element is connected to (l+p+j+2)-th input device, and a third input of C (p+l+2)-th input device, the first input of each [(n-p-m-3-)d+e] (d=0, n-p-m-3; e=d+1,n-p-m-2) Tregubova element And the m-th group is connected+2)-th input device, outputs trehshipovyh elements And each r-th group (r= 1,n-p-4) combined with the respective element OR the output of which is connected to the first input (r+1)-th EXCLUSIVE OR element, a second input connected to (r+p+2)-th input device inputs the first Tregubova element And connected respectively with (p+1)-m (2p+2)-th and (p+2)-th inputs of the device, and the inputs of the second Tregubova element And connected respectively with (n-p-1)-th, n-th and (n-1)-th inputs of the device, the outputs of the first and second trehshipovyh elements And are connected respectively to the first inputs of the first and (n-p-2)-th XOR, the second inputs of which are connected respectively with (p+2)-th and (n-1)-th inputs of the device, the outputs of XOR are information output device, p+1 Junior and n-th inputs of the device are simultaneously and outputs.

Any natural number n-bit Fibonacci p-code is presented in the form of a polynomial

Aasp(s), (1) where

as0,1}

p(S)-p-Fibonacci number (p=0.1.)

p(s)=

A method of correcting errors in S-m category describes a Boolean function:

I(s)0-1= a(s-p+i)a(s)a(s+j)(2) where a(s)binary coefficient S-th digit;

The drawing shows a diagram of the device for p=2 and n=8. It should be noted that since the p least significant bits of the code are not processed by the device, the two low-order code of the device is excluded.

The proposed device comprises a first group trehshipovyh elements And 1.1-1.3, the second group trichotomy elements And 2.1-2.3, the first and second trehochkovye elements And 3.4, group of items OR 5.1, 5,2, group of XOR 6.1-6.4, the group of information inputs 7 and the group of information outputs 8 devices. The first and second groups trehshipovyh elements And 1.1-2.3, the first and second trehochkovye elements And 3.4 are used to form signals, error correction, and a group of elements OR 5.1, 5.2 is intended to combine these signals. The group of XOR 6.1-6.4 is designed to correct mistakes at the inputs 7 and forming the correct code combination at the outputs 8 of the device. The input elements to satisfy the criterion of "substantial differences".

The device operates as follows. Assume that the input device filed representation of the number 5 in binary Fibonacci 00100100. This combination, when the corresponding inputs of elements And 1.1-2.3, 3,4, or in odno from the outputs of the elements And 3.4 is supplied to the first inputs of the respective XOR 6.2, 6.3, 6.1, 6.4, on the second inputs of which are controlled potentials code, which in this case are part of the output device without modification. Suppose that in the fourth discharge failure-type move "0" to "1" and code combination has been 00110100. In this case, the work item And 3, since all of its inputs submitted singular potentials, respectively, of the third, sixth and fourth digits. A single potential from the output element And 3 is supplied to the first input of the EXCLUSIVE OR element 6.1, to the second input of which receives a "1" distorted fourth grade. At the output of the EXCLUSIVE OR element 6.1 appears zero potential, which will be held on the output device, fixing thus the failure. Similarly corrected and failure in the fifth grade. In this case, the triggered element And 1.1, and "1" through the OR element 5.1 is supplied to the first input of the EXCLUSIVE OR element 6.2, where and corrects the failure of the fifth grade. If controlled code combination had the appearance 00100010, the failure of the fifth grade will trigger element And 1.2, and then similarly through the element OR 5.1 operation of the EXCLUSIVE OR element 6.2. The same will be fixed crash fifth grade if the code combination are the ability of the known device to fix some single bug-type move "0" to "1". Increased performance is achieved by reducing the number of intermediate elements.

The proposed device can be used to build highly reliable electronic storage and processing of information in systems with high demands on reliability and can also be used in systems with a high level of noise.

DEVICE FOR ERROR CORRECTION of FIBONACCI P-CODES containing the group of elements OR, characterized in that it contains two elements And p 2 groups of elements And (K 1, p 2), n 3p groups of elements And P 2 groups of elements And (m n 2p 1, n p 4), and a group of n p - 2 XOR, and (p + b + 1)-th input device connected to the first input of each element And the k-th group (b 0, k, c, b + 1, k + 1), second and third inputs of which are connected respectively with (2 p + c + 1)-th and (P + K + 2)-th inputs of the device, (l + i + z)-y log (l p 1, n 2p 2) connected to the first input of each element And the l-th group (i 0, p 1; j i + 1, p) the second and third inputs of which are connected respectively with (l + p + j + 2)-th and (p + l + 2)-th inputs of the device, (m + d + 2)-th input (d 0, n p m -3) connected to the first input of each element And the m-th group (s d + 1, n p m 2), second and third inputs of which are connected respectively with (n p + s + 1)-PI, the output of which is connected to the first input (r + 1)-th EXCLUSIVE OR element group, a second input connected to (n + p + 2)-th input of the (p + 1)-th, (2p + 2)-th and (p + 2)-th inputs of which are connected with inputs of the first element And the input of the second element And is connected to the (n p 1)-th, n-th and (n-1)-th inputs of the device, the outputs of the first and second elements And are connected respectively to the first inputs of the first and (n p 2)-th XOR, the second inputs of which are connected respectively with (p + 2)-th and (n-1)-th inputs of the device, the outputs of XOR group, (p + 1)-th Junior inputs and the n-th inputs of the device are the outputs of the device.

Same patents:

The invention relates to computer technology and can be used for error correction

The invention relates to telecommunication and can be used in high-voltage modems for forming surtace-coded signals

The invention relates to telecommunication and can be used in high-speed modems for encoding information signals convolutional code

The invention relates to computer technology and can be used in systems noiseless coding and decoding, in particular in the optical disk storage devices

The invention relates to data transmission systems for communication channels and can be used in devices for decoding by the Viterbi algorithm

The invention relates to computing

Encoder // 2033691
The invention relates to computing

The invention relates to computing and data transmission and can be used to control structural codes

The invention relates to computing and communications

The invention relates to a device for the transmission of discrete data and can be used in systems of automatic locomotive alarm, Autolock and other devices of railway automatics

FIELD: Witterby algorithm applications.

SUBSTANCE: system has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.

EFFECT: higher efficiency.

2 cl, 9 dwg

FIELD: communications engineering.

SUBSTANCE: proposed device and method for mobile code-division multiple access communication system including device for transferring channel of backward-link transmission speed indicator afford generation of optimal code words ensuring optimal coding for all types of coding procedures from optimal type (24.1) up to optimal coding procedure 24.7 and supporting all optimal-coding devices.

EFFECT: optimized capacity.

74 cl, 21 dwg, 44 tbl

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communication systems.

SUBSTANCE: method includes generating sets of sub-codes of quasi-additional turbo-codes with given encoding speeds, and given sub-codes are reorganized as a set of sub-codes with another encoding speed for use in next transfer of sub-code with given encoding speed.

EFFECT: higher efficiency.

9 cl, 13 dwg

FIELD: data transfer technologies.

SUBSTANCE: method includes segmentation of length N of quasi-complementary turbo-codes on preset amount of sections, determining identifiers of sub-code packets appropriate for segmented portions, setting of said packets separated for initial transfer of sub-code, calculation of number of remaining symbols in form N-Fs, where N - length of quasi-complementary turbo-codes, and Fs - position of start symbol of sub-code of quasi-complementary turbo-codes, determining position of symbol of remaining symbols in amount equal to sub-codes amount, which have to be sent and serial transfer of sub-code symbols from position of starting symbol Fs to position of last symbol Ls.

EFFECT: higher efficiency.

5 cl, 17 dwg

FIELD: communications engineering.

SUBSTANCE: method includes selecting one combination among given combinations, appropriate for several or every generated symbols of code word to transmit generated symbols of code word with length of sub-packet, determined in accordance to data transfer speed, information, appropriate for data transfer speed, is read, also based on length of sub-packet and chosen combination, from a table, wherein identification information, pointing at data transfer speed, sub-packet length and selected combination, is, is previously displayed for given information, and generated code word symbols are transmitted in accordance to read information and in accordance to selected combination.

EFFECT: possible check transmission of information by means of hybrid automatic repeat query for increasing carrying capacity during high-speed information transfer.

4 cl, 16 dwg, 6 tbl

FIELD: communications engineering; simulating digital communication channels with separate and grouping errors.

SUBSTANCE: proposed method includes evaluation of set of communication channel states S0,S1, ..., Sm - 1 and calculation of conditional error probabilities P(e/s) in each state s" i = 0, ..., m - 1 of communication channel, and error acquisition in communication channel in compliance with conditional error probability for current state of communication channel; in the process probability of error-free interval p(0i) of i bits is found, and conditional probabilities p(0i1/11), p(0i1/01) of error-free intervals of i bits are calculated with respect to them basing on probabilities p(0i) and using recurrent rules during each current time interval and preceding one on condition that for error generation use is made of two states of communication channel corresponding to combination of errors 11 or 01; random number p uniformly distributed within interval between 0 and 1 is generated; conditional probabilities p(0i1/11), p(0i1/01) are summed up starting from i = 0 resulting in sequence 0k1 that constitutes bit-by-bit stream of communication channel errors.

EFFECT: enhanced speed.

1 cl, 1 tbl

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: coding in communication systems.

SUBSTANCE: proposed partial reverse bit-order interleaver (P-RBO) functions to sequentially column-by-column configure input data stream of size N in matrix that has 2m lines and (J - 1) columns, as well as R lines in J column, to interleave configured data, and to read out interleaved data from lines.

EFFECT: optimized interleaving parameters complying with interleaver size.

4 cl, 7 dwg, 3 tbl