Device for error correction of the i-codes fibonacci

 

(57) Abstract:

The invention relates to computer technology and can be used for error correction. The technical result is achieved due to the fact that the device contains five elements And the five elements BAN with corresponding connections. The device can be used to build highly reliable electronic storage and processing of information in systems with high demands on reliability, as well as in systems with a high level of noise. 1 Il.

The invention relates to computer technology and can be used for error correction of Fibonacci P-codes.

A device for monitoring fibonacii p-code containing a n-bit register, the element OR n-p units of fixation failure [1] the Disadvantage of this device is its low noise immunity.

The closest in technical essence to the present invention is the device [2] for the correction of single errors of Fibonacci p-codes containing the elements OR the first and second groups, the n-bit register n-bit code), single input bits which are information the device inputs and outputs: Junior p bits are connected to the corresponding inputs of the OR element, the output of which is the error output device, the output of the i-th digit of the n-bit register (i=p+2,n) connected to the first input (i-p+1)-th element And the first group and the j-th input (i-p-2+j)-th element OR the second group (j=1,p), the output of the k-th (k=1,n-p-3) element OR the second group is connected to the second input of the (k+1)-th element And the first group of output (p+1)-th digit of the n-bit register connected to the second input of the first element And the first group, the outputs of the elements And the first group are connected to respective inputs of the element OR the reset input (p+1)-th and n-th bits of the n-bit register is connected to the reset input of the device, the output of the i-th element (i-th,n-p-3) And the first group connected to the first input of the corresponding element And the second group and the j-th (j=1,p) input (i-j)-th element OR the third group, the output of which is connected to the second input of the corresponding element And the second group, the output of the last element And the first group is connected to the second input of the last element And the second group, the output of the k-th element And the second group (k=1,n-p-2) connected to the first input (k+p-th element OR the first group, the output of which is connected to the reset input (k+P+1)-th digit of the n-bit register, the outputs of the first p-bits of the n-bit register connected to the first inputs sootvetstvo register, second input elements OR the first group is connected to the reset input of the device. A disadvantage of the known device is low speed.

The technical objective of this invention is to improve the performance of your device.

This objective is achieved in that for the case p=1 and n=8 device containing from one to five elements, And further comprises first to fifth element PROHIBITION, and the first input of each of the k-th (k=1,5) element And is connected to the k-th input device, the second input of each of the k-th element And connected to the (k+1)-th input device, the third input of the k-th element And connected to the (k+2)-th input device, the output of each of the k-th element And is connected to an inverted input of the corresponding k-th element of the BAN, the direct input of which is connected to the (k+1)-th input device, the output of the k-th element of the BAN is (k+1)-th output device, the first and seventh inputs of the device are simultaneously relevant outputs of the device.

Any natural number n-bit Fibonacci code is represented in the form of the polynomial A Asp(s) (1) where asE{0,1} p(S)p-Fibonacci number (p= 0.1.)

p(s)=

A method of correcting errors in S-m category describes a Boolean memory function-other Fe>/BR>I(s)0-1individual signal error correction type switching "On" to "1"

i=0,p-1; j=i+1; p

The invention consists in the realization of the formula (2) for p=1 and n=8. It should be noted that, since the p least significant bits of the code are not processed by the device, one least significant bit of device is excluded.

The drawing shows a diagram of the device.

The proposed device contains trehochkovye elements And 1.1-1.5, BAN items 2.1-2.5, information 4 inputs and information outputs 5. Trehochkovye elements And 1.1-1.5 are used for generating signals error correction, and the BAN items 2.1-2.5 for correct mistakes on inputs 4 and forming the correct code combination at the outputs 5 of the device.

The input elements to satisfy the criterion of "substantial differences".

The device operates as follows. Assume that the input device filed representation of the number 12 in 2-Fibonacci code 00101010. This combination, when the corresponding inputs of elements And 1.1 to 1.5 in any case does not give the output elements And a single potential, i.e. "About" from the outputs of the elements And 1.1 to 1.5 is supplied to inverted inputs of elements PROHIBITION 2.1 to 2.5, the direct inputs of which the th. Suppose that in the third category of failed type switching "On" to "1" and code combination got kind of 00101110. In this case, the work item And 1.1, since all of its inputs submitted singular potentials, respectively second, third and fourth digits. A single potential from the output element And 1.1 is supplied to an inverse input element PROHIBITION 2.1, the direct input of which receives a "1" distorted the third category. The output element PROHIBITION 2.1 appears zero potential, which will be held on the output device, fixing thus the failure. Similarly corrected and failure in the fifth grade. In this case, the triggered element And 1.3 and "1" is supplied to an inverse input element PROHIBITION 2.3, where and corrects the failure of the fifth grade. Thus, the proposed device is fully preserves the ability of the known device to fix some single bug-type move "0" to "1". Increased performance is achieved by reducing the number of intermediate elements. The proposed device can be used to build highly reliable electronic storage and processing of information in systems with high demands on reliability, as well as in systems with wysowa And characterized in that it contains five elements BAN, and the first input of the k-th element And is connected to the k-th information input device, (k + 1)-th information the input of which is connected to a second input of the k-th element, And a third input connected to the (k + 2)-th information input device, the output of the k-th element And connected to the negative input of the k-th element of the BAN, the direct input of which is connected to the (k + 1)-th information input device, the outputs of all elements of the BAN, the first and seventh information the device inputs are the outputs of the device.

 

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