A method of manufacturing structures of p-channel mos lsi
(57) Abstract:Usage: microelectronics, manufacturing technology p-channel MOS LSI with a high voltage level. The essence of the invention: in the manufacture of structures of p-channel MOS LSI on a silicon substrate is applied layers oxidan silicon nitride, forming a mask on the active areas, conduct protivodiversionnaya doping is grown in the field layer of silicon oxide, form a photoresistive mask to remove the silicon nitride from the active diffusion regions, alloyed active diffusion area and oxidize its surface to form a gate dielectric, create the contact metallization and interconnects. The method allows to increase reliability and to extend the scope of BIS by increasing the breakdown voltage Pastorova layer of silicon oxide. The invention relates to microelectronics, and is intended for the manufacture of p-channel MOS LSI with a high voltage level.A known method of manufacturing structures of the p-channel MOS LSI, comprising applying to the silicon substrate layer of silicon oxide and silicon nitride, the opening in the layer of silicon nitride Windows on the field and the active region is of Blasta, not protected by the nitride mask, forming a photoresistive mask, the doped diffusion regions, the cultivation of field and diffusion regions of a thick layer of silicon oxide, the etching of silicon nitride and the establishment of contact metallization and interconnects. The disadvantage of this method is the formation of a thick silicon oxide both on the field and active regions. It is not possible to create a thick layer of field oxide of silicon, since the oxidation occurs segmentation impurities growing oxide layer, which leads to a considerable decrease in the conductivity of the active regions.The closest technical solution is a method for manufacturing structures of the p-channel MOS LSI, comprising applying to the silicon substrate layer of silicon oxide and silicon nitride, the opening in the layer of silicon nitride Windows only over the field regions, protivodiversionnaya doping field areas, the growing field of silicon oxide, the removal of silicon nitride, forming a photoresistive mask, doping the active diffusion regions, forming a layer of gate silicon oxide, creating a contact metallization and interconnects. This method allows SF is a high build field and active regions. However, the layer of gate silicon oxide, is formed on signalisierung forest areas, has a low breakdown voltage (in comparison with the silicon oxide above the channel of the transistor), which is associated with a decrease in the packing density of the layer due to the inclusion of impurities of boron growing silicon oxide. It is not possible to produce BIS with a high level of supply having a thin gate dielectric. Low values of the breakdown voltage gate silicon oxide reduces the reliability of the BIS.The technical result increased reliability and expand the scope of an ENCORE by increasing the breakdown voltage gate oxide layer of silicon.The technical result is achieved in that in the method of manufacturing structures of the p-channel MOS LSI, comprising applying to the silicon substrate layer of silicon oxide and silicon nitride, forming a mask silicon nitride, protivodiversionnaya alloying, the cultivation of the field layer of silicon oxide, removing the layer of silicon nitride, forming a photoresistive mask, doping the active diffusion regions, forming a gate oxide layer of the silicon, creating a contact metallization and interconnects, according to the invention the SL is their alloying oxidize the surface of the doped active regions, remove the remaining part of the layer of silicon nitride to form the gate oxide layer of silicon. Thus, the increase of the breakdown voltage of the layer of gate silicon oxide is achieved by selective oxidation of the diffusion regions of the p-type protected by the mask silicon nitride.Forming a photoresistive mask, under the protection of which is the doping of the active regions, is performed on the layer of silicon nitride, which protects the active area when growing field isolation. The etching of silicon nitride in accordance with the configuration of the mask for the doping allows to oxidize the active region after alloying. As the channel length is set photoresistive mask for the doping of the active regions, the gates of transistors overlap with the active region on the value of resumeware. The gate dielectric located on signalisierung forest areas, has a low breakdown voltage due to violations of the structure of the oxide caused by included in the dielectric atoms of boron due to the effect of segregation. This significantly reduces the overall magnitude of the breakdown voltage gate dielectric. Therefore, the operation of selective oxidation of boron-doped regions (h is CI silicon nitride, located on the areas of the channels of the transistors can significantly increase the thickness of the layer of gate silicon oxide on the active regions and to increase its breakdown voltage. The thickness of the layer of silicon oxide is limited only by the requirements of the resistance of the active areas, which increases with increasing thickness of the oxide layer due to the effect of segregation of dopant. For example, in the manufacture of BIS CR 1043-VG with the level of operating voltage 35 V, above the channels of the transistors are formed gate oxide of silicon with a thickness of 0.09 μm, and the diffusion regions with a thickness of 0.4 μm. When subsequent etching removes approximately 0.2 μm oxide layer. Thus, the final thickness of the layer of silicon oxide on the active areas under the shutter is approximately 0.2 μm, which allows to increase the breakdown voltage of gate oxide of silicon to 70 C. In the manufacture of circuits with a higher level of operating voltage it is possible to improve the breakdown voltage by increasing the thickness of the oxide.The conditions of oxidation of the active regions is determined mainly by the requirements of the final resistance of the active regions. For example, if coprativeaboutC for 50 min in an atmosphere of water vapor, followed by annealing for 1 h in oxygen atmosphere, the resistance of the active regions is 40-450 m/sqThis increased resistance can be eliminated by conducting the oxidation at higher temperatures. Thus, the specific modes of formation of a protective layer of silicon oxide on the active regions are determined by the particular requirements of the electrophysical parameters of the gate dielectric and the active areas and depend on structural and technological features manufactured BIS.The increase of the breakdown voltage of gate silicon oxide can increase the reliability BIS and manufacturing schemes with a high level of power, i.e., to expand the scope of BIS. A METHOD of MANUFACTURING structures of p-CHANNEL MOS LSI, comprising applying to the silicon substrate layer of silicon oxide and silicon nitride, forming a mask silicon nitride, protivodiversionnaya alloying, the cultivation of the field layer of silicon oxide, removing the layer of silicon nitride, forming a photoresistive mask, doping the active diffusion regions, forming a gate oxide layer of the silicon, creating the Finance photoresistive mask with active diffusion regions, and after doping the active diffusion regions of the surface oxidize and remove the remaining part of the layer of silicon nitride, then form the gate oxide layer of silicon.
FIELD: technologies for making transistors.
SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.
EFFECT: ultra-short channel length of produced transistors.
11 cl, 17 dwg
FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.
SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.
EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.
2 cl, 1 dwg, 1 tbl
SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.
EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.
2 cl, 1 dwg, 1 tbl, 5 ex
SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.
EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.
SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.
EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.
4 cl, 1 dwg, 1 tbl
FIELD: electrical engineering.
SUBSTANCE: method for manufacture of a powerful UHF transistor includes formation of the topology of at least one transistor crystal on the semiconductor substrate face side, formation of the transistor electrodes, formation of at least one protective dielectric layer along the whole of the transistor crystal topology by way of plasma chemical application, the layer total length being 0.15-0.25 mcm, formation of the transistor crystal size by way of lithography and chemical etching processes. Prior to formation of the transistor crystal size, within the choke electrode area one performs local plasma chemical etching of the protective dielectric layer to a depth equal to the layer thickness; immediately after that one performs formation of protectively passivating dielectric layers of silicon nitride and diozide with thickness equal to 0.045-0.050 mm; plasma chemical application of the latter layers and the protective dielectric layer is performed in the same technological modes with plasma power equal to 300-350 W, during 30-35 sec and at a temperature of 150-250°C; during formation of the transistor crystal size ne performs chemical etching of the protectively passivating dielectric layers and the protective dielectric layer within the same technological cycle.
EFFECT: increased power output and augmentation ratio or powerful transistors with their long-term stability preservation.
4 cl, 1 dwg, 1 tbl
SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.
EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.
3 cl, 7 dwg
SUBSTANCE: invention relates to semiconductor technology. Proposed method comprises removal of photoresist from at least one surface of conducting layer with the help of the mix of chemical including first material of self-optimising monolayer and chemical to remove said photoresist. Thus self-optimising monolayer is deposited on at least one surface of said conducting ply. Semiconductor material is deposited on self-optimising monolayer applied on conducting layer without ozone cleaning of conducting layer.
EFFECT: simplified method.
15 cl, 4 dwg
SUBSTANCE: method for manufacture of powerful SHF transistor includes application of a solder layer to the flange, shaping of pedestal, application of a sublayer fixing the transistor crystal to the pedestal, formation of p-type conductivity oriented at the plane (111) at the base substrate of single-crystalline silicon and auxiliary epitaxial layers, application of the basic layer and buffer layer for growing of epitaxial structure of a semiconductor device based on wide-gap III-nitrides, application of heat conductive layer of CVD polycrystalline diamond to the basic layer, removal of the basic substrate with auxiliary epitaxial layers up to the basic layer, growing of heteroepitaxial structure based on wide-gap III-nitrides on the basic layer and formation of the source, gate and drain. The heat conductive layer of CVD polycrystalline diamond is used as a pedestal; nickel is implanted to its surficial region and annealed. Before formation of the source, gate and drain an additional layer of insulating polycrystalline diamond and additional layers of hafnium dioxide and aluminium oxide are deposited on top of the transistor crystal; the total thickness of the above layers is 1.0-4.0 nm.
EFFECT: invention allows increased heat removal from the active part of SHF-transistor and minimisation of gate current losses.
6 cl, 4 dwg
FIELD: electronic equipment.
SUBSTANCE: invention is intended to create discrete devices and microwave integrated circuits with the help of field-effect transistors. Method of making field-effect transistor, including creation of drain and source contacts on the contact layer of semiconductor structure and extraction of active region, metal or metal and dielectric mask is applied directly on the surface of contact layer, formation of submicron slot in the mask for further etching operations of contact layer etching and application of T-shaped gate metal through resist mask, after application of the first metal mask lithography for opening windows is carried out when one of the edges coincides with location of Schottky gates in manufactured transistor, and after opening windows the second metal or dielectric mask is applied on the whole surface, remove resist and by lithography create window in resist surrounding slits formed between two metals or between metal and dielectric, perform selective etching of contact layer, after which spray metal films to form T-shaped gates. As a result, edges of T-shaped gate heads on both sides resting on metal or metal and dielectric masks. Then, via selective etching the mask is removed from under the "wings" of T-shaped gate and from the surface of transistor active area. After that, the surface of transistor active area, containing drain, source contacts and Schottky gates, is coated with a passivating layer of dielectric so that under "wings" of T-shaped gate cavities are formed filled with vacuum or gas medium.
EFFECT: technical result is production of gated with length less than 100 nm, as well as reduced thickness of the metal mask and elimination of intermediate layer of dielectric placed between the active region surface and mask.
1 cl, 1 dwg