A device for converting digital signals

 

(57) Abstract:

The invention relates to a digital magnetic recording and can be used to reduce the time of conversion, error correction in the external storage device micro-computers and personal computers. The purpose of the invention: reducing conversion time while improving the noise immunity of digital magnetic recording without reducing the density digital magnetic recording. The device includes a Converter binary signal, a buffer register, a logical switch in parallel-to-serial Converter, a control unit consisting of a frequency multiplier nine, two frequency dividers by four frequency divider by three, two RS-triggers, pulse shaper, delay elements, two elements, OR four Inverto, elements And. reducing the noise caused by the transition to the septenary signals is compensated for by the view of the sevenfold signal is a binary signal and use an encoding that allows to correct single Semirechye errors of any sort. 7 Il. 3 table.

The invention relates to a digital magnetic recording and can be used for opensemaphore.

The invention can be used to correct errors in the communication channel using non-binary signals.

It is known a device in which the recording of information on magnetic media by a three-level code, which allows you to erase previously recorded information without the use of special erase head. Restore the original three-level signal by using a peak detector and a comparator with four levels of operation.

However, the immunity system of the recording-playback is low, and the use of the ternary signal is not possible to increase the recording density of more than 1.5 times.

A device for ternary digital magnetic recording, in which a continuous sequence of the erase signal inputted insert the positive and negative polarity, leading the media to saturation.

The device allows to increase the density digital magnetic recording 1.5 times, but the conversion time, as well as the density and robustness of the recording-playback low.

A device for digital magnetic recording-reproduction in which to increase the float time of conversion, the noise immunity of the recording-playback is low due to the low redundancy.

It is known a device in which to increase the density digital magnetic recording 2.0 times used sevenfold signal.

However, the noise immunity of the recording-playback is low, because the analogue is not possible to correct errors.

A device adopted for the prototype, to convert digital signals in which to improve noise immunity and informative uses binary-patienoe conversion. The device prototype contains the transducer signal into a bipolar signal analyzer weight, this polarity pulse, the multiplexer, the logical switch, consisting of a rectifier, the five elements OR five inverters, three adders, two keys, and the input device connected to the Converter binary signal, the most significant of which are connected to respective inputs of the analyzer weight and to the first inputs of the Converter polarity pulses whose outputs are connected to respective first inputs of the multiplexer, the output of the multiplexer is connected to the output of the device, low-order bits of the Converter binary signal into a bipolar signal connected to the corresponding information input logical pereklyuchatelnom logical switch is connected via a second inverter to the first information output logical switch, with the first input of the first key with the first inputs of the first, fourth, and fifth elements OR through third and fourth inverters are connected respectively to the first inputs of the second and third elements OR the second information input of logic switch connected to the first input of the second key, the third information output logical switch and through the rectifier to the second inputs of the first, second, third, fourth and fifth elements OR through the first inverter to the first information output logic switch, the output of the first element OR is connected to the third output of the logical switch, the first control input logic switch is connected to the second input of the first key and the first control output of the logical switch, the outputs of the second and third elements OR connected with the first and second information inputs of the logical switch, the outputs of the fourth and fifth elements OR connected to the input of the third adder, the output of which through the fifth inverter is connected with the third information output logical switch.

The device prototype (with his undoubted health) has significant nedostatkami.mne information on the yield of the desired signal resolution Converter, the polarity of the pulses, which is formed at the output of the analyzer weight, after finding the weight of this unit and this operation is repeated in each unit, due to this, the conversion time increases significantly, resulting in lower performance computers.

The obvious solution to these problems is using patricinha correcting code, to compensate for the decreased immunity. The use of any known systematic patricinha code a specified length requires the introduction of additional test characters. Although this can partially compensate for the decreased immunity, however, this increases the conversion time, reduces the specific speed information, and therefore the density digital magnetic recording. The application of nonlinear patiricia codes allows you to correct single errors without reducing the speed information, i.e., without reducing the density digital magnetic recording. However, the implementation of such a device is possible only with memory usage very large, which significantly increases the conversion time and complicates the system for digital magnetic recording. Thus, it is obvious PU is="ptx2">

The aim of the invention is to reduce the time of the conversion, while increasing the noise immunity of conversion without reducing the density digital magnetic recording.

The achievement of this goal allows to increase the reliability of digital magnetic recording without reducing the amount of information recorded on magnetic media. While the performance of the process recording-reproduction, and hence the performance of the computer will be raised.

With this purpose, the device is a prototype, containing Converter binary signal information input by the information input device, the logical switch, the outputs of which are connected to the first information input parallel to serial Converter whose outputs are the outputs of the device, t l and h and Yu y e e s I the fact that, in order to reduce the time of the conversion and improve noise immunity of the device without reducing the density digital magnetic recording, the device entered the control unit and 36-bit buffer register, the Converter binary signal is made in the form of binary-sevenfold Converter, the logical switch is made on seven su is the breaker, engraved Converter binary signal is combined with the input of the control unit and is the synchronization input device, the first and second outputs of the control unit connected to the first and second control inputs of the Converter binary signal, the outputs of which are connected to the information input 36-bit buffer register whose outputs are connected to the corresponding inputs of the logical switch and the second information inputs parallel-to-serial Converter, the third output control unit connected to the control input 36-bit buffer register and the first control input in parallel-to-serial Converter, the second control input connected to the fourth output control unit, consisting of a frequency multiplier by two frequency divider by-eight frequency divider by nine, two frequency dividers by four frequency divider by three, two RS-triggers, pulse shaper, delay elements, two elements, OR four inverters and And gates the input of the frequency multiplier on the two combined with the input of the frequency multiplier eight and is the input of the control unit, the output of the frequency divider eight is connected to the S-input pen is ogiela frequency on two connected to the input of the second inverter, the output of which is connected with the first inputs of the frequency divider nine, frequency divider by three, the first frequency divider by four and the input of the delay element, the output of which is connected to the first inputs of the first and second elements OR, the outputs of which are respectively the second and fourth outputs of the control unit, the output of the frequency divider nine connected directly to the R-input of the first flip-flop and connected in series through the third inverter, a second frequency divider for four and a pulse shaper to the third output of the control unit and the input of the fourth inverter, the output of kotorogo connected to the first input element And the output of which is connected to a second input of the first frequency divider by four, the output of which is connected to the second input element And S is the input of the second trigger, the output of which is connected to a second input of the second element OR the second input of the frequency divider by three, the output of which is connected to the R input of the second trigger, the output of the first flip-flop connected to the second inputs of the first element and the frequency divider nine.

The essence of the invention lies in the fact that the introduction of these elements together with their connections can reduce the solution, supplied to input buffer register, and only for synchronization and to perform error correction when recording-playback sevenfold signala. Since the transition from patienoe record to sevenfold leads to a slight decrease in noise and redundancy sevenfold signal r7log272,81, significantly more redundancy patricinha signal r52,36, at the desired length, you can build a systematic sevenfold correcting code that will compensate for the reduction of noise without reducing the density recording, which remains the same as in the device prototype.

In the proposed device the source tridtsatidvuhletny information code word (a1and2.and32)i0,1 converted into twelve sevenfold code word (C1with2.with12) ci. This is possible because 232< 712. The transformation is carried out according to the rule of transformation of the number of binary notation in septenary. To significantly simplify all subsequent operations and to reduce the time of conversion, each i-th septenary symbol ciit seems the three-digit doctable.3. As a result of such conversion the original 32-bit binary code word (a1and2and32)i0,1; seems to be a 36-bit binary code word (b11b21b31; b13b22b32.b1b2b3); bji0,1; i ; j ; ci0,6. To increase the noise immunity of the claimed device formed to 36-bit binary code word is added 12 validation of binary symbols (b37b38.b48), which are chosen so that in a 48-bit binary code word to provide a fix phased package of error of three characters. This representation actually corresponds to fixing one of the sevenfold character in a 16-bit sevenfold code word. While it remains a minor redundancy will be used to maintain the block synchronization. Checking symbols (b37b38.b48) are calculated according to the following algorithm, where all the operations of summation are performed modulo two:

b1+b4+b7+b10+b13+b16+b19+b22+b25+b28+b31+b34= b38< / BR>
b2< / BR>
b3+b6+b9+b12+b15+b18+b21+b24+b27+b30+b33+b36= b41< / BR>
(1)

< / BR>
(2)

Check the symbols b37b40b42b43b46equate to zero b37= b40b42b43b460

Since the combination of (111), the excess, to address uncertainties in each of the three code combination of test symbols, enter a null character. From the formula (2), after some transformations, we find the following checklist characters:

< / BR>
< / BR>
< / BR>
< / BR>
(3)

Thus, at the output device are generated 48-bit binary code words, in which every phased three characters correspond to one of the sevenfold character. Thus, in the proposed device, the transformation is of the form 32V-16S, i.e. 32 original binary symbol is converted to 16 sevenfold characters. As follows from the above, the generated code has a minimum Hemingby distance dm3, i.e. provides fix any septenary errors.

Because delay is introduced only at the initial moment of time the enable signal supplied to input bufetes the calculus the inventive device allows to significantly simplify the device and reduce the conversion time, but also increase the immunity conversion without reducing the density digital magnetic recording.

Thus, the proposed device allows it to achieve its goal to reduce the conversion time and to improve the noise immunity of digital magnetic recording without reducing its density.

In Fig. 1 shows the structural diagram of the inventive device of Fig.2 stresses illustrating operation of the inventive device of Fig.3 implementation of the Converter binary signal of Fig.4 is a structural diagram of the logical switch; Fig.5 block diagram of the decoder of the inventive device of Fig. 6 one of the possible implementations of the parallel to serial Converter 4 of Fig.7 shows one of the possible implementations of the parallel-serial Converter 4.

Table.1 and 2 explain the operation of the device (encoder and decoder.

Table.3 explains the operation of the Converter 1.

The inventive device includes a Converter binary signal 1, the information input by the information input device, the logic is the first Converter 4, the outputs of which are the outputs of the device, a control unit 5 and 36-bit buffer register, the Converter binary signal 1 is made in the form of binary-sevenfold Converter, logical switch 3 is made on seven adders modulo two, the inputs and outputs of which are respectively the inputs and outputs of the logical switch 3, while engraved Converter 1 binary signal is combined with the input of the control unit 5 and is input to the synchronization device, the first and second outputs of the control unit 5 is connected to the first and second control inputs of the Converter 1 binary signal, the outputs of which are connected to the information input 36-bit buffer register 2, the outputs of which are connected to corresponding inputs of the logical switch 3 and the second information inputs parallel-to-serial Converter 4, the third output control unit 5 is connected to the control input of the parallel-serial Converter 4, the second control input connected to the fourth output control unit 5 consisting of a frequency multiplier for two 6, the frequency divider eight 7, the frequency divider nine 8, two frequency dividers on che the owls 16, delay elements 11, two elements OR 13, 22, respectively, four inverters 9, 10, 14, 17 and item And 18, the input of the frequency multiplier of two 6 United c input frequency multiplier eight 7 and is input to the control unit 5, the output of the frequency divider eight 7 is connected to the S input of the first flip-flop 12, and the input of the first inverter 9, the output of which is the first output control unit 5, the output of frequency multiplier for two 6 connected to the input of the second inverter 10, the output of which is connected with the first inputs of the frequency divider nine 8, the frequency divider by three 20, the first frequency divider by four 19 and the input of the delay element 11, the output of which is connected to the first inputs of the first and second element OR 13, 22, respectively, the outputs of which are respectively the second and fourth outputs of the control unit 5, the output of the frequency divider nine 8 is connected directly to the R-input of the first flip-flop 12 and connected in series through the third inverter 14, a second frequency divider for four 15 and the pulse shaper 16 to the third output control unit 5 and to the input of the fourth inverter 17, the output of which is connected to the first input element And 18, the output of which is connected with the second input of the first frequency divider is th is connected to a second input of the second OR element 22 and the second input of the frequency divider by three 20, the output of which is connected to the R input of the second trigger 21, the output of the first flip-flop 12 is connected to the second inputs of the first element OR 13 and the frequency divider nine 8.

The device operates as follows. At the first input of the Converter 1, receives an information signal with a clock frequency Fa(Fig.2,a), which is converted to parallel the twelve sevenfold signal. The transformation is carried out according to the rule of transformation of the number of binary notation in septenary. Such a transformation is possible, because 232< 712. Each discharge sevenfold, kodovogo words in turn appears to be a three-digit binary combination in accordance with table.1, 2. To significantly reduce the amount of memory used in the Converter 1, the following correspondence between the input and output codes.

The input sequence of 32-bit binary symbols is divided into blocks of 8 binary characters. Each such unit (4) is converted into 3 septenary symbol. Such a transformation is possible, because 28< 73. To simplify the implementation of each septenary character introduces himself units of 3 binary symbols, and comb the tins 9 binary symbols, and during one of the 32-bit binary code words, such a transformation in ROM is carried out 4 times. The correspondence between the input 8-bit and output 9-bit codes shown in table.3 (Fig.6). This transformation corresponds to the translation of numbers from binary notation to sevenfold. Because the combination 111 is prohibited in the table.3 (Fig.6) some measures have been taken to resolve a series of three units. Thus, the binary Converter 1 converts the signal tridtsatidvuhletny binary signal in parallel tridtsatishestiletny binary signal with frequency FandFa/32 (Fig.2,and). The principle of operation of the Converter 1 is the same as in the device is a prototype and is to transfer the number from one number system to another. Unlike the prototype, the proposed device in the Converter 1 is a representation of each septenary number a three-digit binary word. Implementation of the Converter is known, it is possible to eight shift registers series I, two ROM series CRRT, delay elements and is shown in Fig.3. The input transducer 1 (Fig.3) in sequential code comes with the 32-bit binary sequence SIM is th shift register, which performs serial-to-parallel conversion. With outputs of the first register 8-bit binary combination in parallel code is supplied for informational inputs of the first and second ROMs that are paired carry out the conversion code in accordance with table.3 (Fig.6). The permission signal code translation is the frequency F2(Fig.2,g). Outputs of ROM 9-bit binary signal (which corresponds to 3-bit sevenfold signal) is supplied to the corresponding inputs of the second and third registers, the control input of which receives the frequency F2(Fig.2,g), and the clock input frequency FW(Fig.2,W).

From the output of the third shift register signal in the sequential code is supplied to the information input serial input information DR chetvertogo of the shift register. In the fourth-seventh register serial-to-parallel conversion, i.e. the conversion of four 9-bit serial binary combinations in 36-bit parallel binary combination, which corresponds to 12-bit sevenfold combination. Thus, in the inverter 1 is the translation of a 32-bit binary numbers in 12 razrehseniem solutions this conversion does not require huge memory (28bits instead of 232). This reduces the conversion time. With outputs of the Converter 1, the converted signals are sent to corresponding inputs of a buffer register 2, which serves for storing tridtsatishestiletny characters within T' Ta' 32. Outputs of the buffer register 2 signals without changing arrive at the corresponding first 36 inputs parallel-to-serial Converter 4, as well as to corresponding inputs of a logical switch 3. The principle of operation of the buffer register 2 is to implement a parallel-serial conversion, and its implementation is known from the literature.

In the logical switch 3 performs a summation modulo two, in accordance with the encoding algorithm. Implementation of the logical switch 3 is known (Fig.4) and the possible seven the multi-input adders modulo two, performed on eighteen velmuradova chips parity, series IP. With the outputs of the logical switch 3, the signals which are checking symbols in the proposed codes come on sootvetstvuyushie remaining 12 inputs parallel-postroute. The principle of operation of the parallel-serial Converter 4 is to implement the transformation of sorokowski binary characters presented in the parallel code, in groups of 3 binary characters, presented in sequential code, and each group corresponds to one of the sevenfold character.

Parallel-to-serial Converter 4 of the proposed device is made in the form of a parallel-serial shift register, the last three weekends of the discharge which are the inputs of the three-digit parallel-serial register, the information of which is read at a frequency Fk(Fig. 2,to).

The parallel-to-serial Converter contains seven shift registers, the counter, the three elements, differential chain, and a clock input parallel-to-serial Converter connected with the first inputs of the first, second, third, fourth, fifth, sixth shift registers, through the first, second, third element And is connected to a second input of the counter, the output of which is connected with its first input with the first input of the seventh shift register, while the third input of the counter through differential chain is connected with the UE is th, fifth, the sixth shift register, a second input connected to the last output of the fifth shift register, a second input connected to the last output of the fourth register, shift, a second input connected to the last output of the third shift register, a second input connected to the last output of the second shift register, a second input connected to the last output of the first shift register, and information inputs parallel-to-serial Converter connected to the appropriate information inputs of the first, second, third, fourth, fifth, sixth shift register, three of the last output of which is connected with the first three informational inputs of the seventh shift register, the first three of which are the outputs of the parallel-to-serial Converter. The output of parallel-to-serial Converter 4 is a three-digit code word that corresponds to the first septenary signal following the clock frequency Fk. Implementation of the parallel-serial Converter 4 are known from the literature.

Parallel-to-serial Converter operates as follows. 48-bit as the shift register CIR eight bit it uses six shift registers. For parallel input input 48-bit binary symbols on the control inputs of S1D1-D6the signal write Fand(Fig.2,and). Recent outputs of the D1-D6connected to respective inputs serial input information DR. The information from the shift registers D1-D6 are read with a clock frequency Fn(Fig. 2, n), which is fed to the clock inputs D1-D6. Clocked through the inverter D9.1 and delay element assembled on D9.2, D9.3 is supplied to the counting +1 counter input D6. Input reset to zero all outputs of the counter signal Fn(Fig.2,and through differential chain. On the element D8 assembled a divide-by-three frequency Fn(Fig.2,n), i.e., the output D8 received frequency Fto(Fig.2,K), which is supplied to the clock input C2 of the shift register D7, the inputs of which are connected respectively with the last three outputs of the shift register D6. The outputs Q1, Q2, Q3the shift register D7 are output parallel-to-serial Converter 4 and the output device. Elements D1-D6 are shift registers series CIR, D7 CIR, d A, D9 US. Thus the output of the parallel-serial is the next Alu with a clock frequency Fto(Fig.2,to).

The operation of the transducer binary signal 1, the buffer register 2 parallel-serial Converter 4 control signals from the control unit 5. Clock frequency Fa(Fig.2,a) is supplied to the second input of the Converter binary signal 1, and also to the input of the multiplier 6 frequency by two and the divider 7 frequency by eight, from the output of the divider 7 frequencies on eight through serially connected inverter 9 frequency FgFa/8 (Fig.2,g) is supplied to the third control input of the Converter 1, and the S input of the first RS-flip-flop 12, with the inverted output of which the signal Fc(Fig.2,e) is fed to the input pre-setting of the frequency divider at nine, which is the second input of the divider 8 frequency at nine, at a first input, which is the counting input receives the inverse of twice the frequency Fin(Fig. 2) with the output of the second inverter 10. The implementation of the controlled divider 8 to nine are known from the literature and possible counter series II. From the output of the controlled divider 8 frequency nine signal Fd(Fig.2,d) is fed to the R input of the first RS-flip-flop 12, with the inverted output of which the signal Fedepicted on Fig.3,e, is fed to the R and the delay element 11 is fed inverted double clock frequency Fin(Fig. 2). With the release of the first element OR 3 control signal FW(Fig.2,W) is supplied to the fourth control input of the Converter 1 binary signal. To control the buffer register from the third output control unit is frequency FandFa/32 (Fig.2), which is formed as follows. The signal Fd(Fig.2,d) from the output of divider 8 frequency nine through series-connected third inverter 14, the first divider 15 frequency to four (Fig.2,C), the imaging unit 16 pulses (Fig.2,and is fed to the control input of the buffer register 2 and the first control input in parallel-to-serial Converter 4. The signal Fand(Fig.2,and) from the output of the pulse shaper 10 via the fourth inverter 17 is supplied to the second input of the second divider 19 frequency by four, which is the input of the pre-setting, the output of which the signal Fto(Fig.2,K) is supplied to the S input of the second RS-flip-flop 21, at the R input of which receives the signal Fl(Fig.2,l) from the output of the frequency divider by three. A possible implementation of the control frequency dividers 19 for four and 20 to three, the same as in the above-described controlled divider 8 frequency at nine. The first entrance, which is the counter input Delhi is e, which receives the inverse of twice the clock frequency Fin(Fig.2) with the output of the second inverter 10. At the second input of the divider 20 frequency by three, which is the input of the preset signal Fm(Fig.2,m), with the inverted output of the second trigger 21, which is supplied also to the second input of the second element OR 22, the first input through the delay element 11 receives the inverse of twice the frequency Fin(Fig.2), the signal Fn(Fig.2,n) from the output 22 of the element OR supplied to the second control input in parallel-to-serial Converter 4. The control unit is implemented on a standard chip series C.

Thus, the proposed device provides a solution to a single sevenfold error if the length of the septenary code word m 16. This allows to significantly improve the noise immunity without compromising density digital magnetic recording with simultaneous reduction of time conversion.

The present invention allows to reduce the conversion time, first, due to the fact that all operations are performed in binary notation and in parallel, and secondly, due to the fact that otsutstvuet delay element as indicated by the tion, and also allows the system digital magnetic recording with twice the density to increase the noise immunity by correcting errors. Increased robustness achieved without reducing the density recording, which became possible thanks to the introduction of elements together with their relationships. This has enabled the recording of the sevenfold signal, and the resulting redundancy is to use error correction, while remaining small redundancy can be used to maintain the block synchronization. The proposed device also has some other advantages: it provides samosinkhronizatsii reproduced signal, the ease of implementation (decoder) decoder.

Experimental studies have fully confirmed the possibility of achieving the goal. To confirm the achievement of these goals, and to prove the uniqueness decoding, consider the decoding device (the device that performs the opposite conversion), the scheme of which is shown in Fig.5. The algorithm of the decoder illustrated by the following expressions:

++++++++++++= e1< / BR>
++++++++++++= e2< / BR>
++++++++++++= e3,

(4) where (e1the mules (5) after conversion, we find the following check symbols by the formula:

< / BR>
(6)

From the formula (5)

(e1+e2g+e3g2g6+g+g2+g3(7)

where gi=

Let the code word represents a sevenfold sequence, . )= , where each symbol in this sequence is represented by a three-digit code word (,,), 0,1; i ; j . Thus, the information input decoder receives 48-bit serial code word (, .), where each triplet of symbols corresponds to one of the sevenfold character. Moreover, the information input of the decoder is connected to the input of a serial-to-parallel register 23, which is the representation of 48 consecutive code words in 48 parallel code word, which is supplied to corresponding inputs of a logical switch 24 that calculates the sum modulo two the algorithm (formula 4, 5, 6). If the syndrome s1e2e30, the input 48 bit information from which undertake only (, , ,,) output from the serial-to-parallel register 23 through the serially connected logic device 24, is fed to semireche-binary Converter 28, where the conversion code words (,, ,, in a code word (a1and2andwhich exists on a parallel-serial register 29, in which is the representation of a parallel 32-bit code words in consecutive 32-bit code word. The output of parallel-to-serial register 29 is the output of the decoder. If at least one test of syndrome symbols (e1e2e3) is not equal to zero, then it prohibits the logical device 27 for the passage of the 36-bit code words. When this test is calculated symbols (e1e2e3) (,,, ), the algorithm (formula 4, 5, 6), the output of the logical switch 24 serves to corresponding inputs of a programmable memory (ROM) 25, where in accordance with the algorithm (7) are stored various decision algorithm F. 6 in accordance with the arithmetic for GF(16), asked irreducible primitive polynomial X4+X+1 by the formula:

g4g+1

g5g2+g

g6g3+g2< / BR>
g7g3+g+1

g8g2+1

g9g3+g (8)

g10g2+g+1

g11g3+g2+g

g12g3+g2+g

g13g3+g2+1

g14g3+1

g151

At the outputs of the ROM 25 is formed of a 4-bit binary CODM code word ), ; = ; i ; j , the package where the error occurred. Output from the ROM 25 4-bit code word is supplied to corresponding inputs of a decoder 26, a low level output which indicates it is in which position the error occurred. From the output of the decoder 26 12-bit code word is supplied to corresponding inputs of a logical device 27, which is based on the 12-bit code word is given permission on the package where the error occurred. When this verification syndrome (e1e2e3), which is fed to the input logical device 27 with the respective outputs of the logical switch 24, is added modulo two with the package (a (,,;=0,1; i ;j ) where the error occurred.

Next 36-bit code word output from the logical device 27 is supplied to corresponding inputs of semireche-binary Converter 28, the output of which is 32-bit parallel binary code word is supplied to corresponding inputs of a parallel-serial register 29 whose output is the output device. The layout of the proposed device have shown the effectiveness of this method and relatively simple technical implementation.

Thus, the proposed technique is the elements together with their relationships. This allowed all the operations to perform in a binary system in parallel, to write sevenfold signal represented in binary code, and appearing redundancy is to use error correction. This allowed also in the system of digital magnetic recording with twice the density to increase the noise immunity by correcting errors. Increased robustness is achieved without reducing the density recording.

The proposed device has other advantages: it provides samosinkhronizatsii reproduced signal, the ease of implementation (decoder) decoder. Experimental studies have fully confirmed the possibility of achieving the goal.

A DEVICE FOR CONVERTING digital SIGNALS containing Converter binary signal information input by the information input device, the logical switch, the outputs of which are connected to the first informational inputs parallel-to-serial Converter whose outputs are the outputs of the device, characterized in that, in order to reduce the time of the conversion and improve noise immunity of the device without SN is p, Converter binary signal is made in the form of binary sevenfold Converter, the logical switch is made on seven adders modulo two, the inputs and outputs of which are respectively the inputs and outputs of the logical switch, engraved Converter binary signal is combined with the input of the control unit and is the synchronization input device, the first and second outputs of the control unit connected to the first and second control inputs of the Converter binary signal, the outputs of which are connected to the information input 36-bit buffer register whose outputs are connected to the corresponding inputs of the logical switch and the second information inputs parallel-to-serial Converter, the third output control unit connected to the control input 36-bit buffer register and the first control input in parallel-to-serial Converter, the second control input connected to the fourth output control unit consisting of a frequency multiplier by two frequency divider by-eight frequency divider by nine, two frequency dividers by four frequency divider by three, two RS-triggers, shaper of the two combined with the input of the frequency multiplier eight and is the input of the control unit, the output of deites frequency eight is connected to the S-input of the first RS-flip-flop and the input of the first inverter whose output is the first output control unit, the output of the frequency multiplier of two is connected to the input of the second inverter, the output of which is connected with the first inputs of the frequency divider nine, frequency divider by three, the first frequency divider by four and the input of the delay element, the output of which is connected to the first inputs of the first and second elements OR, the outputs of which are respectively the second and fourth outputs of the control unit, the output of the frequency divider nine connected directly to the R-input of the first RS-flip-flop and connected in series through the third inverter, a second frequency divider for four and a pulse shaper to the third output of the control unit and the input of the fourth inverter, the output of which is connected to the first input element And the output of which is connected to a second input of the first frequency divider by four, the output of which is connected to the second input element And S is the input of the second RS-flip-flop, the output of which is connected to a second input of the second element OR the second input of the frequency divider by three, the output of which is connected to the R input of the second RS-flip-flop, the output of the first RS-flip the

 

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FIELD: engineering of printers and memory devices for printers.

SUBSTANCE: in accordance to suggested method for detecting error in data, received from memory device of replaceable printer component, ensured is first evenness control bit, associated with first data element. First data element and first evenness control bit are stored in memorizing device. Printer includes a set of electro-conductive lines. Memorizing device includes a set of bits. At least one of electro-conductive lines is associated with each bit. First data element and first evenness control bit are read from memorizing device. Electric test of at least one of electro-conductive lines is performed. Error is identified in first data element on basis of first evenness control bit, read from memorizing device, and electric test. Other inventions of group envelop printing system, two variants of realization of replaceable printer component for printing system and method for storing information in replaceable printer component are provided.

EFFECT: creation of memory device with increased reliability, timely detection and correction of errors in replaceable components of printers ensures their continuous operation.

5 cl, 7 dwg

FIELD: transport; shipbuilding.

SUBSTANCE: device contains magnetoelastic torque transducer consisting of two magnetoelastic converters located at opposite sides of propeller shaft and made with test coils. Transducer is capable of measuring mechanical stress caused by torsional oscillations and constant component of torque. There is compensation circuit of zero signal and automated remote control system for main engine of vessel's power plant. Apart from it, device has synchronous detector, lower frequencies filter, upper frequencies filter, and threshold devices.

EFFECT: increase of reliability and efficiency of vessel's power plant at expense of prevention of operation of diesel in sphere of mechanical stress from torsional oscillations exceeding preset value and its protection from overload.

1 dwg

FIELD: physics, measurement.

SUBSTANCE: invention is related to the field of measurement and may be used in metrological research of sine-cosine rotary transformers. In device for measurement of static error, on angle setting unit there is rotary transformer fixed, signal windings of which are connected via switchboard to analog inlets of voltage-code transducer. Its digital outlet is connected via register to address bus of ROM, information bus of which via buffer cascade is connected to inputs of decoder, to outlet of which digital indicator if information display is connected.

EFFECT: expansion of functional resources by provision of error measurement at any value of angle and visualisation of angle value displaying.

1 dwg

FIELD: radio engineering, communication.

SUBSTANCE: disclosed is automated monitoring and testing equipment for testing energy and information interaction circuits of a multichannel control system with actuating devices, having a virtual reference and a module for comparing signals with the reference, a personal computer connected to an information transmission unit with a monitoring unit, which can be connected to a monitored system and has a control unit, a multichannel unit for standardising input signals with an analogue-to-digital converter, a unit for generating output signals and an interface simulator. The equipment is provided with a unit for simulating standard connection of the monitored system with a unit for generating relay signals of the state of the monitored system, a unit for simulating connection to a power supply network, a control module, a module for communication of the monitored system with the personal computer and an interface module, which can be connected to the interface simulator of the monitoring unit through the monitored multichannel control system.

EFFECT: broader functional capabilities of the equipment and high reliability of monitoring by providing equivalent standard connection of the monitored system.

1 dwg

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to monitoring activation of subordinate blocks of LIN networks. The device (D) is designed to monitor activation of subordinate blocks (OE1-OE5) of a multiplexed LIN communication network (R) controlled by a driving block (OM). The device (D) is designed such that when the driving block (OM) detects activity in the network (R) during a standby phase, i) it instructs the driving block (OM) to transmit to at least some subordinate blocks (OE1-OE5) and preferably to all blocks, which can be a source of an activation request, request messages to which they must respond via a response message containing a status field, the value of which characterises a local or non-local source of the detected activity, ii) analyse the value of the status field of each response message received by the driving block (OM) in order to determine if at least one subordinate block is a source of activity and if so, whether said activity is justified with respect to the corresponding value of the status field, and iii) allow the driving block (OM) to acknowledge activation of subordinate blocks only if the activity is justified.

EFFECT: preventing activation of subordinate blocks of a LIN network if the source of an activation request is interference.

13 cl, 2 dwg

FIELD: physics, control.

SUBSTANCE: invention relates to remote control, particularly to remote control of parameters in a given range. The invention describes a system and a method for controlling a plurality of devices (150) using a remote control device (105). The remote control device (105) transmits the same sequence of commands to each of a plurality of devices (150) to perform relative increase or decrease of their parameter by a certain value. Two-way communication exists between the remote control device (105) and the devices (150). The devices (150) acknowledge correct reception of commands by transmitting an acknowledgement message to the remote control device (105). The remote control device (105) retransmits a command to a device (150) if no acknowledgement message is received from the device (150). In that case, all control devices (150) are guaranteed to receive the same commands and their controlled parameters are maintained in synchronisation.

EFFECT: synchronised control of a plurality of devices with relative parameter values.

14 cl, 5 dwg

FIELD: instrumentation.

SUBSTANCE: invention relates to the device to control error of conversion of the shaft rotation angle to the code. The device contains reference converter of shaft rotation to code, block interfacing the monitored and reference converters, comprising assembly of rigid connection of shafts of the reference and monitored converters, assembly limiting casing rotation of the monitored or reference converter with installed autocollimating mirror, which angular position is measured by the digital autocollimator. The autocollimator output and outputs of the controlled and reference converters via the electronic block are connected with PC. Assembly limiting casing rotation of the monitored or reference converters provided the casing with all degrees of freedom excluding rotation around the axis of the own shaft, and can be made in form of parallel-link mechanism with spherical linkages.

EFFECT: assurance of the possibility tom increase number of the monitored positions of the converter.

FIELD: measurement equipment.

SUBSTANCE: device comprises a measurement result storage unit, switches, a unit of splitting into intervals, random number generators, a unit of the related values removal, a ranking unit, a register of storing random number sampling, approximation units, subtracting units, units of storing the residues, units receiving the ranked series at the intervals, units receiving the truncated sample, calculation units of the estimated standard deviation, multiplication units, a register of storing the coefficient, a unit of determining the coefficient, a unit of setting false alarm probability, comparators, units of storing fines, an arithmetic adder, a unit of calculating the threshold, a comparator, a register of storing fines, units of constructing and approximating the histogram, a difference calculation unit, a replacement unit, a storage unit, a control unit, a storage register, a delay unit, a generator of the clock pulses.

EFFECT: detecting and eliminating the anomalous measurements at the fixed probability of the false alarm.

2 dwg

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