A device for the regeneration control in the semiconductor dynamic memory

 

(57) Abstract:

The invention relates to computer technology and can be used in computer systems special purpose exposed during operation to physical fields of high and variable intensity. The device contains the first 1, second 2, third 3 and fourth 4 elements AND NOT the first 5 and second 6 triggers the first 7, second 8 and 9 third elements, the first 10 and second 11 elements of the delay element OR 12, item NO 13, block 14 forming pulses of regeneration start and a group of sensors 15, 1 15 K. 1 C.p. f-crystals, 1 Il.

The invention relates to computer technology and can be used in computer systems special purpose exposed during operation to physical fields of high and varying intensity, for example, in information-measuring systems of control of the radiological situation, x-ray and NMR tomography, industrial robots, etc.

At high intensity affecting the computational complex of ionizing radiation and/or electromagnetic fields it is necessary, first of all, about the use in computer systems semiconductor dynamic memory device, which include dynamic BIS RAM.

By maintaining information in a dynamic BIS RAM is the need to periodically access each row of the matrix memory. Usually used for this purpose, the regeneration mode, in which in each cycle of treatment ENCORE RAM is address of the next line, followed by the address strobe line (signal ), and prohibited the issuance of the address strobe column (signal ). In order to iterate through all the rows, you must have the meter, and circuit switching its contents on the address inputs BIS RAM with the appropriate controls.

In order to exclude these hardware costs, late model domestic and foreign BIS RAM has a special mode of regeneration, when the chips are served both signal and , however unlike a normal write or read signal should earlier signal . There is an internal counter BIS RAM, which counts the regenerated lines.

A device for the regeneration control in the semiconductor dynamic memory, providing the mode control regeneration as in the absence of memory requests from external devices, the coy memory contains a first the second, third and fourth elements, AND IS NOT, first and second triggers, the first, second and third elements, the first and second delay elements, the element OR the element is NOT the first input of the first element AND IS NOT connected to the direct output of the first trigger, the trigger input of which is the first clock input devices, the output of the second element AND IS NOT connected to the set input of the first trigger, the inverted output of which is connected with the reset input of the second trigger and the first input of the third element AND IS NOT, the second input of which is a control input device, the first input of the fourth element AND IS NOT connected to the output of the first element And is the start output device, the first input of the second element And is connected to the direct output of the second trigger, the information input which is the input signal of the logical unit, the output of the first element AND IS NOT connected to the first input of the third element And the second input and the input of the first delay elements are United and connected with the output of the third element AND IS NOT, the input of the second delay element and the first input of the first element And the joint and is connected to the output element OR the first input of which the input element is NOT United and avlod which, the second input of the first element AND the second input of the fourth element AND NOT joint and are the second-synchronization input device, the third input of the second element AND IS NOT connected to the output of the second element And the second input is connected with the output of the first delay element, the output of the second delay element connected to the second input of the first element And the fourth element AND-NOT and the output of the third element And are respectively output Gating the address lines and the output Gating address column device, the information input of the first flip-flop is the input signal of the logic zero of the device, and direct the output of the first trigger is connected to the second input of the OR element. The device comprises also connected to the synchronization input of the second trigger pulse generator, the repetition period which determines the frequency of regeneration cycles.

When determining the duration of the repetition period of pulses of the start of the regeneration mode, be aware that, firstly, when working BIS RAM it cannot communicate with other parts of the computer complex, which is interrupted during the regeneration cycle. Secondly, stored in dynamic memory detail and her work is required to increase the frequency of the start of the regeneration mode.

When exposed to a semiconductor dynamic memory ionizing radiation and/or strong electromagnetic fields increases the rate of destruction of stored data. This, in turn, requires reduction of the time interval between cycles of regeneration, that is, increasing the frequency of the start of the regeneration mode. At a constant duration of the regeneration cycle, the increase in the frequency of running this mode leads to a redistribution of the total operating time of the dynamic memory in the direction of reducing the time during which the dynamic memory can interact with other parts of the computer complex, which is equivalent to reducing the average effective speed of the dynamic memory and, consequently, poor performance computing.

During operation of computer system with dynamic memory in stable conditions, the possible choice of the optimal constant frequency mode of regeneration, which produces the desired robustness and reliability of the memory at the minimum acceptable reduction in the average effective performance.

In the case of impact on the computational complex of polypr the s start the regeneration mode with increasing intensity fields in excess of the specified values can lead to disruption of the complex due to a sharp reduction in the reliability of memory. The choice of high frequency start mode regeneration focused on the maximum peak intensity values of physical fields, leads to unnecessary loss of machine time for medium and low intensity.

The objective of the invention is the possibility of adaptation of the triggering frequency of the regeneration mode semiconductor dynamic memory to changes in the intensity of the external physical fields, thereby maintaining the required noise immunity and reliability of the memory to provide the maximum allowable current conditions average effective memory speed.

This technical result is achieved in that in a device for the regeneration control in the semiconductor dynamic memory, containing the first, second, third and fourth elements, the first and second triggers, the first, second and third elements, the first and second delay elements, the element OR the element is NOT the first input of the first element AND IS NOT connected to the direct output of the first trigger, the trigger input of which is the first clock input devices, the output of the second element AND IS NOT connected to the set input of the first trigger second input of which is a control input device, the first input of the fourth element AND IS NOT connected to the output of the first element And is the start output device, the first input of the second element And is connected to the direct output of the second trigger, the information input which is the input signal of the logical unit, the output of the first element AND IS NOT connected to the first input of the third element And the second input and the input of the first delay elements are United and connected with the output of the third element AND IS NOT, the input of the second delay element and the first input of the first element And the joint and is connected to the output element OR the first input of which the input element is NOT United and are requested by the input device, the output element is NOT connected to the first input of the second element AND IS NOT, a second input, the second input of the first element AND the second input of the fourth element AND NOT joint and are the second-synchronization input device, the third input of the second element AND IS NOT connected to the output of the second element And the second input is connected with the output of the first delay element, the output of the second delay element connected to the second input of the first element And the output of the fourth element AND-NOT and the output of the third element And are respectively you the pout trigger is an input signal of the logic zero of the device, and direct the output of the first trigger is connected with the second input element OR entered the group of sensors of the intensity of the external physical fields and block the formation of pulses of the start of regeneration, the inputs of which are connected to the outputs of the sensors of the intensity of the external physical fields, and the output from the synchronization input of the second trigger. The block pulse shaping regeneration start contains the integrator, performed on the differential operational amplifier, a comparator, and an adjustable DC voltage source, is connected by its output to one of the adder inputs of the integrator, the rest of the summing inputs which are input block, the output of the integrator is connected to the signal input of the comparator, the input reference voltage which is associated with a different output regulated DC voltage, and a comparator output connected to the reset input of the integrator is the output of the block.

Functional diagram of the device for the regeneration control in the semiconductor dynamic memory shown in the drawing.

The device contains the first 1, second 2, third 3 and fourth 4 elements AND NOT the first 5 and second 6 triggers, P4 pulse shaping regeneration start and a group of sensors 15.1 15.k the intensity of the external physical fields. The drawing also shows the first clock input 16 and output 17 start request input 18, a second clock input 19 output 20 Gating the address line (signal output ) and the output 21 of the Gating address column (output signal ), the control input 22.

A device for the regeneration control in the semiconductor dynamic memory works as follows.

In the initial state triggers 5 and 6 are zeroed at the inputs 16 and 19 are high voltage levels of the logic unit log. 1), and at the inputs 18 and 22 low logic zero (the log. 0), the output of the OR element 12 and the output element And 7 are log. 0, and the outputs of the elements AND NOT 1 and 3 log. 1. As a result, the output 17 of the device is present in the log. 0, and the outputs 20 and 21 of the log. 1.

In the absence of memory requests on the next positive edge at the input of the synchronization of the trigger 6, the latter is installed in the unit, and the log. 1 with its direct output is fed to the first input element And 8. As the second of its input is also present log. 1, a high level from the output element And 8 is supplied to the third input element AND NOT 2. On the first two inputs of this element are the log. 1, therefore, outputs its log. 0, prog is to the reset input of the trigger 6. The latter is returned to the zero state at the output of the element And 8 is the log. 0, and the output element AND-NOT 2 log. 1.

The transition in the trigger unit 5 (one state trigger 5 is a sign of the regeneration cycle) causes the appearance of a log. 1 at the first input element AND NOT 1. As to the second input of this element is also present log. 1, it outputs a low level voltage, which, passing through the element And 9, available at the output 21 of the device as a signal . At the same time a high level with direct access to the trigger 5 is supplied to the second input of the OR element 12, passes it, and it appears at the first input element And 7 and the input of the delay element 11. The propagation time through the delay element 11 is determined by the interval between signals and in the regeneration mode, after which the second input element And 7 is also provided a high level voltage. As a result, outputs its log. 1, issued on the item And 8, resulting in outputs its log. 1, issued on the output device 17 in the form of a signal "Start". The latest comes in the shape of added RAM, which can be made on the basis of the shift register or delay line.

In response, oneiroi input 16, and the detainee regarding him for some time , received at the clock input 19. The low level of the clock is held at the second input element is NOT 1 and 4 and causes the appearance of the entrances to the log. 1, which leads to the completion of the issuance of the signals and . The first synchronization signal is supplied to the synchronization input of the trigger 5 and, since the input data is present in the log. 0, rear positive front returns the trigger to the zero state. Reset trigger 5 leads to the completion of the issuance of the START signal and guarantees the preservation of high levels at the outputs 20 and 21 of the device after the issuance of the second clock .

If you need to write or read information from the drive to the input device 18 receives a high level signal REQUEST. He runs at the first input of the OR element 12, and generates at its output a log. 1, then, similarly to the regeneration mode, the outputs 17 and 20 of the device generates signals the START and . The formation of the signal on the input 22 of the device is a high level controlled signal panel, the rear edge of which is determined by the time when the recording or reading data from the drive. Because the maintenance cycles of the external request trigger 5 saves zero SOS the exhaust gas. 0, in the future it through the element And 9 available at the output 21 of the device as a signal .

Two variants are possible conflicts between regeneration and external requests to the drive. The first request to the drive comes during a regeneration cycle; the second requirement of regeneration (positive differential voltage on the trigger input trigger 6 occurs in the process of servicing the request to the drive).

If the request to the drive occurs during the regeneration cycle, the log. 1 at the output of the OR element 12 is retained after reset trigger 5 on the trailing edge of the first clock , the START signal at the output 17 remains in the state log. 1, so at the end of the second synchronization signal on both inputs of the element AND NOT 4 is a high level voltage and the output 20 is given the signal , and the duration of the pause between signals required for normal operation of the LSI RAM is determined by the duration of the synchronization signal . Issuance of a signal at the output 21 is carried out by the control signal of the control input 22 as described above.

If the demand regeneration occurs during the cycle of the access drive, the high level voltage of the direct trigger output 6 chehade 18, the output element 13 and the first input element AND-NOT 2 present the log. 0, so the output element AND-NOT 2 saved a log. 1 and the trigger 5 remains in the zero state. With the arrival of the control signal at both inputs of the element AND NOT 3 is the log. 1, and at its output to the log. 0. The last is the element 10 of the delay element And 8 and is supplied to the third input element AND NOT 2, confirming the log. 1 at its output in the log. 1 at the output of element AND-NOT 2 continues after removal of the signal REQUEST from input 18.

Upon completion of the write or read data from the drive signal control input 22 is removed, and the output element AND-NOT 3 appears in the log. 1. After the delay element 10 and the element And 8, it is supplied to the third input element AND-NOT 2 at all three inputs of which are high voltage levels. At the output of the element AND NOT 2 is formed log. 0, and the trigger 5 passes in one state. As a result, the outputs of the device generates signals the START, and according to the timing chart corresponding to the regeneration mode, and the duration of the pause between signals required for normal operation of the LSI RAM is determined by the transit time of the log. 1 through the delay element 10.

In high-speed RAM signal panel can be NSA before the end of the clock , low level which is present at the second input element AND NOT 2. This allows to complete the cycle of writing or reading data until the circuit characteristic of the loop.

The frequency of regeneration cycles is determined by the repetition period of the pulses from block 14 forming pulses of the start of regeneration, which can be used in the Converter of the sum of input voltages in frequency. The source of input voltages block 14 are measuring sensors 15.1 15.k. Depending on the operating conditions of a semiconductor dynamic memory group of the measuring sensors of the intensity of the external physical fields can contain intensity sensors and radiation sensors of electromagnetic field strength, etc.

The work of the above options for performing block 14 forming pulses of regeneration start is as follows.

At the output of the integrator is formed by linearly increasing voltage, the slope of which is determined as the time constant of the integrator and the values of input voltages, and the input coefficients of the respective inputs of the integrator. When reaching a linearly increasing output voltage of the integrator, Ural branch of the ODA unit 14 receive a positive voltage. This signal, when the reset input of the integrator, clears its output voltage, resulting in the signal at the comparator output returns to zero. Thus, at the output of the comparator, i.e. the output of block 14, the pulses of positive polarity, the minimum frequency of which is determined by the time constant of the integrator and the values of the voltage levels at the outputs of the regulated DC voltage source.

Coming to the other inputs of the integrator voltage outputs of the sensors 15.1 15.k increase the steepness of the output voltage of the integrator and, therefore, the frequency of the pulses at the output of block 14. The frequency generated at the output of block 14 of the pulses varies in accordance with changes of the output voltages of the sensors 15.1 15.k, that is, in accordance with the current values of the intensities controlled by sensors of physical fields.

Thus, the device made according to the invention allows not only to resolve conflict between requests to the drive and regeneration requirements and carry out the regeneration using the internal counter of the regenerated lines in BIS RAM, but also adapts to current conditions is upucka the regeneration mode the maximum allowable operating conditions average effective memory bandwidth while maintaining the required noise immunity and reliability.

1. A DEVICE FOR the REGENERATION CONTROL IN the SEMICONDUCTOR DYNAMIC MEMORY, containing the first, second, third and fourth elements, AND is NOT, first and second triggers, the first, second and third elements, the first and second delay elements, the element OR the element is NOT the first input of the first element AND is NOT connected to the direct output of the first trigger, the trigger input of which is the first clock input devices, the output of the second element AND is NOT connected to the set input of the first trigger, the inverted output of which is connected with the reset input of the second trigger and the first input of the third element AND NOT, the second input of which is a control input device, the first input of the fourth element AND is NOT connected to the output of the first element And is the start output device, the first input of the second element And is connected to the direct output of the second trigger, the information input which is the input signal of the logical unit, the output of the first element AND NOT connected to the first input of the third element And the second input and the input of the first delay elements are United and connected with the output of the third element AND NOT the input of the second delay element and the first input of the first element of the UIS request from the input device, the output element is NOT connected to the first input of the second element AND NOT the second input, the second input of the first element AND NOT the second input of the fourth element AND NOT joint and are the second sinhroniziram input device, the third input of the second element AND is NOT connected to the output of the second element And the second input is connected with the output of the first delay element, the output of the second delay element connected to the second input of the first element And the fourth element AND NOT the output of the third element And are respectively output Gating the address lines and the output Gating the address column of the device, the information input of the first trigger is the input signal of the logic zero of the device, and direct the output of the first flip-flop connected to a second input of the OR element, characterized in that it introduced the group of sensors of the intensity of the external physical fields and block the formation of pulses of the start of regeneration, the inputs of which are connected to the outputs of the sensors of the intensity of the external physical fields, and the output from the synchronization input of the second trigger.

2. The device under item 1, characterized in that the power generating pulses of regeneration start function is constant voltage, connected by its output to one of the adder inputs of the integrator, the rest of the summing inputs which are input block, the output of the integrator is connected to the signal input of the comparator, the input reference voltage which is associated with a different output regulated DC voltage, and a comparator output connected to the reset input of the integrator is the output of the block.

 

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