A device for the regeneration control in the semiconductor dynamic memory device

 

(57) Abstract:

The invention relates to computer technology and can be used for data recovery in the semiconductor dynamic memory devices included in a specialized computers which are exposed during operation to physical fields of high intensity. The device comprises a first 1 and second 2 clocks, the first 3 and second 4 triggers, the second 5 and the first 6 bus shapers, block 7 local control, counters 8, a decoder 9, the encoder 10, the register 11, the And gate 12, the element OR 13, the block of code generation control frequency of regeneration 32, the group of sensors of the external parameters of physical fields 33. 2 Il.

The invention relates to computer technology and can be used for data recovery in the semiconductor dynamic memory devices included in a specialized computers which are exposed during operation to physical fields of high intensity, such as in information-measuring systems of control of the radiological situation in x-ray and NMR tomography in industrial robots is magnitnykh fields in the first place it is necessary to ensure the safety recorded in the storage device information. This problem is often solved by the use of computer systems semiconductor dynamic memory device (DZU), which is periodically regenerating the stored information. Thus the regeneration of the contents of the memory cells is made through pre-defined and, as a rule, constant time intervals, determining the duration of which should be considered two contradicting one another circumstances.

First, when working DZU in the regeneration mode, it cannot communicate with other parts of the computer, which is interrupted during execution of the regeneration cycle. Therefore, to reduce unproductive total cost of machine time required to increase the interval of time between cycles of regeneration, that is, reducing the frequency of regeneration start DZU.

Secondly, stored in the memory cells DZU information will be disrupted, and therefore to improve noise immunity, DZU and increase reliability at the expense of the security listed in the data it is necessary to reduce the time interval between cycles of regeneration, that is, to increase the purity of the regeneration start DZU.

Ivalsa the rate of destruction of the recorded information, that requires increasing the frequency of regeneration start DZU, resulting in an additional decrease in computer performance.

When operating the computer with DZU in stable conditions, it is possible to select the optimal frequency of regeneration start DZU, which produces the desired robustness and reliability DZU at a specific and constant reduction of its performance.

In the case of impact on a computer with a semiconductor DZU physical fields of varying intensity maintaining constant the frequency of the regeneration start DZU at higher intensity fields in excess of the specified values can lead to malfunctions of the computer due to a sharp reduction in the reliability of the COUNTRY. The choice of high frequency regeneration DZU-oriented maximum peak intensity values of physical fields, leads to unnecessary loss of machine time for medium and low intensity.

The software automatically changes the frequency of the regeneration start DZU depending on intensity changes affecting computer external physical fields will eliminate the deficit.

A device on the regeneration of memory cells, located in the row to which there was no treatment when recording information in the memory, and due to the implementation of the regeneration only those previously involved rows of memory that are not being accessed for a specified period of time [1]

The known device for the regeneration of the dynamic memory includes first and second clocks, the first and second triggers, the first and second bus shapers, local controls, a group of counters, decoder, encoder, Ledger, item, element, OR an element of delay, trigger group and the group elements And the output of the first clock state clock inputs connected to the unit of local government and first trigger, a direct output which is the output requirements of a direct memory access (RAP), input provision RAP installation is the input of the second trigger, direct output which is the output of the confirmation of the seizure of the canal, and is also connected with control inputs of the first and second tire shapers, with the input of the operation mode of the unit of local government and with the reset input of the first trigger, set input connected to the output element OR inverted output of the second trigger poseiden is s, and the output to one input of each of the elements And groups of elements, And another input of each of which is connected to the direct output of a corresponding trigger trigger group, and the output from the counting input of the corresponding counter group counter, the output of the high-order bit of each of which is associated with one of the inputs of the OR element and one of the inputs of the encoder, the outputs of which are connected to the inputs of the second bus driver whose outputs are the outputs of the address, the entrance gate is the input of the delay element, the output of which is connected to the reset input of each of the triggers in the trigger group, installation input of each of which is connected to the corresponding output of the decoder, connected their information inputs to the outputs of the register, the information inputs which are address inputs, the outputs of the first bus driver are control outputs, control inputs is the group of inputs of local controls, the group of outputs of which are connected with inputs of the first bus driver, local controls its outputs the synchronization signal and the enable signal write is connected to the corresponding inputs of the register is showing the trigger when this input is reset each of the counters group is associated with a corresponding output of the decoder.

However, this device does not provide when the intensity of external physical fields automatically change period of time, after which start the regeneration of previously used memory cells.

Object of the invention is the provision of opportunities for adapting the frequency of the regeneration start DZU intensity of the external physical fields, which allows to increase the average effective performance DZU while maintaining the required noise immunity and reliability, resulting in improved performance of the computer.

This is achieved in that in a device for the regeneration control in the semiconductor dynamic memory device containing the first and second clocks, the first and second triggers, the first and second bus shapers, local controls, a group of counters, decoder, encoder, Ledger, item, element, OR an element of delay, trigger group and the group elements And the output of the first clock state clock inputs connected to the memory block, entrance provide direct access to the memory is setup the input of the second trigger, a direct output which is the output of the confirmation of the seizure of the canal, and is also connected with control inputs of the first and second tire shapers, with the input of the operation mode of the unit of local government and with the reset input of the first trigger, set input connected to the output element OR an inverse input of the second trigger is connected to one input element And the other input of which is connected to the output of the second clock, and the output to one input of each of the elements And groups of elements And, another input of each of which is connected to the direct output of a corresponding trigger trigger group, and the output from the counting input of the corresponding counter group counter, the output of the high-order bit of each of which is associated with one of the inputs of the OR element and one of the inputs of the encoder, the outputs of which are connected to the inputs of the second bus driver whose outputs are the outputs of the address, the entrance gate is the input of the delay element, the output of which is connected to the reset input of each of the trigger group setting input of each of which is connected to the relevant inputs of which are the inputs of the address, the outputs of the first bus driver are control outputs, control inputs is the group of inputs of local controls, the group of outputs which are connected with inputs of the first bus driver, local controls its outputs the synchronization signal and the enable signal write is connected to the respective input register, the output signal Gating to the control input of the decoder, and output the reset signal to the reset input of the second trigger, introduced the group of sensors of the external parameters of physical fields and the block code generation controls regeneration frequency, the inputs of which are connected to the outputs of the group of sensors of the external parameters of physical fields, and outputs the information inputs of all, in addition to senior, ranks each counter group counter, entry permit records each of which is connected to the corresponding output of the decoder.

In Fig. 1 presents a functional diagram of a device made according to the invention; Fig. 2 timing diagram of the operation of the device in the regeneration mode information.

The device comprises a first 1 and second 2 generators clock them the IKI 8, the decoder 9, the encoder 10, the register 11, the And gate 12, the element OR 13. In Fig. 1 also shows the elements of computers that communicate with the Central processor 14 and memory 15, which is used semiconductor DZU. In addition, in Fig. 1 shows the output of the 16 requirements of the direct memory access (RAP), the input 17 of the provision of the RAP, the output 18 of the acknowledgement channel capture (PZ), the address bus 19 bus 20 memory management, group 21 and outputs a group of 22 unit 7 local control input 23 of the operation mode of the block 7 local control, the output 24 of the synchronization signal, the output 25 of the signal recording resolution, the output 26 of the signal Gating, the output 27 of the reset signal, engraved 28 unit 7 local control.

In addition, the device contains an element 29 delay, trigger group 30.1,30.i,30.n group elements And 31.1,31.i,31.n, block 32 code generation control frequency regeneration group 33 of the measuring sensors of the external parameters of physical fields and input 34 Gating record.

As block 7 local control can be used the local controls of the known device.

Group 33 of the measuring sensors of the external parameters of physical fields can contain, electromagnetic fields, etc.

When using sensors with analog output unit 32 code generation controls regeneration frequency can contain, for example, the weight analog adder, the inputs of which are the inputs of the block, and analog-to-digital Converter that converts an analog signal at the output of the adder to the output code block 32.

When using sensors with digital output unit 32 may be made in the form of multi-input summing device performing the weighted summation of the input codes.

If you are using sensors with analog output and digital, in this case, to one input multi-input summing device can be connected to the analog-to-digital Converter that converts the code signal output analog weighting adder processing output signals of the respective sensors.

The device operates as follows.

In the initial state triggers 3, 4, 30.1 30.n reset and the counters 8 8.1. n is reset to zero, and the output unit 7 zero signal levels. The pulses from the output of the generator 2 clock pulses through the element 12 And the element group And 31.1 31.n for counting input of the counter 8 correspond to the addresses of the rows that have the si information in the memory, the pulses will not be received, since the corresponding elements And 31.1 31.n group blocked low levels of the signals on the respective outputs of the triggers 30 30.1.n group.

Overflow of one of the counters 8 8.1.n output it to the senior level through the element OR 13 is fed to the input setup trigger 3.

At the same time at the output of the encoder 10 is installed counter code 8.i (from 1 to n), the corresponding code line address those memory cells that have reached the time information storage and requires regeneration.

On the leading edge of the pulse generator 1 clock pulse sets the trigger 3, the direct output of the signal 16 requirements for direct memory access. The processor 14 suspends the execution of operations, releases the address bus 19 and generates a signal in response to the input 17 of the provision of the RAP sets the trigger 4, which in turn resets the trigger 3, produces a signal at the output 18 of the acknowledgement channel capture (PZ), and opens the bus formers 5 and 6.

The signal from the inverted output of the trigger 4 prohibits the passage of the pulse generator 2 clock pulses through the element And 12 to the inputs of counters 8. From a trip to the RAM 15 and the removal of the synchronization signals of the active device (XIA), synchronization passive device (XIP), arriving at the inputs 22 of block 7 of the local government, the formation of a positive differential clock pulse (T) from the generator 1 clock signal regeneration (group) on one of the outputs of the group 21 of the output unit 7 local control. This signal is applied via a bus driver 6 in the RAM 15 and remains active during the whole time of regeneration.

On the following clock pulse unit 7 local government forms on the respective outputs of the group of 21 outputs signals SIA and Enter that come in the RAM 15 via a bus driver 6 together with the address code timing from the output bus driver 5. At the same time code address line is supplied to the information input of the register 11. The entry in the register 11 is on the leading edge of the signal at the output 24 of the synchronization signal coming from block 7 local control. In response to the signal input of the RAM 15 generates a signal XIP received in block 7 through a group of 22 inputs. After this one MINUTE is removed signal "Input", in response to which the memory 15 removes the signal XIP. On the second then T is removed signal SIA and trailing edge e is engaged, the input of the decoder 9, writing thus in the counter 8.i code stored in the register 11, the code generated at the outputs of block 32 code generation controls regeneration frequency. Following this, at the output 27 of the reset signal pulse appears, Abdoulaye the trigger 4. Removed signals group and PZ, the regeneration cycle is completed.

Thus, it can be done for regeneration of any line in the RAM 15. If during operation of the device, none of the counters 8 is not full, i.e., the time information storage or for one line has not been released, the operation of the device is as follows.

In the mode of accessing the memory 15, the CPU 14 sets the bus 19 address code memory cell, and on the bus 20 produces the control signals received in block 7 of the local management group 22 inputs: channel synchronization signal passive device (XIP), channel select signal from an external device (CEF). Low-order bits of code addresses, which is the code line address signal from the output 24 of the block 7 local control in the presence of the enabling signal at its output 25 of the signal recording resolution recorded in the register 11. Prohibiting the entry signal appears on the output unit 7 is formed local signal at the output 26 of the block 7 local control.

Because when accessing the RAM 15 is the regeneration of all the memory cells specified by the address line, then at the end of the trip to the RAM 15 to the output signal 26 of the block 7 of the local control signal output from the decoder 9 is the entry code from the outputs of the block 32 in the counter 8.1 serial number that matches the address code string stored in the register 11. A request for regeneration of the cells of the RAM 15 with the given string address can come from the output of the counter 8, only through time Tgroupperiod of regeneration, provided that during this time, the CPU 14 will not apply to cells with the same address line.

Current codes counters 8.1 8.n determine the allowable storage time information for each row of the RAM 15, which may not exceed the value defined by the expression

TGROUP= (2k-1-N) where f2the frequency of the pulses at the output of the generator 2 clock pulses;

To the bit width counter 8 8.1.n;

N (K-1) bit code output unit 32 code generation control frequency of regeneration.

Code number N is generated by the block 32 code generation control frequency regeneration engaged muuusic on DZU external physical fields outputs of the group 33 of the measuring sensors. In the simplest case, the code number N is a linear combination of the values of the measured parameters to a common scale using a weighted summation. The only important thing is to increase the current value of the at least one parameter (given the current values of other parameters) led to the increase in the number of n

While there are no fundamental restrictions on the implementation of more complex functional dependencies of the number N from the measured current values of the parameters characterizing the intensity affecting DZU external physical fields. In particular, both the inputs and outputs of the block 32 can be installed functional converters, or the unit 32 may be implemented as a specialized evaluator performing more complex processing of input data.

As follows from the formulas above, with increasing number N due to the increase in the intensity of affect DZU external physical fields the value of the permissible time of storage of information for each row of the RAM 15 is reduced, that is, increases the frequency of regeneration of the mesh the Finance record incoming on the state clock inputs of the triggers 30 30.1.n group via element 29 delay, the corresponding trigger is set in one state, because the installation log he is a high signal generated by the decoder 9. Installation of the trigger 30.the first group occurs during the initial recording information when re-accessing the RAM cells 15 with the same address line, the trigger 30.i remain in the established state, the element 29 delay also provides a matched load characteristics of the main processor 14 state clock inputs of the triggers 30 30.1.n group.

Thus, from the cycle of regeneration no regeneration of cells of a dynamic memory which does not add information.

A DEVICE FOR the REGENERATION CONTROL IN the SEMICONDUCTOR DYNAMIC MEMORY DEVICE containing the first and second clocks, the first and second triggers, the first and second bus shapers, local controls, a group of counters, decoder, encoder, Ledger, item, element, OR an element of delay, trigger group and the group elements And the output of the first clock state clock inputs connected to the unit of local government and first trigger, the direct output of which is the adjustment input of the second trigger, direct output which is the output of the confirmation of the seizure of the canal, and is also connected with control inputs of the first and second tire shapers, with the input of the operation mode of the unit of local government and with the reset input of the first trigger, set input connected to the output element OR an inverse input of the second trigger is connected to one of inputs of the element And the other input of which is connected to the output of the second clock, and the output to one of the inputs of each of the elements And groups of elements, And another input of each of which is connected to the direct output of a corresponding trigger trigger group, and the output from the counting input of the corresponding counter group counter, the output of the high-order bit of each of which is associated with one of the inputs of the OR element and one input of the encoder, the outputs of which are connected to the inputs of the second bus driver whose outputs are the outputs of the address, the entrance gate is the input of the delay element, the output of which is connected to the reset input of each of the trigger group setting input of each of which is connected to the corresponding output of the decoder, connected their information inputs to the outputs registrasie output device, control inputs is the group of inputs of local controls, the group of outputs of which are connected with inputs of the first bus driver, local controls its outputs the synchronization signal and the enable signal write is connected to the corresponding inputs of the register, the output signal Gating to the control input of the decoder, and output the reset signal to the reset input of the second trigger, characterized in that it introduced the group of sensors of the external parameters of physical fields and the block code generation controls regeneration frequency, the inputs of which are connected to the outputs of the group of sensors of the external parameters of physical fields, and outputs information all inputs, except the eldest, bits for each counter group counter, entry permit records each of which is connected to the corresponding output of the decoder.

 

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