A device for the separation directions of transmission and reception in full duplex communication systems

 

(57) Abstract:

Usage: telecommunications. The inventive device includes an input unit 1, unit conversion layer 2, the differential system 3, ADC 4, block addressing 5, the memory 6, 10, generator 7, the computing unit 8, an adder 9, the control unit 11, the threshold unit 12, the trigger 13, the corrector 14. 2 C.p. f-crystals, 2 Il.

The invention relates to telecommunication.

It is known device, comprising sequentially connected to the input unit, the switch, the first digital to analog Converter, analog-to-digital Converter, the first memory block, myCitadel, a second input coupled to the output of the analog-to-digital Converter, an adder, a second memory block, an output connected to a second input of the adder, and the second d / a Converter, former address and generator.

The objective of the invention is to increase the noise immunity of the received message.

In Fig. 1 shows a block electrical diagram of Fig. 2 scheme of the first memory block.

The device comprises an input unit 1, unit 2 level conversion differential system 3, an analog-to-digital Converter 4 (DAC), which means, the threshold unit 12, the trigger 13, the corrector 14.

Block addressing contains random access memory 15, the parallel register 16, an adder 17, the counter 18 with the preliminary record, the serial register 19.

The first block of memory includes random access memory 20, the parallel register 21, the key 22.

The device operates as follows.

There are four simultaneously occurring process, which, in turn, are linked.

The first process is the formation of the transmitted signal. This operation is cascade connected to the input 1 block, block 2, level conversion and differential system 3, which transmits signals to its own transmission in the direction of transmission.

The second process is the formation of address for normal operation of the device. This operation is carried out with the help of block 5 addressing, where the component parts include a serial register 14, a random access memory 15, the parallel register 16, an adder 17 and the counter with a prior record of 18.

The third process is the compensation signals its own transmitter in the reception path. He osushestvlyaetsya 14, analog-to-digital Converter 4, the memory block 6 and block 8.

Finally, the fourth process is to restore the shape of the received signal. He is using the adder 9, the second memory block 10, a threshold unit 12 and the trigger 13.

All the above processes are controlled by the control block 11 together with the generator 7.

Now consider in more detail the above processes.

So, the first process, as mentioned earlier, is necessary for the formation and simultaneous binding to a clock frequency signal to be transmitted. The input signal is supplied to the input of the input unit 1, representing essentially normal On the trigger. To the clock input of the input unit 1 receives the clock synchroshuttle from the output of the generator 7. The output signal of the input unit 1 is identical to the input signal, but the appearance of it is strictly synchronized with the clock frequency. Next, the transmitted signal enters the unit 2 level conversion. For a two-level signal block 2 level conversion is the comparator to the second input of which is filed with the threshold value. When forming the output of the input unit 1, the logical unit to the output unit 2 one signal block 2 level conversion will be equal. Next, the transmitted signal is fed to the input lines of communication through defsystem 3 and at the same time due to the coupling parameters defsystem 3 in the reception path. Thus, the first process ends.

The second and third processes are interrelated. Let us consider them in more detail. Thus, at the output of defsystem 3 observes the sum of two signals: received from station B and own flowing into the reception path. The total signal received at the input of the corrector 14, the adjustment of the amplitude-frequency and phase-frequency distortion of the communication line (hereinafter ACI, PCI). The corrector 14 eliminates ACI, PCI the received signal. For its own transmitted signal corrector 14 distorts the shape of the parasitic signal, however, due to the linear nature of the corrector 14 this will not affect the future work of the compensation of the transmitted signal. For compensation of own signals of the transmitter in the reception path used the law of relativity. Under this law, if you know the sequence of transmitted symbols, the interference signals from its own transmitter in the reception path can be accounted for by subtracting it on a nearby clock intervals. Let the output of the input unit 1 is peridot time. From the transmitted signals at the output of ACHR observed interference is

P1(K1t) S1(K1t) * gDS(K t) * *Lcor(T) (1)

P2(K2t)= S2(K2t) * gDS(K t) * Lcor(K t)

< / BR>
< / BR>
Pn(Knt) Sn(Knt) * gDS(t) * Lcor(K t) Here gDS(T) the impulse response defsystem 3 in path nepomucene signals

Lcor(t) impulse response of the corrector 14.

Because of the linear nature of the impulse response of defsystem 3 and corrector 14 we can say that the transmitted signal S1(K1t) corresponds to the interference of the P1(K1t). Similarly, the signal S2(K2t) corresponds to the interference of the P2(K2t), and so on, it Should be said that the parameters defsystem 3 and corrector 14 can vary in time due to the change settings link. This will cause the magnitude of the noise counts Pi(Kt) will change. However, according to the law of relativity the magnitude of these changes on adjacent clock intervals will be small. In fact, we let transmits the signal S1at time K1t and K10t. In the first case, the output ACHR is an obstacle equal to P1(K1t), while in the second the capacity of the communication line. Similarly, if next TO20t re-transmitted signal S1on the output of the ADC 4 is an obstacle equal to P1(K20t) P1(K10t) +a2and so on

Then according to the law of relativity compensation signals its own transmitter in the reception path would be to subtract the signals on adjacent clock intervals. For the purpose memory block 6 and block 8. So, let the output of the ADC 4 on the i-th clock interval during transmission (for example) the observed signal is equal to

Li(Kit) P1(Kit) + yi(Kit) (2) Here yi(Kit) is the reference signal.

According to the previously mentioned using block addressing 5 we have in the memory unit 6 to find the memory location where you previously recorded a hindrance P1. Let such a cell is found, where the signal is equal to

Lm(Kmt) P1(Kmt) + ym(Kmt) (3) Then the output of block 8 will have a signal equal to

Mi(Kit) Li(Kit) Lm(Kmt)yi(Kit) tm(Kmt) (4) As can be seen from (4), there is no amount of interference from its own transmitter.

Show how you specify the desired memory cell to stupet block addressing 5 on the serial input of register 19. The sequence of zeros and ones, which is transmitted towards station B simultaneously retained in the serial register 19. Thus, the output signal of the serial register 19 is a set of ones and zeros that are transmitted in real time and in the previous cycles of transmission. The operation of delaying the transmitted signal in the serial register 19 this is essentially a form signals S1, S2. Snfor management unit 6 memory, as each sequence of zeros and ones corresponding interference from the transmitter to the receiver input. If we denote by N the number of digits on the serial output of the register 19, and through the M number of address digits of the memory unit 6, M > N. the Remaining bits of the (M-N) are formed by using the memory unit 15, the parallel register 16, adder 17 and counter with a prior record of 18. Show how this is done.

Let the transmitted signal is stored in the serial register 19 has the form 10001011 (N 8) at time t1. In the next moment of time t2in the serial register 19 all information is shifted one step to the right, when atetra 19 is a signal equal 01000101. To control the operation of memory unit 15 are used in combination, shifted one digit to the left of the combinations at the input of the memory unit 6. So, at time t1in the direction of the memory unit 6 receives the signal 10001011, and the address inputs of RAM 15 enters code combination 01000101. This sequence prepares the work RAM 15 when the next code combination. The bit width of the RAM 15, the parallel register 16, adder 17 are the same and equal To the digits.

Even in the first moment of time t1The RAM 15 has been reset. Then with the advent of time t1code combination 01000101 of the RAM 15 with this address is read zero and is recorded on the signal output from the control unit 11 in parallel to the register 16. Further, the outputs of the parallel register 16 formed in the adder 17 with the unit and is recorded in the RAM 15 at the same address 01000101. Since the beginning of time interval t2the signal from the parallel register 16 is written to the counter 18, which under the action of clock pulses starts to change its state from a previously installed state. For example, at time t2in the counter 18 enrolled 0. After this sostoyaniya 18: 1,2,3.15,0.

When at some regular t1the clock interval of the address inputs of RAM 15 code combination 01000101, from the RAM 15 is a unit that can be written in the parallel register 16, and the RAM 15 will be written the number "2" and so on, Thus, using a RAM 15, a parallel register 16 and the adder 17 different code combination is the increase in the content of the RAM 15 per unit. Upon reaching the RAM 15 state IIIl, in the RAM 15 will be written to "0" (IIII + 0001 0000, the transfer is discarded). This behavior allows to adapt the parameters of the communication line. So, at time t1the address inputs of the memory block 6 enter the code combination 010001010000, 010001010001, 010001011111 at time t2the address inputs of the memory block 6 enter the code combination in the form of 010001010001, 010001010010, 010001010000.

As can be seen from the description above, the N high-order bits at time intervals ti-ti+1unchanged, and the remaining "K" bits change. Since the most significant bit unchanged, and disturbance Piat the output of the ADC 4 will be about the same. From the first memory block 6 on the first formed from a block of address 5 address first reads the contents of the corresponding memory cell.

In the cell with acerentomata only read. Then at the output of the memory block 6 appear for the first time P1(K1t) + y1(K1t), the second moment of zero (write data), the third P1(K3t) + +y3(K3t). in the sixteenth P1(K16t) + y16(K16+ t). In this address to the memory unit 6, the first members of the above-listed sequences are equal, and the second random members. Thus, at the output of vicites 8 is a signal in the form

yi(Kit) t1(K1t); yi(Kit) y3(K3t);

yi(Kit) y16(K16t) (5)

When reading information, the key 22 is closed, the signal from the outputs of the RAM 15 via a common bus arrives at the parallel inputs of the register 21. The recording signal in the parallel register 21 is produced on the signal output from the control unit. In the case of recording information in the RAM 20 is opened, the key 22 and through a common bus signal write goes to the inputs/outputs of the RAM 20. Modes of operation key 22. RAM 20 and the output of the register 21 is strictly synchronous and are controlled by the output signal of the control unit and block addressing. The second and third stages are over.

The fourth stage is designed to restore the shape of the received signals. Because the device PrEA value [yi(Kit) > 0] and then the entire sequence is either a positive value or zero value when the components are the same in magnitude and sign. Using the adder 9, the second memory block 10 is the summation of all components from the output of vicites 8.

The output signal of the adder 9 is described by the expression

Q[yi(Kit)-yj(Kjt)]

Thus, if the samples of the received signal yido not have a permanent component, the sign of the value Q is uniquely characterizes the sign of the received signal. It's more complicated if each sample of the received signal has a DC component. Then the output signal of the adder 9 is compared with a threshold value in the threshold block 12. The threshold value in the threshold device is selected from a ratio

R 2toFrom Here the magnitude of the DC component of the received signal

P value threshold

K - the number of bits of the counter 18

(M N)

Then, if Q > P, the trigger receiving 13 is written to the logical unit. If Q < P, the trigger receiving 13 is written to zero.

Thus, the output trigger signal reception 13 uniquely characterizes the sign of the received signal Si leads to the change of interference samples, which are recorded in the memory unit 6. Thus, after a few cycles of transmission changes due to interference samples Pifrom the signals of its own transmitter compensation will be the same.

1. A device FOR the SEPARATION directions of TRANSMISSION AND RECEPTION IN a DUPLEX COMMUNICATION SYSTEM comprising a generator, the first output of which is connected to the first input of the input unit, the input of the analog-to-digital Converter and the first inputs of the first and second memory blocks, the outputs of the latter are connected respectively to the first inputs of the subtraction unit and the first memory block, a second input connected to the output of the adder, a second input connected to the output of the subtraction unit, characterized in that the input unit control unit addressing, the threshold block, trigger, connected in series block level conversion differential system and corrector, moreover, the first and second outputs of the control unit connected with the first and second inputs of block addressing, the first and second outputs of which are connected to third and fourth inputs of the first memory block, a fifth input connected to the third output of the control unit, the fourth output of which is connected to the third input of the second block pathologe block, an input connected to the output of the adder, the output of the corrector is connected to the second input of the analog-to-digital Converter, the input of the conversion unit level is connected to the output of the input unit, the second output of the generator is connected to the input of the control unit.

2. The device under item 1, characterized in that the block address contains an adder and consistently connected the serial register, random access memory, the parallel register and counter with pre-entry, with the parallel output of the register is connected to the input of the adder, the second input of the serial register, random access memory and a parallel register are combined and the first input block addressing, second and third inputs of which are respectively the second inputs of the counter with a prior record and the serial register, and outputs the second output serial register and counter with a prior record.

3. The device under item 1, characterized in that the first memory block contains connected in series key and the output register, as well as online storage device, the information input / output connected to the input of the output regisrar connected respectively to the first input key, joint second inputs of the operational storage device and the output trigger, third and fourth inputs of the random access memory device and combined with a second inlet valve and the fifth input of the memory device.

 

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