A device for the separation directions of transmission and reception in full duplex communication systems

 

(57) Abstract:

Usage: in telecommunications, primarily for the transmission of digital signals via communication cables. The purpose of the invention: improving the noise immunity of the received signals. The inventive device includes an input unit 1, unit 2 level conversion, defsystem 3, analog-to-digital Converter 4, the serial register 5, the blocks 6 and 10 memory generator 7, myCitadel 8, the adders 9 and 12, the parallel register 11, the trigger 13 and the control unit 14. 1 C.p. f-crystals, 2 Il.

The invention relates to telecommunications, mainly for the transmission of digital signals via communication cables.

It is known a device for separating directions, designed to be placed in the equivalent bridge circuit, where one diagonal of the bridge is enabled transmitter and the other receiver [1] the Principle of such systems is based on the possibility of organizing duplex communication with perfectly balanced resistances shoulders of the bridge circuit.

However, due to variation in the lines of communication are not able to balance the bridge circuit, therefore, the signals of its own transmitter penetrate into the receiving device, significantly reducing quality is the most closest to the invention by the technical nature of a device [2] including sequentially connected to the input unit, switch, the first digital to analog Converter, analog-to-digital Converter, the first memory block, myCitadel, a second input coupled to the output of the analog-to-digital Converter, an adder, a second memory block, an output connected to a second input of the adder, and the second DAC, former address and generator.

The operation of this device can be explained as follows.

The stream of logical ones and zeros from the output of the source message arrives in the input block, which is made to convert the analog signal into a corresponding set of binary combinations, showing the samples of the signal Ui(k t ), which then, after passing the first digital to analog Converter is converted into a corresponding analog linear signal (t) flowing in the opposite direction. The link comes the signal y(t), which is added to the transmitted signal (t), and the resulting sum is converted to an analog-to-digital Converter in a digital

M(kt)=g(kt)+y(kt).

The signal M(k t) is served in myCitadel and at the same time in the first memory block. Output vicites transmitted signal g(k t) is compensated, and the received signal y(k t) is promodelirovany memory block. Restored received signal y(k t) is then converted into an analog value in the d / a Converter and delivered to the message consumer. The generator generates the appropriate clock sequence, and shaper addresses are required for initial training device separation under the parameters of the communication channel.

This device allows you to separate directions of transmission and reception in full duplex communication systems the coincidence of the spectra of transmitted and received messages.

However, this device works effectively when transferring data over the communication channel. When using data CCITT regulates a special algorithm occurrences in the relationship. This algorithm involves the training device separating areas in the absence of a character of the opposite side.

There are a large number of technical solutions that allow you to use the prototype as a digital defsystem during data transfer. The situation is more complicated when the transmission of digital information with greater speed communication cables using duplex digital regeneration points. When using the prototype for these purposes requires the specification of the opposite station are not guaranteed when using tens and maybe hundreds of recovery points. In addition, the receiver is not able to constantly adapt to the parameters of the communication channel. The result is a low reliability of the received signals coming from the line due to insufficient compensation of the signals your transmitter in the reception path. If the receiver does not use the correlation of the received signal after demodulation.

The aim of the invention is to increase the noise immunity of the signals received.

For this purpose a device for the separation directions of transmission and reception in full duplex communication systems, containing cascading United oscillator, analog-to-digital Converter, myCitadel, a second input coupled to the output of the analog-to-digital Converter through the first memory block, the adder output is connected to its second input via a second memory block and the input block, a second input connected to the second inputs of the first and second memory blocks and the first output of the generator, put the cascade United transform block level and pre-defsystem, the first output connected to a communication line, and a second output from the second analog-digital conversion on the config with the second input of the second adder, connected in series control unit and the output trigger reception, while the second output of the generator is connected to the input of the control unit, the first, second and third outputs of which are connected respectively with the third input of the second memory block, the second parallel input register and a second input of the serial register, the second output of which is connected to the third input of the first memory block, a fourth input connected to the output of the second adder, the output of the input unit is connected with the first inputs of the serial register and block level conversion output of the first adder is connected to a second input of the output trigger reception.

Distinctive structural features of the proposed solution is the introduction of block level conversion prior defsystem, serial and parallel registers, the second adder, a control unit and an output trigger reception, new electrical connection between the newly introduced nodes and receiver nodes, and a new constructive design of control unit. All distinctive design features are of a single set of features, because the elements of the proposed device are interconnected and the CLASS="ptx2">

The device comprises an input unit 1, unit 2 level conversion, defsystem 3, analog-to-digital Converter 4, the serial register 5, the first 6 and 10 second memory blocks, the generator 7, myCitadel 8, the first 9 and second 12 adders, parallel register 11, the output of the trigger 13 and reception unit 14 of the control.

Unit 14 contains a control counter 15 and the decoder 16.

Constructive 11 running parallel and serial 5 registers known. This chip IR, IR, IR etc.

Constructive performance of the ADC 4 is also known. This chip PW, PW etc.

Constructive preliminary defsystem 3 known. It is an integral node of the multi-channel transmission systems.

Constructive design of vicites adders 8 and 9 and 12: chips IN, IM, IM etc.

Constructive execution of blocks of memory chips RU, RU etc.

The generator 7, a counter 15, a decoder 16, the trigger 13 is also known by the nodes. The input unit 1 is a D-flip-flop (TM, TM).

A device for the separation directions of transmission and reception in a duplex communication system includes serially connected input block 1, block 2 preobrazovaniya-digital Converter 4 via the first memory block 6, the first adder 9, the output of which is connected with its second input via a second memory block 10, the output of the trigger 13 of the reception, connected in series generator 7, the control unit 14, the serial register 5, the second adder 12, the parallel register 14, an output connected to a second input of the adder 12, the second output of the generator is connected to the second inputs of the input unit 1, an analog-to-digital Converter 4, the first 6 and 10 second memory blocks, the third and fourth inputs of the first memory block 6 are connected respectively with the output serial register 5 and the output of the second adder 12, the output of the input unit 1 is connected to the serial input of the register 5, the second and third outputs of the control unit 14 is connected to the second parallel input of the register 11, the second inputs of the second memory block 10 and the output trigger reception.

The proposed device operates as follows.

In the process, we can distinguish four basic operations, simultaneously flowing in the proposed device:

1. The formation of the duration and amplitude of the signal being transmitted from station a and station B. This process is performed by the input unit 1, unit 2 level conversion and defective stannage transmitter. This process is sequential register 5, the second adder 12 and the second parallel register 11.

3. Compensation signals its own transmitter in the reception path. This operation is performed, first, by using defsystem 3 in path nepomucene (pre-compensation) and, secondly, by analog-to-digital Converter 4, the first memory block 6 and myCitadel 8.

4. The recovery process of the received signal after compensation of its own transmitted. This operation is performed using the first adder 9, the second memory block 10 and the output of the trigger 13 of the reception.

All of these processes are controlled by the unit 24 controls, an input of which receives the clock pulses from the output of the generator 7.

So, first of all, according to the algorithm of the first process it is necessary to form the transmitted signal shape and duration. The signal to be transferred, is fed into the input unit 1, which essentially is a D-flip-flop. Here is "binding" of the signal being transmitted to the clock frequency of the processing. This operation is necessary because of the fact that all the signal processing device is synchro is m, coming from the generator 7.

Next, the generated binary signal is supplied to the unit 2 level conversion, which converts a single-level signal transmission in the duplex. Unit 2 conversion level has a threshold equal to half of the TTL level. If the transmitted signal differs by more than the threshold, then the output of this block will be generated voltage +U. If the transmitted signal is less than the threshold, then the output of the conversion unit level will be generated voltage U. Thus, the transmitted signal received at the input of the input unit 1, first, is supplied synchronously with a clock frequency and, secondly, all logical units transfer is converted to a voltage +U and the zero signal (-U). A two-level signal through the pre-defsystem comes on line clamps and forth in the direction of station C. In the pre-defsystem in path nepomucene is some attenuation level of the signal being transmitted. This operation is necessary to facilitate the work of the digital part. This ends the first process.

The second process is necessary for forming addresses for the first memory block 6. The formation of addresses necessary for the expressed signal output from the input unit 1 simultaneously fed to the input serial register 5. Clocking the input unit 1 and the serial register 5 is synchronized by the generator 7. Therefore, in the serial register 5 will always be stored To bits of the transmitted signal. Data To bits required to generate an address signal in a given time and K-1 values of the transmission signals that have been transmitted previously. Since the transmitted signal duplex serial register bit. The number of addresses that can appear at the output serial register 5, is 2k. However, in the direction of the first unit 6 memory do not all these combinations. From the transmitted bits of the signal of N bits is fed to the input of the second adder 12, and K-N bits in the direction of the first memory block 6. It is obvious that the mandatory conditions must be N < K Data N bits received at the second memory block 6, which works in conjunction with the parallel register 5. The output signal of the second adder 12 in the form of N bits is also fed in the direction of the first memory block 6. Explain this on a concrete example.

May 8, N 4. At some point in time (denoted by T1in the serial register 5 will be some kind of eight-bit code register 5 are directly to the address inputs of the first memory block. The remaining four categories, i.e., 0100, arrive at the input of the second adder 12. Since N 4, the second adder 12 and the second parallel register 11 is also selected four-digit. It should be noted that the time interval between adjacent samples of the transmission signals (in our case T1-T2) is divided by 2Ntime intervals. At time T1T2. TLthe second parallel register 11 is forcibly reset by the output signal from the control unit 14. When the input transfer Raboutthe second adder 12 receives a constant signal equal to a logical unit. So, at time T1output serial register 5 code combination is received at the input of the second adder 12. Since at time T1the second parallel register 11 was set to zero, then the output of the second adder 12 will see a combination equal to 0101. At time t1this code combination is recorded by the signal output from the control unit 14 in the parallel register 11. So, from the point in time T1-t1in the direction of the first unit 6 memory receives the address signal 11010101. From the moment of time t1and up to t2in the second adder 12 is the addition signal output from computers is tsya combination respectively 0100 and 0101. The output of the second adder 12 is the result of adding two numbers is equal to 1010. This code combination at time t2recorded again in the parallel register 11. Therefore, in the direction of the first unit 6 memory receives an address equal to 110110100. From the moment of time t2-t3the second adder is again the sum of two signals. The result of addition is equal to 1111. The addition by the second adder are for our case 16 times. As a result, the formation of the addresses K-N high-order bits remain unchanged during time intervals Ti-Ti+1and younger N bits change. Moreover, the number of addresses generated in the interval Ti-Ti+1is equal to 2N. For our case, after 16 clock intervals will be formed following addresses: 11010101, 11011010, 11011111. 11010000. Although lower 4 digits not follow in the order of increasing his fortune, but the first unit 6 memory is random access memory random access and therefore the treatment of the cells can be done arbitrary. As can be seen from the description of the second process, the last N bits play a supporting role when addressing, but this is to pensionati transmitted signal in the reception path. Explain the operation in more detail. As mentioned above, defsystem 3 weakens (about 10 dB) transmitted signal in the reception path. At the same time from the station B receives the received signal. At the input of analog-to-digital Converter 4 observe the sum of the two signals. Denote by S1(t) the transmitted signal at the ADC input, and y(t) received signal. Analog-to-digital Converter 4 converts the analog signal into a digital equivalent. Thus, at the output of the ADC 4 observed combination Si(k t) + yi(k t). Here and below, k t denotes discrete time. For compensation of own signals of the transmitter using the law of relativity: a hindrance to the i-th clock interval is compensated by interference from signals of its own transmitter on i-1 clock interval. Denote by S1(k t) signal of its own transmitter output ACP when transmitting the next code combination 10000000, and S2(k t) signal of its own transmitter during transmission of the next code combination 01000000. Similarly, we can denote it by S3(k t), S4(k t). Sk(k t) signals at the output of the ADC 4 when transmitting code combinations 11000000, 001000000.11111111. This will record the memory will output to the input of vicites 8. This procedure reads the records will stay the same throughout the session. For ease of understanding, assume that at initial entry into the communication received signals are absent. Then in the first cell of the memory will be written to the response of the communication channel, is equal to S1(k t), the second S2(k t), and so on, This assumption does not restrict the occurrence in connection with the presence of y(t). But understanding in this case is more complex. So upon initial entry into a relationship with 11 parallel and serial 5 registers, and the second adder 12 is addressing the first memory block 6. Thus, the time interval T1-T2once the recording signal to the address 10000000 and the reading from numbers 10000000, 10000001.10001111. On the interval T2-T3reads the signal from the first memory block address 01000000, 01000001. 0100111 and made a single recording signal to the address 01000000, etc. If the first time the first unit 6 memory was set to zero, the time interval T1-T2the output of the first memory block 6 will be zero. Starting from time T2k+1starts working mode. Let at time T2k+1at the output of the ADC 4 vnode signal, equal to S1(k t)+y1(k t). Since the serial communication parameters change slowly in time, then the law of relativity the signal S1(k t) observed at the output of the ADC 4 in the first moment of time, and T2k+1time on the same code combination 10000000 will be about the same. Then, by reading the previous contents of the first memory block 6 S1(k1t) and feeding it to the second input of vicites 8, it is possible to compensate for the transmitted signal. Indeed, in this case, the output of vicites 8 is a signal equal to

L1(kt) (k t)+y1(kt)-S1(k1t) y1(kt)+1where1neocomposite of the transmission signal in the reception path.

The signal y1( k2k+1t) then output vicites 8 is fed to the input of the first adder 9. However, this compensation process does not end. According to the order of the organization addressing it reads signals from other memory cells, i.e., 10000001, 10000010.10001111. Because high-order bits of all the above addresses are the same, and the response of the communication channel to the data code combination will be approximately the same. Consequently, at the output of vicites signals will appear as

y1(kt)+2< / BR>
y1(kt) is series. This value will be assessed below.

As signal transmission station And the first memory block is gradually filled with the total signal station a and station B. Then output vicites 8 on the next Tmthe clock interval of the observed signal in the form of

ym(kt)-ym-1(kt);

ym(kt)-ym-2(kt).

ym(kt)-y(kt).

Because the device is designed to separate the two signals, the latter members listed above series have the same magnitude and sign or opposite sign. Consequently, at the output of vicites 8 will be either zero or double amplitude of the received signal. Due to the fact that in any digital signal, there is always a balance in the permanent component, the appearance of positive and negative levels are roughly the same. Therefore, approximately twice the output of vicites 8 will receive signals that are close to zero, and twice the amplitude of the received signal. In this third process ends.

The recovery process forms received signal and outputting it to the consumer of the messages is carried out using the first adder, the second memory block 10 and the output of the trigger 13. At time T1is output to the trigger 13. The first adder 9 and the second memory block 10 are essentially storing the adder. The output signal it is described by the following expression

Cj=[yj(kjt)-yi(kit)] (1)

After M clock cycles, the summation in nakaplivaya the adder is approximately equal

Cj=Myj(kjt)=2Nyjt), (2) where M 2N.

Since the received signal duplex, then the sign of Cjuniquely determines the sign of the received signal yj(kjt), which corresponds to the output of the trigger 13 to the output signal from the control unit 14. Thus was the transfer of digital linear signal, the compensation signal of the opposite direction and restore the received signal.

Appreciate the advantages of the proposed solution compared to the prototype.

As is known, the reception quality is measured by the signal-to-noise ratio at the receiver input. For the prototype this ratio will be equal to

D , (3) where RADC2/12 the noise power of the ADC;CC2the power of white noise. This expression is true for the proposed device. But for the latter due to the summation repeatedly summarized splitting noise of the ADC is part of the big 2Nthe noise power is equal to PADC2N.

Because the distribution of PADCand PCCsubject to the normal law, the total noise power is equal to 2 + effect linear summation of samples of the signal, the total power of the signal according to (2) is equal to M2Pwith. Then for the proposed device, the signal-to-noise ratio will be equal to the

Q . (4)

Gains in improving the noise immunity will be an amount equal to the

2N. (5)

So, when N 4 winning would be 16 times. The reliability of a positive effect was confirmed by experimental data, fully confirmed the justice of theoretical research.

1. A device FOR the SEPARATION directions of TRANSMISSION AND RECEPTION IN a DUPLEX COMMUNICATION SYSTEM comprising a generator, the first output of which is connected to the input of the input unit, the first input of the analog-to-digital Converter and the first inputs of the first and second memory blocks, the output of the analog-to-digital Converter connected to the first input of vicites and the second input of the first memory block, the output of which is connected to a second input of myCitadel, the output of which is connected to the first input of the first adder, the output of which is connected to a second who entered the block level conversion differential system, trigger, and connected in series control unit, the serial register, the second adder and the parallel register, and the output of the input unit is connected to a second input of the serial register and through the conversion unit level to the input of a differential system, the first output of which is connected to the communication line and the second output from the second analog-digital Converter, the second output of the generator is connected to the input of the control unit, the second output control unit connected to the second parallel input register, the output of which is connected to a second input of the second adder, the output of which is connected to the third input of the first memory block, the fourth input connected to a second output of the serial register, the third output control unit connected to the third input of the second memory block and the first input of the trigger, a second input connected to the output of the first adder.

2. The device under item 1, characterized in that the control unit contains consistently United counter and decoder, the same outputs are outputs of the control unit, the input of which is the entrance counter.

 

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