A device for decoding a convolutional code


H03M13/12 -

 

(57) Abstract:

The invention relates to data transmission systems for communication channels and can be used in devices for decoding by the Viterbi algorithm. The purpose of the invention is the extension of functionality by monitoring the quality of the communication channel in the operating modes of the device. In the device containing the switch, the n blocks of the addition - comparison-selection, (n + 2) buffer register, a multiplexer, a control unit, a display unit and a memory block solutions, introduced the unit of comparison, two of the counter, a decoder, a trigger, a buffer element and (n + 3) buffer register. 5 Il.

The invention relates to systems for the transmission of information via communication channels and can be used in devices for decoding by the Viterbi algorithm.

A device for decoding a convolutional code used in the decoding by the Viterbi algorithm. This device consists of a switch, the n blocks of the addition-comparison choice (CERs), n buffer registers, memory block solutions, (n+1) and (n+2) buffer registers, the display unit, a control unit and a multiplexer. The output switch is connected with the first inputs of the first (n)-th blocks CER (n=2 where the length of the code granatstein lattice diagram code outputs (211)-th and (21)-th buffer register (i=1, n/2) are connected respectively with the second and third inputs (21-1)-th and the (21)-th blocks of CERs, the second outputs of the first (n)-th blocks CERs are connected to respective inputs of the memory block solutions, the outputs of the first (n)-th buffer registers connected to information inputs of the multiplexer, the first information and the control inputs of the switch are respectively the information input and the input of the mode selection device, the output of the memory block solutions connected to the information input of the (n+2)-th buffer register and an output, the outputs of the multiplexer combined with the corresponding outputs of the (n+2)th buffer register and is connected to the information input display unit, (n+1)-th buffer register and the bidirectional data bus of the control unit, the first and second inputs of which are respectively input start and control device, the output (n+1)-th buffer register connected to the second information input of the switch, the address outputs of the control unit is connected to the address inputs of the multiplexer, the first, second, third, and fourth control outputs of the control unit connected to control inputs suitable operation of the main device for decoding a convolutional code is what is the Troubleshooting by automatically testing and fault location of its main components. Testing device for decoding a convolutional code is carried out according to the program stored in the micro-computer.

However, the main device does not allow to judge the quality of the communication channel.

The aim of the invention is to expand the functional capabilities of the device for decoding a convolutional code by ensuring quality control of the communication channel in the operating modes of the device.

This is achieved by the fact that in the known device for decoding a convolutional code is entered, the unit of comparison, two counters, a third decoder, the trigger, the buffer element, an additional (n+3) buffer register, and the outputs of the first (n)-th buffer register connected to the first inputs of the block comparison, the second input of which receives a threshold signal, to the counting input of the first counter receives signals clock frequency, the outputs of the first counter is connected to the input of the third decoder, the first output of which is connected to the R inputs of the first and second counters, the output of the Comparer is connected to the counting input of the second counter outputs catalogados trigger and the first control input (n + 3) buffer register, the second control input connected to the fifth output of the control unit and managing the input of the buffer element, the outputs of the (n+3) buffer register connected to the bidirectional data bus of the control unit, the R-input of the trigger is connected to the sixth output control unit, the trigger output is connected to the information input of the buffer element, the output of which is connected to the bidirectional data bus of the control unit.

In Fig.1 shows a block diagram of the device of Fig.2 is a functional block diagram of the addition comparison selection CERs; Fig.3 block diagram of the memory block solutions; Fig.4 block diagram of the programme of work of the device for diagnosing a communication channel; Fig. 5 block diagram of the programme of work of the device in the test mode.

A device for decoding a convolutional code (Fig.1) consists of a switch 1, n blocks CER 21-2nbuffer registers 31-3nblock 4 memory solutions, buffer registers 5, 6, display unit 7, a control unit 8, a multiplexer 9, Comparer 10, a counter 11, a decoder 12, a counter 13, a trigger 14, the buffer register 15, the buffer element 16. The output of switch 1 is connected with the first inputs of the blocks 21-2nCER, the first outputs are connected to escrow 32i-1and 32i(i 1, n/2) are connected respectively with the second and third inputs of the blocks 22i-1and 22iCERs, the second outputs of blocks 21-2nCERs are connected respectively to the inputs of the block 4 memory solutions. The outputs of the buffer register 31-3nconnected respectively with the information inputs of the multiplexer 9. The first data input and the control input of switch 1 are, respectively, the information input and the input of the mode selection device, the output unit 4 memory solutions connected to the information input of the buffer register 6 and an output, the outputs of the multiplexer 9 is combined with the corresponding outputs of the buffer register 6 and is connected to the information input display unit 7, the buffer register 5 and the bidirectional data bus of the control unit 8. The first, the second inputs of the control unit 8 are respectively input start and control device, the output buffer register 5 is connected to a second information input of the switch 1, the address outputs of the control unit 8 is connected to the address inputs of the multiplexer 9, the first, second, third, and fourth control outputs of the control unit 8 is connected to control inputs of the indication unit 7, the buffer is n connected with the first input unit 10 comparison, the second input of which receives a threshold signal, to the counting input of the counter 11 receives signals clock frequency, the outputs of the counter 11 are connected with the inputs of the decoder 12, the first output of which is connected to the R-inputs of the counters 11 and 13, the output of the Comparer 10 is connected to the counting input of the counter 13, the outputs of which are connected to information inputs of the buffer register 15, the second output of the decoder 12 is connected to the S-input of the trigger 14 and the first control input of the buffer register 15, the second control input of which is connected to the fifth output control unit 8 and the managing input buffer element 16, the outputs of the buffer register 15 is connected to the bidirectional data bus of the control unit 8, R-input of the trigger 14 is connected to the sixth output control unit 8, the output of the trigger 14 is connected to the information input of the buffer element 16, the output of which is connected to the bidirectional data bus of the control unit 8.

The control unit 8 (Fig.1) consists of decoders 17, 18, the memory element 19, the driver control signals 20. The input of the start of the driver control signals 20 is first input of the control unit 8, the information terminals of the driver control the control unit 8, the output of the memory element 19 is connected to one of the bits of the bidirectional data bus. The address outputs of the driver control signals 20 are connected to the inputs of the decoders 17, 18 and are address outputs of the block, the first and second outputs of the decoder 17 are the same control outputs of the control unit 8. First, second, third, and fourth outputs of the decoder 18 are respectively the third, fourth, fifth and sixth control outputs of the control unit 8, the fifth output of the decoder 18 is connected with the control input of the memory element 19. As a shaper control signals can be used micro-computer based on any microprocessor kit, except for the Central processor, it must include a program memory and data memory.

Unit 2 CER (Fig. 2) consists of a comparison element 21, a switch 22, adders 23, 24. The first inputs of the adders 23, 24 are combined and the first input unit 2 CER, the second inputs of the adders 23, 24 are respectively the second and third inputs of block 2 of CERs, the outputs of the adders 23 and 24 are connected to the inputs of the comparison element 21 and the information inputs of the switch 22, the output of which is the first exit block 2 CER, the output of the comparison element 21 is HOLY is as follows.

Unit 2 CER on each step produces and delivers on their first new value of the metric condition for the corresponding node of the trellis diagram, and generates information about the received code sequence supplied to the second output in accordance with the Viterbi algorithm. To calculate the new value of the metric condition at the output of switch 22, i.e., the first output unit 2 CER use the old values of the state metrics for the two nodes of the trellis diagram supplied with the second and third inputs of block 2 of CERs on the second inputs of the adders 23, 24, to the first inputs of which at this stage do the values of the metrics of the branches from the first input unit 2 CER. The output of the switch 22 passes the minimum of the metric values at the outputs of the adders 23, 24 control switch 22 is a signal of a comparison result from the output of the comparison element 21. The signal of the comparing metrics of the States from the output of the comparison element 21 corresponds to the information about the adopted code and is supplied to the second output unit 2 CER.

Unit 4 memory solutions (Fig.3) consists of n triggers 25125nn elements AND 261-26nn elements PROHIBITION 271-27nn elements 281-2 the eye, the output of each register is connected to the first input of the element AND 261-26nand prohibiting the entrance of the element of the BAN 271-27nthe output of each trigger 251-25nconnected to the second input of the same name element I1-26nand allows the input of the element of the BAN 271-27nthe outputs of all elements AND 261-26nand BAN 271-27nconnected to inputs of elements OR 271-28nin accordance with the trellis diagram of the code, the outputs of the elements 281-28nconnected to inputs of the same name triggers 251-25nthe outputs of the elements 282i(i=1, n/2) are connected with the inputs of the OR element 29, the output of which is the output of the block.

Work unit 4 memory solutions is the following.

Signals corresponding to the information about the accepted code for each node of the trellis diagram and arriving at the inputs of shift registers 301-30nfirst written in them by simultaneous shift to the right (see Fig.3), and then read by a simultaneous shift to the left. This operation is implemented tracing, widely used in the memory blocks of the decoder algorithm is set to be "1". (Scheme, performing pre-installation trigger 251-25n, Fig.3 not shown). On each step of reading information from the registers 301-30nstatus changes trigger 251-25nwhen this is set to "1" in one of the triggers 251-25nthat corresponds to a node located on the true path of the process trellis diagram of the code. Setting a corresponding trigger 251-25nis the signal "1" from the output of the corresponding element OR 281-28n. This signal "1" depending on the information from the registers 301-30ncomes from the output of any element AND 261-26nor output of any element PROHIBITION 271-27non the second input of which is supplied allowing the potential of the trigger 251-25nset to "1" in the previous step. At the same time in each step is the delivery of information through the element OR 29 to the output unit 4 memory solutions. Unit information comes from the outputs of the elements 282i(i=1, n/2), are connected with inputs of the OR element 29. If this clock signal "1" at the output of any of the elements OR 282i-1not connected with the input element of the convolutional code is as follows.

There are two modes of operation of the device: work and testing.

In the operating mode (see Fig.1) the signal metrics of the branches coming from the information input device through the switch 1 is controlled by the input signal mode, the first input blocks 21-2nCERs. Blocks 21-2nCERs carry out the calculation of the new state metrics and information sequences for each node of the trellis diagram. Buffer registers 31-3nstore the metrics of the States of each node. In unit 4 memory solutions is storage of information sequences for each node, allocation and output on the output device, the decoded information sequence.

In the operating mode simultaneously with the operation of the device and control the quality of the communication channel.

The control is carried out according to the program shown in Fig.4. The beginning of the run control is received at a first input of the control unit 8 of the start signal calling address of the driver control signals 20 to the beginning of the control program.

The first operation (block a in Fig.4) is reset counters 11, 13, trigger 14 and a software schetchik registers 31-3non the second inputs of the block comparison 10 receives the threshold signal. If any of the metrics of States is greater than the threshold signal, which is an elementary evaluation of the deterioration of the quality of the communication channel, the output of the Comparer 10 a signal quality estimation of the communication channel. The counter 13 counts the number of signals to evaluate the quality of the communication channel for a certain number of cycles of operation of the device for decoding a convolutional code. The number of cycles determines the counter 11.

When filling of the counter 11 at the second output of the decoder 12 of a signal, which sets the trigger 14 in line "1" and writes information of the counter 13 in the buffer register 15. Then the signal from the first output of the decoder 12 clears the counters 11 and 13. Setting the trigger 14 in the state of "1" indicates the accumulation of information in the buffer register 15. The output signal of the trigger 14 act on the information input of the buffer element 16. The signals from the fifth output control unit 8 continuously poll the status of the buffer element 16. When the detection code "1" at the output of the buffer element 16 information from the output buffer register 15 is introduced through a bidirectional data bus in the driver control signals 20. Nanogrammes loop counter.

In the driver control signals 20 is addition accepted in the buffer register 15 information with information accumulated during previous cycles, and increment a software counter cycle. The output signal VI of the control unit 8 resets the trigger 14. Then check the end of the cycle analysis software loop counter. If the cycle is not finished, it is the repetition of blocks b, C, d, e Fig.4.

The number of iterations in the loop is chosen sufficient for averaging the results. The resulting sum is compared with a certain threshold. The threshold value is selected from the acceptable quality of the communication channel for the device to decode the convolutional code. If the value of the amount received exceeds the threshold value, the display unit 7 displays the message to the poor quality of the communication channel (blocks g, h, Fig.4).

Message to the poor quality of the communication channel is converted to the code necessary for the display unit 7 corresponding subroutine (block And Fig.4). The generated code is displayed on the data bus control unit 8 and stored in the display unit 7 by the signal from the first control output of the control unit 8 (unit 3, Fig.4).

The work of the who and the first input of the control unit 8 of the trigger signal, the calling address of the driver control signals 20 to the beginning of the test program.

The first operation is the formation of a test array of metrics branches (block a in Fig. 5), which is formed by encoding and subsequent transformations of information symbols corresponding pseudo-random sequence. The length of the pseudorandom sequence must be equal to the number of lattice edges of the graph minus one. This test sequence metrics of the branches provides a full scan of the device for decoding a convolutional code.

The test device is made in two stages:

1. Testing block 21-2nCERS;

2. The testing unit 4 memory solutions.

Testing blocks 21-2nCER is in the cycle, number of cycles which is equal to the length of the test array metrics of the branches, consisting of the blocks a-d (see Fig.5).

On each step of the cycle are the following:

the branch metric output on the data bus control unit 8, is written into the buffer register 5 pulse with the second control output of the control unit 8. Output buffer register 5 metric branch of Poo metric set of States, recorded in the buffer register 31-3n(block b, Fig.5);

all the metrics of the States through the multiplexer 9 controlled by signals on the address outputs of the control unit 8 and is connected to the data bus signal from the third control output of the control unit 8, is entered into the control unit 8, the driver control signals 20 calculates a checksum of the state metrics (block b, Fig.5);

the calculated checksum is compared with the reference (block g, Fig.5) stored in the permanent memory of the driver control signals 20. In case of equality checks the end of the cycle and the transition or in the beginning of the cycle or to the next stage of the testing unit 4 memory solutions.

If nesravnennye transition to operations error handling (blocks e, f, C, Fig.5), where the first stage is output to the display rooms of tact, which fixed the problem. The status of the software of the tick count is converted into a code that is required for the display unit 7 corresponding subroutine (block t, Fig.5). The generated code is displayed on the data bus control unit 8 and stored in the display unit 7 by the pulse from the first (1) control output control unit 8 (section e, Fig. 5 the rum after visual observation of the display (block W, Fig.5). To do this, the program checks the presence of the control signal at the input of the memory element 19 connected to the data bus of the control unit 8 pulse from the third output of the decoder 18. This process is repeated until the supply of the control signal to the input of the memory element 19, and then moves to the next operation (block C, Fig. 5). This activity is consistent display all metrics of States at a given quantum state of each buffer register 31-3nthrough the multiplexer 9, controlled by the address signals of the outputs of the control unit 8 and is connected to the data bus signal from the third (III) control output control unit 8, is fed to the data bus of the control unit 8, and then converted into a code indicating the subroutine display (block t, Fig. 5) and is displayed in the display unit 7. The induced metric of the States analyzed by visual comparison with known values of the metrics of the States. A mismatch indicates a fault or test register 31-3nor corresponding block 21-2nDIS.

Stage test unit 4 memory solutions begins with the feeding of the metrics of the branches of the SFD is the main part of the testing phase unit 4 memory solutions are in the cycle, includes blocks K, l, m Fig.5. In each step of the cycle are the following:

flow metrics of the branches to fill the buffer register 6 new information, enter this state buffer register 6 shaper control signals 20 of the control unit 8 is carried out by connecting the register to the data bus under the action signal from the fourth (IV) control output control unit 8 (unit, Fig.5);

comparison of this information with the reference information (block l, Fig.5). In the case of a tie, the next beat cycle or loop exit when it is finished (block m, Fig.5). At the end of the cycle is indicated right end (block n, Fig.5), while the display unit is output from the control unit 8 what specific message, the code of which is stored in the program itself. When nesravnennye status buffer register 6 with the standard operations error handling (blocks, o, p, s, Fig. 5).

First (block o, Fig.5) shows the number of the quantum in the loop test unit 4 memory solutions similar to those described above for the testing phase blocks 21-2nCERs. Then after the operation standby signal to the input UPRAVLENIJA register 6. For this purpose, the output buffer register 6 is connected to the data bus of the control unit 8 by the signal from the fourth (IV) output control unit 8, its status is entered in the driver control signals 20 of the control unit 8 where it is converted to the code necessary for the display unit 7 by the subroutine display (block t, Fig.4), and is displayed in the display unit 7 as described previously. Visual comparison of the content of the buffer register 6 with the known reference information allows to determine the location of a fault within the unit 4 memory solutions.

The use of the invention allows to estimate the quality of a communication channel or to reveal its failure to take prompt action to restore the quality of the communication channel by holding the transceiver settings or demobilise equipment.

A DEVICE FOR DECODING a CONVOLUTIONAL CODE containing the switch, the output of which is connected with the first inputs of the first through n-th blocks of the addition-comparison-selection, where n = 2- length code constraint convolutional code, the first outputs of the blocks of the addition-comparison-election connected to inputs of first to n-th buffer registers in accordance with the diagram of the convolutional code, the neck 2i-th blocks of the addition-comparison-selection and relevant information inputs of the multiplexer, the outputs of which are combined with the corresponding outputs of the (n + 1)-th buffer register and connected to the corresponding information input display unit, (n + 2)-th buffer register and the bidirectional data bus of the control unit, outputs first to fourth which is connected to the control inputs, respectively, of the display unit, (n + 2)-th buffer register, a multiplexer and (n + 1)-th buffer register, the information inputs which are output bus and connected to respective outputs of the memory block solutions the inputs of which are connected to the second outputs of the respective blocks of the addition-comparison-selection, with the address inputs of the multiplexer is connected to the address bus of the control unit, the first and second inputs of which are respectively tire "start" and "Control" and bus "Mode" and input bus are respectively the Governor and the first information input switch, the second information input of which is connected to respective outputs of the (n + 2)-th buffer register, characterized in that it introduced two counter, a decoder, a trigger, a buffer element, (n + 3)th buffer register and the unit of comparison, the first inputs of which are connected to outputs of the first through n-th the pout counter, the input set to "0" which is the same input of the second counter connected to the first output of the decoder, the input of which is connected to respective outputs of the second counter, the clock input of which is the bus clock pulses, and the second output of the decoder is connected to the S input of the trigger and the first control input (n + 3)-th buffer register, the information input of which is connected to respective outputs of the first counter, the second control input is combined with the control input of the buffer element and is connected to the fifth output control unit that outputs an (n + 3)th buffer register and the output buffer element is connected to the bidirectional data bus of the control unit, the input buffer element is connected to the trigger output, R is the input connected to the sixth output of the control unit.

 

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