Encoder

 

(57) Abstract:

The invention relates to computing. Its use in the remote input, working under the influence of electromagnetic interference and electrostatic discharge, allows improved data encryption through the restoration of the distorted character of the output code. This is achieved through the introduction of additional encoder elements analog memory and error correction block output code, as well as the transformer of the Converter unit code adjustment code in the form of a transformer of the Converter unit code in the Hamming code. 2 C.p. f-crystals, 1 tab., 10 Il.

The invention relates to computing and can be used in devices for remote input information in digital devices operating under the influence of electromagnetic interference and electrostatic discharge.

The purpose of the invention to increase the reliability of encryption due to restoration of the distorted character of the output code.

In Fig. 1 is a diagram of an encoder with fifteen keys (K 4), and Fig. 2.10 shows the scheme of its functional elements.

Keys 1.15 in the Converter 16 is entered decimal number that coincides with the sequence numbers of the keys. Binary codes of these numbers is generated in the transducer 16 with transformers 99.105 in accordance with the requirements of the Hamming code of length seven and four information bits shown in the table.

As the table shows, four to the left of the symbol (X1, X2, X3, X4) cameratracker binary key codes are four-digit binary codes (8421) decimal numbers entered by the keys 1.15. The remaining three characters (X5, X6, X7) these key codes 1.15 chosen in accordance with the requirements of the Hamming code of the following ratios:

X5 Hrumych in the Converter 16 in accordance with the requirements of the code of Hamming, the following test ratios (amounts):

S1 X4 + X5 + X6 + X7;

S2 X2 + X3 + X6 + X7;

S3 X1 + X3 + X5 + X7. (2)

When all of the sum (modulo two) is equal to zero, the output unit 26 signals are absent, and this means that in the code there is no error. If any of these amounts not equal to zero, i.e., equal to one, it means that in the analyzed code has a bug. The number of the output unit 26, where there is an output signal that indicates the discharge of the output code of the encoder, where there is an error.

Does the encoder as follows.

In the initial state, the keys 1.15 open, the driver 24 generates at its first output a sequence of pulses of negative polarity at the second output of positive polarity with a lower repetition rate. Pulses from the first output of this driver via resistors 106.112 (Fig. 2), the output winding of the transformer 99.105 Converter 16 "polled" status keys 1.15. The magnetic cores of transformers 99.105 open when the keys are saturated, the outputs of the differentiating circuit formed by series-connected resistors 106.112 and output windings of the respective transformers 99.105, formed ratnoo is generated on the cut of pulses, coming from the first output of the specified driver, through diodes 113.119 pass on items 17.23 memory capacitors which are charged to the level of logical "1". This level is supplied to the information input unit 25, memorized D-triggers 126.132 (Fig. 5) last and confirmed by every subsequent pulse on its clock input 76. At the outputs of this block is supported by a logic level "0" which is supplied to the inputs of the block 26 and the second input channel block 27. The outputs of the block 26 is stored a logic level "0". At the first inputs of all channels of the unit 27 is supported by a logic level "0", so it outputs 91.94 a logic level "0". The driver 29 is supported in the initial state, the logical level "0" from the output of the detector 28 of the code word, and its output level logic "0". On the output unit 30 switches also maintains the logical level "0". These original state of the functional blocks of the encoder are saved to the circuit of any of the keys 1.15.

Consider the operation of the encoder in the absence of any failures of elements.

With the closure of any of the keys 1.15 short-circuit occurs consistently vklyuchennoi table. For example, with the closure of the key 3 zamorachivatsja input winding 102-3, 99-1 and 103-2 transformers 102, 99 and 103 with weighting factors 8.1 and 16, respectively. The input resistance output windings 102-4, 99-3 and 103-4 appropriate transformer for pulse shaper 24 is sharply reduced, and all of the voltage pulses of the specified driver almost falls on the resistors 109, 106 and 110 of the respective differentiating circuits, the outputs of the latter disappear pulses generated at the front and the slice pulse shaper 24. Therefore, after closure of the key 3 stops the supply of pulses of positive polarity to the inputs of the elements 20, 17 and 21 of the memory, and the inputs of the elements 18, 19, 22 and 23 and they keep coming. As a result, the outputs of the elements 20, 17 and 21 of the memory is set to a potential signal of logical level "0" and the outputs of the elements 18, 19, 22 and 23 is maintained the initial level of logical "1". At the outputs 78, 81 and 82 of the block 25 is set to the logical level "1", and outputs 79, 80, 83 and 84 saves the original logical level "0", i.e., at the outputs of the block 25 and the code will 0011001 (high-order bits of code to the left).

This combination of signals fed to the inputs of the block 26, and the second input of kanagala at the inputs of the block 26 on its outputs saves the original state of the logical "0", because the combination satisfies the following table, and the sum of S1, S2 and S3 in relations (2) equal to zero. In the presence of logical level "0" to one input each of the channel unit 27 to the output of each of its channels (Fig. 8) given the level of signal present at the other input channel. Therefore, in our case, when closed, the key 3, the outputs of block 27 is issued code 0011, i.e., binary code decimal number 3 (non closed key 3), and remains at all times the closed state of the key.

At the same time (after closure of the key 3) the emergence of logical level "1" on any one of the output unit 27 causes the level of logical "1" at the output of the detector 28 of the code word that starts shaper 29. With the delay, the more time the potential difference of the signals at the outputs of block 25, the imaging unit 29 generates a single pulse signal, which is supplied to the control input 90 unit 30 switches. During this pulse outputs 95.98 encoder a code (in our case, 0011), which is present at its inputs.

When opened, closed key 3 described above, the initial state of the encoder is automatically restored: input resistance output is again receive the pulses of positive polarity, outputs 78, 81 and 82 of the block 25 is restored to the original level of logical "0", the output of the detector 28 of the code word is also a logic level "0", blocking the launch of the shaper 29.

With the closure of any other keys 1.15 encoder in the absence of failures of elements, i.e., when the outputs of the block 25 codes correspond to the following table, works in a similar manner, the outputs 95.98 encoder given binary codes for decimal numbers entered by the keys 1.15.

Consider now the operation of the encoder in the presence of failure of its functional elements, leading to distortion of one bit (the so-called "single failure" code lockable key generated in accordance with the above table, the outputs of the block 25 in the example circuit of the same key 3.

Suppose that the encoder is a failure (or failures), distorting the seventh (X1, see table) discharge (which is formed by the transformer 105) binary code key (for example, open circuit output winding 105-5 transformer 105, the cliffs of the findings of the resistor 112 or diode 119, violation ration of these elements, the failure of D-flip-flop 132 unit 25, and so on). Then with the closure of the key 3 on the outputs of the block 25 instead of binary code 0011001 (see table) has m vetelino, on the input unit 26 that performs the summation of terms modulo two in accordance with the relations (2), components (X1.X7) have the following meanings: X1 1, X2 0, X3, 1, X4, 1 X5 0, X6, 0, X7 1. With these values of the components of X1.X7 sum S3 at the output of element 143 (Fig. 7) equal to one, the sum of S1 and S2 respectively from the outputs of the elements 141 and 142 is equal to zero. Therefore, the inputs of the decoder 144 is binary code 001 number 1, therefore, the output signal (logic level "1" appears at the output 85 of the block 26 and is supplied to the first input of the first channel unit 27. The second input of the first channel unit 27 is connected to the output 84 of the block 25, where because of a failure there is a logical "1" instead of the logical "0". Using the combination of the input signals at the output of the channel unit 27 will be a logical "0" (Fig. 8), i.e., corrected the distorted character of category code at the output of block 25. Since the second input channel block 27 is connected to the four outputs 81.84 high-order bits of the block 25, the outputs of block 27 is code 0011, i.e., binary code numbers 3, coincides with the number of closed key 3. This code is supplied to the information input unit 30 switches on the control input 90 whose output driver 29 receives a pulse signal that is delayed relative to the time of povleyal at the output of the detector 28 of the code word. As a result, the outputs 95.98 encoder pulse is issued fixed binary code 0011 closed key 3.

Consider now the operation of the encoder in case of failures, resulting in the issuance in one of the bits of the binary code of a closed 3 key outputs of the block 25 instead of the logical "1" logical "0". This situation can be, for example, in cases where any D-trigger unit 25 does not switch when it is necessary, in the zero state (the initial state of the D-flip-flops 126.132 unit 25 unit).

Suppose that with the closure of the key 3 because of the refusal does not switch D-flip-flop 126 of the block 25 (Fig. 5) in the circuit of the first digit of the binary code of the key. Then from the outputs of the block 25 instead of the code 0011001 present code 0011000. Therefore, the components of (X1.X7) on the input unit 26 have the following meanings: X1 X2 0, X3 X4 1, X5X6 X7 0. With these values of the components of the sum modulo two of S1, S2 and S3 on the outputs respectively of the elements 141, 142 and 143 unit 26 (Fig. 7) all equal to one, i.e., to the inputs of the decoder 144 of the block attached binary code 111 number 7. Therefore, the output signal is the output of "7" decoder 144 and passes to the output unit 26. This means that in the event of a failure in the encoder correction of any character output caterers is because in the four high-order bits of the seven-bit code output unit 25, from which is removed through the blocks 27 and 30 is output on encoder four-digit binary code of the closed key, the error did not occur: there, in spite of this refusal, was code 0011, i.e., closed code key 3, which is output on 95.98 encoder.

With the closure of other keys in case of failures in the encoder, resulting in distortion of the single character code from the outputs of the block 25 (conversion of logical "1" logical "0" or Vice versa), the encoder works in a similar way.

Thus, when the closure of any of the keys 1.15 at the outputs of block 25 of the encoder appears within the closed state of the key) seven-bit binary code in accordance with the above table. Four senior level this code are for information only, i.e., contain information about serial numbers lockable keys, and three Junior level (taken from transformers 99.101 Converter 16) are testing. Information about the number of closed key is output on 95.98 encoder short-term (during the pulse shaper 29) at the end of transients in the circuit of the keys. If the encoder has a failure, leading to distortion of one character (single failure) key codes in bits, the ol is restored.

1. ENCODER containing the 2K1 key (K the number of characters output code), the first and second findings of the i-th key connected respectively with (2i 1)-th and 2i-th information input transformer of the Converter unit code adjustment code, the first (K + 1) th outputs of which respectively through the first (K + 1)-th analog memory elements connected to respective information inputs of the block RAM, the first (K + 1) th outputs of which are connected to the simultaneous inputs of a block of code analysis, shaper pulse reading the first output of which is connected to the clock input transformer of the Converter unit code correcting code, the second output of the pulse shaper reader is connected to the clock inputs of the block RAM and a single pulse shaper, the output of which is connected to the control unit switches the information inputs of which are respectively combined with the input code word detector, the output of which is connected with the control input of the shaper of a single pulse, the outputs of block switches are outputs of the encoder, characterized in that, to improve the accuracy of the encoding at the expense of no the lo symbol correcting Hamming code) and the error correction block output code, and transformer Converter unit code adjustment code is executed in the form of a transformer of the Converter unit code code Hamming (K + 2)-th n-th outputs of which respectively through (K + 2)-th n-th analog memory elements are connected with the same information inputs of the block RAM, the first K-th inputs of the correction block output code is connected to the simultaneous outputs of the block RAM, (K + 2)-th n-th outputs of which are connected to the same unit code analysis, the first is the K-th outputs of which are connected to the (K + 1)-th 2K-th inputs of the correction block output code, the first K-th outputs of which are connected with the same information input unit switches.

2. The encoder under item 1, characterized in that the transformer inverter unit code Hamming code contains n transformers n resistors and n + 1 diodes, K (2i 1)-th and 2i-th information inputs of the Converter are connected in series and in accordance with relevant United the primary winding of the transformer, with numbers corresponding to the individual bits in the i-th line of code tables used Hamming code, the beginning of the secondary winding of each transformer is connected with the first you and are a clock input of the Converter, the ends of the secondary windings of all transformers and the second output (n + 1)-th diode is connected to the shared bus, the second set of conclusions n diodes are the corresponding outputs of the Converter.

3. The encoder under item 1, characterized in that the block of code analysis contains the decoder and K 1 adders modulo two inputs of the j-th modulo two is connected to the inputs of the unit in accordance with the j-th row of the check matrix used Hamming code, outputs K 1 adders modulo two are connected to the corresponding inputs of the decoder, the outputs of which are the respective outputs of the block.

 

Same patents:

The invention relates to the field of conversion codes and can be used in information processing systems multi-channel datalogger

The invention relates to computing and data transmission and can be used to control structural codes

The invention relates to computing and communications

The invention relates to a device for the transmission of discrete data and can be used in systems of automatic locomotive alarm, Autolock and other devices of railway automatics

The invention relates to a device for the encoding of discrete messages and can be used in FSO communication systems

The invention relates to computing and communication technology and can be used in digital communication systems using convolutional codes

The invention relates to a remote control and pulse technique and can be used in the transmission and processing of discrete information for error correction in communication channels

The invention relates to telecommunications and is intended for use in digital transmission systems convolutional code

The invention relates to computer technology and can be used in communication systems and information processing, operating with modular codes

The invention relates to computing and communication technology in the information transmission codes JUICE and can be used in computing devices operating in JUICE

The invention relates to telecommunication and can be used in communication systems

FIELD: Witterby algorithm applications.

SUBSTANCE: system has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.

EFFECT: higher efficiency.

2 cl, 9 dwg

FIELD: communications engineering.

SUBSTANCE: proposed device and method for mobile code-division multiple access communication system including device for transferring channel of backward-link transmission speed indicator afford generation of optimal code words ensuring optimal coding for all types of coding procedures from optimal type (24.1) up to optimal coding procedure 24.7 and supporting all optimal-coding devices.

EFFECT: optimized capacity.

74 cl, 21 dwg, 44 tbl

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communication systems.

SUBSTANCE: method includes generating sets of sub-codes of quasi-additional turbo-codes with given encoding speeds, and given sub-codes are reorganized as a set of sub-codes with another encoding speed for use in next transfer of sub-code with given encoding speed.

EFFECT: higher efficiency.

9 cl, 13 dwg

FIELD: data transfer technologies.

SUBSTANCE: method includes segmentation of length N of quasi-complementary turbo-codes on preset amount of sections, determining identifiers of sub-code packets appropriate for segmented portions, setting of said packets separated for initial transfer of sub-code, calculation of number of remaining symbols in form N-Fs, where N - length of quasi-complementary turbo-codes, and Fs - position of start symbol of sub-code of quasi-complementary turbo-codes, determining position of symbol of remaining symbols in amount equal to sub-codes amount, which have to be sent and serial transfer of sub-code symbols from position of starting symbol Fs to position of last symbol Ls.

EFFECT: higher efficiency.

5 cl, 17 dwg

FIELD: communications engineering.

SUBSTANCE: method includes selecting one combination among given combinations, appropriate for several or every generated symbols of code word to transmit generated symbols of code word with length of sub-packet, determined in accordance to data transfer speed, information, appropriate for data transfer speed, is read, also based on length of sub-packet and chosen combination, from a table, wherein identification information, pointing at data transfer speed, sub-packet length and selected combination, is, is previously displayed for given information, and generated code word symbols are transmitted in accordance to read information and in accordance to selected combination.

EFFECT: possible check transmission of information by means of hybrid automatic repeat query for increasing carrying capacity during high-speed information transfer.

4 cl, 16 dwg, 6 tbl

FIELD: communications engineering; simulating digital communication channels with separate and grouping errors.

SUBSTANCE: proposed method includes evaluation of set of communication channel states S0,S1, ..., Sm - 1 and calculation of conditional error probabilities P(e/s) in each state s" i = 0, ..., m - 1 of communication channel, and error acquisition in communication channel in compliance with conditional error probability for current state of communication channel; in the process probability of error-free interval p(0i) of i bits is found, and conditional probabilities p(0i1/11), p(0i1/01) of error-free intervals of i bits are calculated with respect to them basing on probabilities p(0i) and using recurrent rules during each current time interval and preceding one on condition that for error generation use is made of two states of communication channel corresponding to combination of errors 11 or 01; random number p uniformly distributed within interval between 0 and 1 is generated; conditional probabilities p(0i1/11), p(0i1/01) are summed up starting from i = 0 resulting in sequence 0k1 that constitutes bit-by-bit stream of communication channel errors.

EFFECT: enhanced speed.

1 cl, 1 tbl

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: coding in communication systems.

SUBSTANCE: proposed partial reverse bit-order interleaver (P-RBO) functions to sequentially column-by-column configure input data stream of size N in matrix that has 2m lines and (J - 1) columns, as well as R lines in J column, to interleave configured data, and to read out interleaved data from lines.

EFFECT: optimized interleaving parameters complying with interleaver size.

4 cl, 7 dwg, 3 tbl

Up!