The device decodes the dtmf signals

 

(57) Abstract:

Usage: electronics. The inventive device includes a filter 1, a comparator 2, the register 30, the delay element 7, four counter 5, 9, 16, 18, two elements And 3, 8, two OR element 11, 15, Comparer 14, the dispenser 22, subtractive unit 13. To improve noise immunity in the device entered the block elements And the five elements OR 17, 19, 21, 26, 31, two elements And 4, 25, unit 23 element OR key block 27, block 29 elements OR block 10 initial setup, unit 6, dividing frequencies, two delay elements 20, 24. 1 Il.

The invention relates to radio engineering.

The aim is to increase noise immunity.

The drawing shows a block electrical diagram of the proposed device.

The device comprises a filter 1, a comparator 2, the first element And 3, the third element And 4, the first counter 5, the block division frequency 6, the first delay element 7, the second element And 8, the second counter 9, block 10 initial setup, the first element OR 11, block 12 elements And subtractive block 13, block 14 comparison, the second element OR 15, the third counter 16, the third element OR 17, the fourth counter 18, the fourth element OR 19, the second delay element 20, prestoy element OR 26, key block 27, a persistent storage device (ROM) 28, block 29 elements OR, the register 30, the seventh element OR 31.

The device operates as follows.

By pressing one of the L buttons (L is the number of signals used in the communication system) selects the signal used in the communication system at the moment. Buttons are rigidly connected to the inputs of the address selection EP appropriate zones ROM 28. In each zone the ROM 28 is written in binary code structure code sequence of one of the signals. After pressing one of the L button opens the corresponding key and information one of the areas of the ROM 28 is transferred to the register 30. Simultaneously, the signal from the key through the element OR 31 is supplied to the clock input of register 30. Because the case is parallel to D-triggers when the signal at its clock input is the simultaneous entry into all cells of the register code number stored in a particular area of the ROM 28. Thus this device is tuned to a specific signal. Assume that the device works with trichostatin signal (M=3). Press L button from the ROM 28 in the register 30 has recorded the code structure of the signal 3,1,2. The device is configured for operation with a signal of the source clock frequency, which generates pulses with a frequency of 2M (M is the highest frequency in the structure of the signal). Device synchronization sinteziruet the source clock frequency with the receipt of the signal. When you turn on the terminal And receive a signal through the differential element and the elements OR 11, 17, 19 lists all the counters and the distributor 22 levels in the initial state, namely the momentum of the initial installation is fed to the inputs S, R counters 5, 9 through the element OR 11, the inputs S, R of the counters 16, 18 through the OR element 17 and to the input of the distributor 22 through the element OR 19. This means that when receiving a pulse counting input of the counter will count the number of them in the order received, for example 1,2... etc., No other permissions counters do not need. Same for the distributor 22 levels. Upon receipt of the first pulse on the clock input From the distributor level 22 distributes it in the first channel (first), second in the second channel (the second exit) and so on, No other permissions of the distributor 22 is not necessary. Moreover, the signal on the specific output of the distributor 22 operates continuously as long until the next pulse at its input.

Combine the realities 22. The time delay element 20 is t3= To/2. This first clock pulse supplied to the first output of the distributor level 22, which is connected to the second inputs of elements And unit 23, the input of which is connected to the first cell of the register 30. Thus information from the first cell of the register 30 through the block 23 elements AND / OR receives on a second input unit of frequency division 6, in particular to the input of the decoder unit 6, the signal at the output of which is on one of the M outputs, depending on the binary combinations received from a cell of the register 30. Therefore, the second input element And 3 will be received pulses with a frequency two times less than the clock. In addition, information from the first cell of the register 30 through the block elements AND / OR 23 and a delay element 24 (delay time tC= T/2) is supplied to the entrance of the subtractive unit 13.

Input passed wideband analog filter 1, is supplied to the comparator 2. The signal at the output of the comparator will be in if arriving at its input signal has exceeded some pre-determined level. For example, this level is equal to zero. Then in the moments corresponding to the positive half-waves of the incoming signals at the output of the comp the Torah input element And 3, will be supplied to an inverse input element And 4 and to the input of the delay element 7. As to the second input element And 3 will be received pulses are thinned clock frequency, the output element And 3 will receive signals corresponding to only the positive half-waves of the useful signal. The time delay element 7 is set to a single text. After a delay element 7 signal through the element And 8 is supplied to the second input element And 4. Output element And 4, the signal will be when the presence of a signal from the element And 8 and no signal on the inverse of the input. Thus at the input of the counter 5 will be received pulses, fixing the transition from the positive half wave of each frequency to the negative. Simultaneously, the counter 9 counts the number of clock pulses. When counting the number of pulses is equal to 2M counter 9 outputs a signal to read through the item And 12 in binary code the number counted during this time, the counter 5 counts (which corresponds to the nominal frequency structure of the signal). This number in binary code is supplied to the subtractive input unit 13. Simultaneously, the signal from the counter 9 is supplied to the subtractive input unit 13 and the input unit of comparison 14. In addition, the same signal through the element OR 11 results in and is our input unit 14, zero (a consequence of the denomination of the accepted frequency and recorded in the cell case 30), in the presence of the signal at the input of this device appears in the output signal, which is registered by the counters 16 and 18. If the difference is not zero, the fact that comparison is only registered by the counter 16. The comparison is not constant, and only the control signal from the counter 9.

Therefore, when the counting by the counter 9 2M clock pulses at the outputs of block 14 receive pulses which are counted by the counters 16 and 18. In addition, the output signal of the counter 9 through the element 21 is supplied to the clock input of the distributor level 22, which distributes it to the second output. This output is connected to second inputs of elements And unit 23, the input of which is connected to a second cell of the register. Thus information from the second cell of the register through the block elements AND / OR 23 is supplied to the second input of the frequency division 6, to the input of the decoder. Therefore, the second input element And 3 will be received pulses with a frequency of 6 times lower than the clock, and over the duration of a frequency f1to the second input element And 3 will go just 1 pulse, which will be recorded by the counter 5. In addition Use block. The delay is necessary in order to subtractive block happened subtraction codes previous frequency structure of a signal are counted by the counter 5, and read from the cells of the register 30. Further processing is carried out according to the same algorithm. For the third frequency structure of the signal to the second input element And 3 will be received pulses with a frequency three times less than the clock. Only during the third frequency to the second input element And 3 will go two impulse.

The counter 16 counts the total number of frequencies in the structure of the signal in the calculation of the M frequencies produces a signal on an item And 25. In the case when the structure of the received signal and the copy of the signal stored in the register 30, the same, the counter 18 will register M is zero difference, at the output of this counter is a signal, which indicates that the received QH signal varies. Otherwise, the counter 18 will not work, that will lead to the appearance of the signal at the output of the element And 25, which shows that adopted DF signal is not consistent with this device. When this signal through the OR element 26 is bringing the device to the initial state (reset counters 5, 9, 16, 18, pria to the first output).

The DEVICE is DECODING MULTI-frequency SIGNALS containing the filter, the output of which is connected to the comparator input, the register, the first delay element, the first, second, third, fourth counters, the first and second elements And the first and second elements OR, block compare, allocator, subtractive unit, characterized in that the block elements And the third and seventh elements OR, third, and fourth elements, block element OR block key block elements OR block the initial installation, the block division frequency, the second and third delay elements, moreover, the output of the comparator is connected to the first input of the first element And the output of which is connected to the negative input of the third element And through the first delay element to the first input of the second element And whose output is connected to the direct input of the third element And whose output is connected to the counting input of the first counter, the output of which is connected to the first input of the block elements And the second input, the first input of the fifth element OR the first subtractive inputs of the block, the block comparison, the first element OR is connected to the output of the second counter, the counting input of which the second input of the second element And the first input unit of frequency division and United AOM first element OR the output of block initial installation is connected with the first inputs of the third and fourth elements OR the second input of the first element OR the third input, the second input of the third element OR the second input of the fourth element OR is connected to the output of the sixth element, OR the first input and the inverted input of the fourth element And is connected to the output of the fourth counter, which is the first output, a second output which is the output of the fourth element And connected to a second input of the sixth element OR the output of block elements And is connected to the second subtractive input block, the output of which is connected to the second input of the comparison, the first and second outputs of which are connected respectively with the first and second inputs of the second element OR the output of which is connected to a counter input of the third counter, the input of the initial installation of which the counting input of the fourth counter connected to the output of the third element OR the second output unit of comparison is connected to the input of the initial installation of the fourth counter, the output of the third counter connected to the direct input of the fourth element And the fourth element OR via a second delay element connected to the second input of the fifth element is that element OR, the output of the distributor connected to the first input of the block elements AND OR, the output of which is connected to the second input unit of frequency division and through the third delay element with a third subtractive input block, output block division frequency is connected to the second input of the first element And the outputs of the block of keys connected to inputs of the unit's permanent memory and the sixth element OR the output of which is connected to a clock input of the register, the output of which is connected to the second input of block elements AND / OR outputs of the unit's permanent memory through the block elements OR connected to information inputs of the register.

 

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