Storage capacitor element of the memory integrated circuits
(57) Abstract:Usage: in electronic engineering, in particular in manufacturing processes of semiconductor memory circuits on MIS-transistor. The inventive storage capacitor of the memory element of the integrated circuits includes a first facing layer of conductive material formed on the surface created in the semiconductor plate depressions on the surface of which created the tabs, the capacitor dielectric and the second facing, applying to the entire surface of the first sheath, including the tabs. 1 Il. The invention relates to electronic devices and can be used in the manufacture of semiconductor memory circuits for MOS transistors.Known storage capacitor of the memory integrated circuits formed in the semiconductor substrate and including a first facing layer of conductive material, capacitor dielectric, insulating the first plate from the second layer of conductive material, while the capacitor dielectric is made in the form of a meander . A disadvantage of the known device is the low quality and reliability due to leakage currents, which is associated with the absence of playmost anatomy element, formed in the semiconductor substrate  . In this device one of the condenser elements is the capacity of the p-n junction formed by two semiconductor layers. A layer of n+-type conductivity is made with the bumps and hollows. Known condenser design is of poor quality and reliability, because the capacitor is used as the p-n junction, which leads to leaks and random crashes.The purpose of the invention is reducing the size of the capacitor, while maintaining its capacity, higher reliability.This is achieved by the fact that in the storage capacitor of the memory element of integrated circuits, including in-depth in the substrate is first coated with a relief surface, the separation region, the second plate, the bottom surface which follows the relief of the first dividing region made of dielectric material, and the lining is made of doped polysilicon.The drawing shows the structure of the storage capacitor element of the memory integrated circuits, the cross-section.It contains the first plate 1 capacitor of a doped polysilicon created on its surface protrusions 2, alitalo region 4 of a dielectric material, the second plate 5 of doped polysilicon, the bottom surface which follows the relief first.The working storage capacitor is identical to the standard transistor of the memory element dynamic storage device. In the technical solution according to the invention is obtained groove with multiple conductive walls, which allows not only to increase the effective area of the first capacitor plates, but also to increase playmost surface after forming the capacitor plates, for slamming each branch of the grooves is at a lower thickness of the conductive material of the second sheath.Using the proposed design, the developer may select, based on the requirements of a specific device.In the first embodiment it is possible to increase the thickness of the capacitor dielectric. This will give the opportunity to improve the reliability of the memory elements VLSI by increasing the breakdown voltage of the capacitor dielectric and reduce the leakage current of the capacitor. The decrease in capacitance by increasing the thickness of the dielectric is compensated by the increase of the effective surface of the plates due to the protrusions of navigating The second option, you can simultaneously increase the capacity of the storage capacitor of the memory element of integrated circuits by increasing the effective surface of the plates and reduce leakage currents (for example, by increasing the thickness of the capacitor dielectric 1.5 times) without changing the area of the accumulating capacitor in the plan. This allows to increase the reliability of the memory elements of the integrated circuits to random failures.The third option may reduce square storage capacitor in the plan without changing the capacitance and breakdown voltage.Using the proposed design, the developer receives a freedom of choice in the thickness of the dielectric and square plates to ensure the reliability of the semiconductor integrated circuit memory.Storage capacitor of the memory element of the integrated circuit is manufactured as part of the dynamic memory element operative memory (dram) 256 Kbps using additional IGOS. The first plate 1 on the surface created in the semiconductor wafer 3 KDB-12 deepening depth of 2 microns with a size in terms of 2x2 µm2formed from doped with phosphorus imported from Germany is of doped phosphorus polycrystalline silicon. Capacitor dielectric 4 is formed of Si3N4the thickness of 27.5 2.5 nm. The second plate 5, as well as first, create a layer of doped polycrystalline silicon with a thickness of 0.1 to 0.01 μm. By varying the thickness of the dielectric, it is possible to reduce the amount of leakage current.The invention increases the operational reliability of the storage capacitor and a semiconductor integrated circuit memory, the design of which includes a memory cell that uses capacitors to store information. Storage CAPACITOR of the MEMORY ELEMENT INTEGRATED circuit containing the first and second plates and the separation region, and the first lining is deepened in the substrate and its upper surface is made visible, and the lower surface of the second casing follows the relief of the first, characterized in that the separation region is made of a dielectric material, and the lining is made of doped polysilicon.
FIELD: computer engineering and integrated electronics; integrated logic gates of very large-scale integrated circuits.
SUBSTANCE: newly introduced in integrated logic gate that has semi-insulating GaAs substrate, first input metal bus, first AlGaAs region of second polarity of conductivity disposed under the latter to form common Schottky barrier junction, first inherent-conductivity AlGaAs spacer region disposed under the latter, first GaAs region of inherent-conductivity channel disposed under the latter, second AlGaAs region of second polarity of conductivity, second AlGaAs spacer region of inherent conductivity, second input metal bus, output region of second polarity of conductivity, output metal bus, power metal bus, zero-potential metal bus, and isolating dielectric regions are inherent-conductivity AlGaAs tunnel-barrier region, InGaAs region of inherent-conductivity channel, AlGaAs region of second inherent-conductivity barrier, L-section power region of second polarity of conductivity, and Г-section zero-potential region of second polarity of conductivity; first GaAs region of inherent-conductivity channel and InGaAs region of inherent-conductivity channel are disposed in relatively vertical position and separated by AlGaAs region of inherent-conductivity tunnel barrier; output region of second polarity of conductivity is ┘-shaped and ┘-section region.
EFFECT: enhanced efficiency of using chip area, enhanced speed and reduced power requirement for integrated logic gate switching.
1 cl, 3 dwg
FIELD: computer science and integral electronics, in particular - engineering of VLSI integral logical elements.
SUBSTANCE: integral logical element contains semi-insulated GaAs substrate, first input metallic bus, first AlGaAs area of second conductivity type, positioned above aforementioned bus and forming Schottky transition together with it, below it first AlGaAs area of native conductivity spacer is positioned, below it, first GaAs area of native conductivity channel is positioned, second AlGaAs area of second conductivity type, second AlGaAs area of native conductivity spacer, second input metallic bus, output area of second conductivity type, output metallic bus, zero potential metallic bus, metallic power bus, areas of separating dielectric. Integral logical element additionally contains AlGaAs area of native conductivity tunnel barrier, InGaAs area of native conductivity channel, AlGaAs area of second conductivity barrier, zero potential area of second conductivity type with transverse cross-section in form of symbol L, while first GaAs area of native conductivity channel and InGaAs area of native conductivity channel have vertical mutual position and are divided by AlGaAs area of native conductivity tunnel barrier, output area of second conductivity type is L-shaped and has L-shaped cross-section.
EFFECT: decreased efficiency of crystal area usage, increased speed of operation and decreased energy consumed by switching integral logical element.
FIELD: power semiconductor microelectronics.
SUBSTANCE: newly introduced in central part of semiconductor structure that has substrate, semiconductor material with depleted area in its central part enclosed by depleted area in peripheral part of structure, and relevant current-conducting contacts are recessed components of reverse polarity of conductivity with spherical depleted area whose electric field strength is higher than that of depleted areas in gap between recessed components and in peripheral part of structure.
EFFECT: improved power characteristics, enhanced resistance to pulse overcurrents.
7 cl, 1 dwg
SUBSTANCE: invention relates to design and technology of manufacturing semiconductor integrated circuits (IC) and can be used in digital, analogue and memory units in microelectronics. The semiconductor IC has a high-resistance monocrystalline silicon layer grown in form of a hollow cylinder in which there are regions with different conduction type, which form bipolar transistors, resistors and capacitors. On the outer surface of the high-resistance monocrystalline silicon layer there are emitter and base contacts adjacent to corresponding regions of corresponding transistors connected to resistors and capacitors by conductive paths formed on the surface of a dielectric placed on the outer surface of the high-resistance monocrystalline silicon layer, and on the inner surface of the high-resistance monocrystalline silicon layer there is a collector contact in form of a hollow cylinder adjacent to the collector regions of the transistors or the adjacent silicon layer.
EFFECT: higher degree of integration of the IC, reduced feature size of the element, lower level of inter-electrode connections, reduction of power consumption by one switching, increased reliability.
3 cl, 1 dwg
SUBSTANCE: semiconductor structure of the logical element AND-NOT comprising the first and second logical transistors, the first and second injecting transistors and a substrate is made as nanosized with a stepped profile and comprises four collectors, four bases and at least four emitters on the substrate of the first type of conductivity.
EFFECT: reduced consumed power and increased efficiency.
SUBSTANCE: in the integral logical AND-NOT element based on a layered three dimensional nanostructure (the element containing the first and the second logical transistors, the first and the second injecting transistors and a substrate) the logical structure is designed to be nanosized with a stepped profile.
EFFECT: increased response speed and reduced power consumption.
SUBSTANCE: multifunctional microwave monolithic integrated circuit board based on a multilayer semiconductor structure combines functions of several monolithic integrated circuit boards and comprises field-effect Schottky transistors and quasivertical Schottky barrier diodes with high values of boundary frequencies, which are integrated at the same chip and used as active and non-linear elements. Active areas of the field-effect transistors and basic areas of the quasivertical diodes are placed in different epitaxial layers with a low-ohmic contact layer placed between them and ohmic source and drain contacts of the transistors and ohmic cathodic contacts of the diodes are attached to it.
EFFECT: increased degree of integration for the microwave multifunctional integrated circuit board, reduced weight and dimensions for receiving and transmitting modules of antenna arrays, reduced losses related to signals passage between the schemes of functional units, increased boundary frequencies for the Schottky barrier diodes.
SUBSTANCE: in a semiconductor device a diode area and IGBT area are formed at the same semiconductor substrate. The diode area includes a multitude of anode layers with the first type of conductivity open at the surface of the semiconductor substrate and separated from each other. The IGBT area includes a multitude of contact layers of the body with the first type of conductivity open at the surface of the semiconductor substrate and separated from each other. An anode layer includes at least one or more first anode layers. The first anode layer is formed close to the IGBT area at least, and the square area in each of the first anode layers in the direction of the semiconductor substrate plane is more than the square area in each contact layer of the body in direct vicinity from the diode area in the direction of the semiconductor substrate plane.
EFFECT: invention prevents direct voltage growth in the diode area and increased heat losses.
2 cl, 5 dwg
FIELD: process engineering.
SUBSTANCE: invention relates to microelectronics, particularly, to production of solid-state devices by evaporation of metal coating on the substrate back surface. Claimed process consists in that the substrate is flexed in reverse direction before evaporation of metal coating. It differs from known processes in that said coating is evaporated on substrate back surface through stencil with through holes shaped and sized to crystals. Jumpers between said holes in stencil are comparable with the width of division webs made between crystals on substrate face surface.
EFFECT: reduced residual thermomechanical strains at said boundary.
FIELD: manufacturing technology.
SUBSTANCE: invention relates to production of integrated microcircuits in part of interposer forming for 3D assembly of several chips in single micro-system and process of its production. Invention is aimed at reducing effect of temperature gradients and associated mechanical stresses arising in body of interposer during operation of integrated microelectronic system. For this purpose, in body of interposer around through holes (TSV) filled with conducting material to create electric connection of metallized electric wiring working side with metallized layout of interposer reverse side formed holes, one of topological dimensions considerably smaller than minimum feature size TSV.
EFFECT: formed holes for reducing effect of temperature gradients are filled with material with heat conductivity higher than that of silicon, for compensation of mechanical stresses are not filled or are filled partially with formation of cavities inside hole.
18 cl, 11 dwg