(57) Abstract:The invention relates to a pulse technique. The task of the technical solutions - ensuring control of the two pulse signals, a single failure of one of them is not a sign of failure. The device comprises a first 1 and second 2 outputs, the first 3 and second 4 shift registers, the pulse generator 5, the inverter 6, the first 7 and second 8 blocks of persistent information, the first 9 and second 10 outputs and a source of constant zero information 11. The first 1 and second 2 inputs connected to the parallel inputs of the first 3 and second 4 shift registers, the outputs of the last digits of which are the first 9 and second 10 outputs the device, the pulse generator 5 is connected to the output of input clock pulses shift registers 3 and 4 and the inverter 6 is connected to the input with the output of the last digit of the register 3, and the output - information input serial write register 3. While the parallel inputs of the data registers 3 and 4 are connected to the corresponding 7, 8 blocks of persistent information, and the structure of the code in these blocks bitwise mutually inverse, and the first information input of the second sequential write register 4 is connected to the source postojano in the automation devices of railway transport with safe failures.The well-known scheme paraphase trigger that contains the logical elements AND NOT forming RS-triggers .The disadvantage of this device is the inability of its application for control signals, for which a valid single drop of parafanalia.The closest technical solution of the invention is a paraphase inverter, containing memory elements (RS-triggers, made by well-known scheme for logic elements AND IS NOT), two inputs controlled two-rail signals, and two outputs, in which case compliance with parafanalia input signals is provided by the presence of two-rail signals .The disadvantage of this device is the inability of its application for control signals, for which a valid single drop of parafanalia.The objective of this technical solution is to provide two control pulse signals, a single failure of one of them is not a sign of failure.The task is implemented as follows. Paraphase inverter includes first and second shift registers, recording inputs of which are connected to first and second inputs of the device is ejstvujuschij constant blocks are mutually inverse information moreover, the structure of the code in these blocks bitwise mutually inverse, and the outputs of the last shift registers are respectively first and second output devices, and input and output of the inverter is connected respectively with the output of the last discharge and the information input sequential record of the first shift register, and the information input sequential record of the second shift register is connected to a source of constant zero signal. Using shift registers, one based on the chipset 533 IL-9, the inverter and the pulse generator, one based on the chipset 533 LN 1.The drawing shows a functional diagram of the device.The device comprises a first 1 and second 2 inputs, the first 3 and second 4 shift registers, the pulse generator 5, the inverter 6, the first 7 and second 8 blocks ongoing mutually inverse of the information, the first 9 and second 10 outputs and the source 11 constant zero information.The first 1 and second 2 inputs connected to the parallel inputs of the first 3 and second 4 shift registers, the outputs of the last digits of which are the first 9 and second 10 outputs of the device, the generator 5 is connected to the output inputs that is 3, and output information input serial write register 3. While the parallel inputs of the data registers 3 and 4 are connected to the respective blocks 7, 8 permanent information, and the structure of the code in these blocks are mutually inverse, and the first information input of the second sequential write register 4 is connected to the source 11.In normal operation on the input device receives two pulses, which produce an entry in the registers 3 and 4 information set in blocks 7 and 8. At clock inputs of registers receives pulses from the generator 5, the frequency of which is inversely proportional to the allowable number of loss of input pulses, and the required shift register is determined by the formula
S = (1/n + 1) 100% where n is the number of failures. Thus in accordance with the above in case of admission of one failure register is shifted by half its capacity (50%), for two to 32%, for the three - 25%, and so on, due to the fact that the information in blocks 7 and 8 bitwise mutually inverted outputs high-order bits of the registers and the outputs 9 and 10 devices are supported two-rail signals.In the case of a single failure of one (simultaneous failure of both) from whodunnit register shifted information only, for example, half of its capacity, at the outputs 9 and 10 devices are supported two-rail signals before the arrival of the next input pulse.If there is a prolonged interruption of the input pulse, is a violation of parafanalia at the outputs 9 and 10 of the device, due to the violation of the mutually inverse of the information in the shift registers 3 and 4 due to the operation of the inverter 6 and zero source of information 11.In case of violation of the logic of any unit also breaking parafanalia signal at the outputs 9 and 10. Two-rail CONVERTER comprising first and second inputs, the first and second memory elements, the first and second outputs, characterized in that it introduced an inverter, a pulse generator, a source of constant zero signal, the first and second blocks of constant usamainterpol information, and the memory elements made in the form of shift registers, while the recording inputs of the first and second shift registers are first and second inputs of the Converter, the outputs of the last bits of the first and second outputs of the Converter, the input clock pulses is connected to the output of the pulse generator, the parallel inputs of information and are connected respectively with the output of the last discharge of the first register and data input sequential record of the first register, information input sequential record of the second register is connected to a source of constant zero signal.
FIELD: railway automatic control and teleautomatics, centralized power control systems including control computer systems for microprocessor centralizing switches and signals for small, medium, and large railway stations.
SUBSTANCE: novelty is that proposed device characterized in greater quantity of parameters being diagnosed and in introduction of means for on-line variation of controlled-entity modes of operation that has pulse signal supplies (PSS) 1, power supplies, final-relay unit (FRU) 5, control-signal supply units (CSSU) 3, output switches (OS) 4, output-switch monitoring units (OSMU) 6 is provided with newly introduced three data acquisition modules (DAM) 15, three processor units PU 12, and three memory units (MU) 13. Power supply of each of three channels is made in the form of safety monitoring and disconnection module (SMDM) 2 designed for generation, monitoring, and on-line disconnection of supply voltages from output stages of OS 4 and PSS 1. PSS 1 unit, OS 4, OSMU 6, and their interconnections are integrated into output amplifier module (OAM) 16 designed to supply control signals for final relays through OS unit 4 and SMDM 2 control signals through PSS 1. CSSU 3 unit, PU 12 unit, MU 13, and their interconnections are integrated into controller module (CM) 14 designed to control OS 4 unit, PSS 1, as well as to check final relays, floor-mounted equipment, and output switches for condition; OAM 16 inputs designed to supply with power output stages of PSS 1 and OS 4 units in each of device channels are connected to respective outputs of same-channel SMDM 2, two other inputs of OAM 16 designed to control PSS 1 and OS 4 units are connected to respective outputs of same-channel CM 14, output designed to check OAM 16 output switches for condition is connected to one of inputs of same-channel CM 14 and first of OAM 16 outputs designed to control SMDM 2 is connected to first of same-channel SMDM 2 inputs. Second and third outputs of first-channel OAM 16 designed to control SNDM 2 are connected to second and third inputs of SMDM 2 of third and second channels, respectively; second-channel OAM 16 is connected to second and third inputs of first- and third-channel SMDM 2, respectively; third-channel OAM is connected to second and third inputs of second- and third-channel SMDM 2, respectively. Same outputs of OAM 16 output switches of three channels are interconnected and connected to FRU 5; same inputs of DAM 15 of three channels designed to receive feedback signals informing about condition of final relays and floor-mounted equipment are likewise interconnected; output of each DAM 15 is connected to second and first input/output of CM 14 of third and second channels, respectively; second input/output of second-channel CM 14 is coupled with first input/output of third-channel MC 14. Trigger inputs of all SMDM 2 are interconnected.
EFFECT: enhanced safety of traffic, enlarged functional capabilities.
1 cl, 1 dwg
FIELD: digital pulse engineering.
SUBSTANCE: proposed device designed for shaping pulses of desired length for each of three events during power turn-on in response to off-operation button signal incorporating provision for chatter elimination in case of skip or stop of changes in input pulses on detection enabling has first and second monostable restart multivibrators 1, 4, off-operation button 2, flip-flop 3, shaper 5 of signal responding to button-provided power turn-on which is built around capacitor 12, resistors 13, 14, diode 15 and two NAND gates 6,7, as well as AND gate 8, controllable pulse generator 9, logical 1 input, pulse signal input 10, and control input 11. Controllable pulse generator 9 is built around AND gate 16, NAND gate 17, resistors 18, 19, and capacitor 20. Device can shape input pulse during power turn-on period and function as hardware watch timer implemented in the course of forward and backward automatic interaction with system microcontroller.
EFFECT: enlarged functional capabilities of device.
1 cl, 1 dwg
FIELD: digital pulse engineering.
SUBSTANCE: proposed device that can be used for shaping output pulses of desired length for each of three events (power turn-on, detection of input-signal pulse skipping or hanging [stop of changing] when detection is enabled in response to signal from closing button, including chatter suppression) provides for shaping output pulse during power turn-on and can function as hardware watch timer enabling generation of output pulse in case of skipping or hanging of input signal pulse. Device has first and second resistors 1, 2, closing button 4, capacitor 5, logical follower 6, inverted pulse signal output, common bus, and power supply bus. In addition, device has third resistor 3, NAND gate 7, first and second AND gates 8, 9, power turn-on and push-button signal integrator 10, pulse detector 11, pulse signal input 12, and control input 13.
EFFECT: enlarged functional capabilities.
1 cl, 1 dwg
FIELD: digital pulse engineering.
SUBSTANCE: proposed device designed for shaping output pulses of desired length for each of three events, that is, signal front across first control input, signal zero level from closing button incorporating provision for chatter suppression, and detection of pulse skipping across signal pulse input has seven resistors 1 - 7, two capacitors 11, 18, button 10, first and second control inputs 12, 13, pulse input 14, AND gate 17, NOT gate 8, two NAND gates 9 - 16, NOT gate with open collector output 15, and pulse signal envelope detector 19. This pulse shaper can be used, for instance, as system reset pulse shaper of numeric control device.
EFFECT: enlarged functional capabilities.
1 cl, 1 dwg
FIELD: impulse engineering, possible use in impulse analyzing devices to select impulses with given parameters of duration, amplitude and period.
SUBSTANCE: device contains differentiating element, zero level limiter, inverter, three delay blocks, key, adder, multi-level amplitude selector, commutator, trigger, saw-shaped voltage generator, AND element, subtracting device.
EFFECT: expanded functional capabilities of device due to selection of both periodic impulses with given duration and amplitude parameters, and impulses appearing in random time moments.
FIELD: impulse engineering, possible use in devices for analyzing impulses to select impulses with given parameters of duration, amplitude and period.
SUBSTANCE: device contains input impulse generator, three delay blocks, key, adder, multilevel amplitude selector, commutator, trigger, saw-shaped voltage generator, AND element, subtracting device.
EFFECT: expanded functional capabilities due to selection of both periodic impulses with given parameters and impulses which appear in random time moments.
FIELD: radio engineering, possible use for finding a stack of mutually coherent impulses.
SUBSTANCE: device contains input block, connected to first input of adder. Second input of adder is connected to output of reverse communication amplifier. New feature is the introduction of compensating amplifier and band filter. Input of amplifier is connected to output of delay line, and output of amplifier is connected to input of band filter. Delay line consists of input, intermediate and output of inter-digital transformers on sound-conductive substrate. Duration of interaction of train of waves in output inter-digital transformer is selected to be several times or several dozen times greater than delay of signal between input and intermediate inter-digital transformers, output inter-digital transformer is made in form of continuous mono-periodical structure, matched with carrying frequency of received radio-impulses, and connected to input of compensating amplifier. Pass band in band filter is selected to be commensurable with reverse value of duration of radio-impulse signal generated in output inter-digital transformer.
EFFECT: increased detection capability of accumulator without worsening of its stability.
FIELD: radio engineering and impulse engineering, possible use for selection and measurement of parameters of regular and random impulse series.
SUBSTANCE: impulse series selector contains input impulse generator (1), at first and second outputs of which impulses of constant duration are generated, proportional to amplitude of input impulses, corresponding to rise-up and descending parts of input impulses respectively, delay blocks (2,4,5,7), AND elements (3,12), adder (6), multi-level amplitude selector (8), commutator (9), triggers (10,13), keys (11,14,15), and computing device (16). At first output of selector one periodical series of impulses is received with preservation of its amplitude. At second output of selector, all impulses are received with given amplitude and duration both from periodical series and those that appear in random time moments. At third output of selector all remaining impulses which may be used for further analysis are singled out. At fourth output of selector, impulses with given amplitude and duration, which appear in random time moments, are singled out.
EFFECT: expanded functional capabilities when analyzing and processing impulse series due to usage of informative impulse parameters.
FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in digital automatic systems. The technical outcome allows for quantitative measurement of the degree of short term mismatch between pulses. The device contains pulse formers (1-4), AND elements (5-7), OR elements (8 and 9), delay elements (10-12), RS flip-flops (13 and 14), standard frequency generator (15), pulse counter (16), memory register (17), input (18) for the first controlled pulse train and input (19) for the second controlled pulse train. The newly introduced AND element (7), delay elements (10-12), RS flip-flop (13 and 14), generator (15), pulse counter (16) and register (17) allow for achieving the said technical outcome.
EFFECT: increased functionalities of the control device.