Paraphase inverter

 

(57) Abstract:

The invention relates to a pulse technique. The task of the technical solutions - ensuring control of the two pulse signals, a single failure of one of them is not a sign of failure. The device comprises a first 1 and second 2 outputs, the first 3 and second 4 shift registers, the pulse generator 5, the inverter 6, the first 7 and second 8 blocks of persistent information, the first 9 and second 10 outputs and a source of constant zero information 11. The first 1 and second 2 inputs connected to the parallel inputs of the first 3 and second 4 shift registers, the outputs of the last digits of which are the first 9 and second 10 outputs the device, the pulse generator 5 is connected to the output of input clock pulses shift registers 3 and 4 and the inverter 6 is connected to the input with the output of the last digit of the register 3, and the output - information input serial write register 3. While the parallel inputs of the data registers 3 and 4 are connected to the corresponding 7, 8 blocks of persistent information, and the structure of the code in these blocks bitwise mutually inverse, and the first information input of the second sequential write register 4 is connected to the source postojano in the automation devices of railway transport with safe failures.

The well-known scheme paraphase trigger that contains the logical elements AND NOT forming RS-triggers [1].

The disadvantage of this device is the inability of its application for control signals, for which a valid single drop of parafanalia.

The closest technical solution of the invention is a paraphase inverter, containing memory elements (RS-triggers, made by well-known scheme for logic elements AND IS NOT), two inputs controlled two-rail signals, and two outputs, in which case compliance with parafanalia input signals is provided by the presence of two-rail signals [2].

The disadvantage of this device is the inability of its application for control signals, for which a valid single drop of parafanalia.

The objective of this technical solution is to provide two control pulse signals, a single failure of one of them is not a sign of failure.

The task is implemented as follows. Paraphase inverter includes first and second shift registers, recording inputs of which are connected to first and second inputs of the device is ejstvujuschij constant blocks are mutually inverse information moreover, the structure of the code in these blocks bitwise mutually inverse, and the outputs of the last shift registers are respectively first and second output devices, and input and output of the inverter is connected respectively with the output of the last discharge and the information input sequential record of the first shift register, and the information input sequential record of the second shift register is connected to a source of constant zero signal. Using shift registers, one based on the chipset 533 IL-9, the inverter and the pulse generator, one based on the chipset 533 LN 1.

The drawing shows a functional diagram of the device.

The device comprises a first 1 and second 2 inputs, the first 3 and second 4 shift registers, the pulse generator 5, the inverter 6, the first 7 and second 8 blocks ongoing mutually inverse of the information, the first 9 and second 10 outputs and the source 11 constant zero information.

The first 1 and second 2 inputs connected to the parallel inputs of the first 3 and second 4 shift registers, the outputs of the last digits of which are the first 9 and second 10 outputs of the device, the generator 5 is connected to the output inputs that is 3, and output information input serial write register 3. While the parallel inputs of the data registers 3 and 4 are connected to the respective blocks 7, 8 permanent information, and the structure of the code in these blocks are mutually inverse, and the first information input of the second sequential write register 4 is connected to the source 11.

In normal operation on the input device receives two pulses, which produce an entry in the registers 3 and 4 information set in blocks 7 and 8. At clock inputs of registers receives pulses from the generator 5, the frequency of which is inversely proportional to the allowable number of loss of input pulses, and the required shift register is determined by the formula

S = (1/n + 1) 100% where n is the number of failures. Thus in accordance with the above in case of admission of one failure register is shifted by half its capacity (50%), for two to 32%, for the three - 25%, and so on, due to the fact that the information in blocks 7 and 8 bitwise mutually inverted outputs high-order bits of the registers and the outputs 9 and 10 devices are supported two-rail signals.

In the case of a single failure of one (simultaneous failure of both) from whodunnit register shifted information only, for example, half of its capacity, at the outputs 9 and 10 devices are supported two-rail signals before the arrival of the next input pulse.

If there is a prolonged interruption of the input pulse, is a violation of parafanalia at the outputs 9 and 10 of the device, due to the violation of the mutually inverse of the information in the shift registers 3 and 4 due to the operation of the inverter 6 and zero source of information 11.

In case of violation of the logic of any unit also breaking parafanalia signal at the outputs 9 and 10.

Two-rail CONVERTER comprising first and second inputs, the first and second memory elements, the first and second outputs, characterized in that it introduced an inverter, a pulse generator, a source of constant zero signal, the first and second blocks of constant usamainterpol information, and the memory elements made in the form of shift registers, while the recording inputs of the first and second shift registers are first and second inputs of the Converter, the outputs of the last bits of the first and second outputs of the Converter, the input clock pulses is connected to the output of the pulse generator, the parallel inputs of information and are connected respectively with the output of the last discharge of the first register and data input sequential record of the first register, information input sequential record of the second register is connected to a source of constant zero signal.

 

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