A method of manufacturing semiconductor devices
(57) Abstract:Usage: in microelectronics for the production of Schottky transistors on the Mesa-structures. The inventive method includes the manufacture of semiconductor devices on politology plusline of gallium arsenide with an active structure by forming a Mesa structure, forming a mask of silicon dioxide with a window above the active region of the device, forming a protective mask anodic oxidation, removing the mask of silicon dioxide by plasma-chemical etching, annealing protective mask anodic oxide, the formation of the contact to the reverse side of the wafer and the deposition of the ohmic contact of the electrolyte with an additional plate lighting. This is achieved by improving the quality of ohmic contacts. 5 Il. The invention relates to semiconductor technology and can be used in the manufacture of Schottky field-effect transistors.A known method of manufacturing field-effect transistors on the Mesa-structures  . Mesa structure is formed by chemical etching in a solution of NH4OH:H2O: H2O. Ohmic contacts create thermal spraying of a layer of Au-Ge-Ni with a thickness of 0.15 μm, followed by "Bang" photoresistive swity relief, numerous pores. The result is increased ohmic resistance. In addition, most of the deposited layer is removed along with photoresistive mask, which is uneconomical.The closest technical solution of the invention is a method of manufacturing semiconductor devices, comprising the oxidation of meso-structures and electrochemical deposition of the contact mask anodic oxide . Use patterns GaAlAs. For local oxidation Mesa and deposition of contacts using conductive layer GaAs n-type.The disadvantage of this method is that when the deposition from the electrolyte Au-Ge contacts the dissolution occurs mask anodic oxide. In the contaminated electrolyte, shortens its life. In addition, this method does not allow to use politology substrate.Technical result achieved during implementation of the method is to improve the quality of ohmic contacts by reducing contamination of the electrolyte in the process of their deposition, by increasing the chemical resistance of the mask anodic oxide and reducing its area.The result is achieved by conducting anodic oxidation only areas of the channel, after-the La in the channel and as the plate material used politology gallium arsenide.In the proposed method, the annealing is carried out in the temperature range 300-500aboutWith to improve chemical resistance of oxide. At lower temperatures, the anodic oxide thickness of 0.1 μm almost completely dissolved in the electrolyte during the deposition of the metal. At temperatures above 500aboutWith the surface of the semiconductor in the channel is enriched with arsenic, increase the point of leakage of the transistor.According to the proposed method of anodic oxidation of the plates is carried out only in the channel region of a transistor, which reduces the amount of anodic oxide, dissolving in the deposition of contacts. The deposition is carried out at intensive plate lighting. As a result, the contacts are formed only on the n+-the surface of the active regions. On the surface of the Mesa deposition of metal does not occur in the absence of additional photoresistive mask.In Fig. 1 shows a plate with a Mesa structure of Fig. 2 - plate with a photoresistive mask for forming the channel of Fig. 3 - plate with anode oxide in the channel of Fig. 4 - plate with deposited from the electrolyte contacts; Fig. 5 - shows a General view of the manufactured device.For a specific example of the use of UP>3< / BR>thickness of dn+=0.2 μm
n=1.5 1017at/cm3dn=0,35 µm
dn 0.5 micron.On the surface of the plate create a photoresistive mask that protects the active area of semiconductor devices. Form a Mesa structure by etching in a solution of H3PO4:H2O2:H2O the depth of the Mesa 0.8 μm, the angle of the Mesa-faces 10about. The photoresist is removed in dimethylformamide (Fig. 1). Put a layer of SiO2the thickness of 0.3 μm. Create a photoresistive mask with Windows over the channel regions of the transistors (Fig. 2). Remove SiO2in the Windows in the buffer provide the Etchant NH4F:HF:H2O. the Photoresist is removed. Carry out anodic oxidation of the plate mask SiO2forming the channel of the transistor. The thickness of the oxide layer of 0.2 μm, the depth of etching of 0.14 μm. The cell voltage 130 Century.Remove SiO2plasmochemical selectively to the gallium arsenide and the anodic oxide (Fig. 3). Hold the lamp annealing plates with anodic oxide at a temperature of 400aboutC for 40 s using the "Impulse 5". Annealing is required to improve chemical resistance of anodic oxide. Thus the rate of dissolution of oxide in the deposition of ohmic contacts is reduced from 600 rpm (for geotagging), 400 /) 300aboutWith chemical resistance oxide almost does not increase. The layer of anodic oxide thickness of 0.15 μm in the deposition of contacts is completely dissolved. At annealing temperatures above 500aboutTo change the stoichiometric composition of the surface of a semiconductor. The surface is enriched with arsenic.The plate is treated in a solution of NH4OH:H2O2:H2O=1:0,5:40 for 5 s to remove the natural oxide on exposed regions of n+-layer. Then install the plate in the cassette horizontally. Create electrical contact to the bottom politology side of the wafer in a solution of KOH:NH4H2PO4:H2O=3y: 0.3 g: 100 ml for lighting. The amount of light of 100,000 Lux. In the absence of light through the current through the plate does not leak. The electrolyte for the deposition of Au-Ge fill the upper part of the cassette plate. Precipitated Au-Ge ohmic contacts by the intense light of 100,000 Lux. Duration of 3 min cell Voltage of 2 V, the total current through the plate of 0.7 mA. The thickness of the formed contacts 800 . The deposition of metal occurs only on the surface of the n+-layer active regions on the mask anodic oxide in the channel. On the surface of the etched Mesa metal not academese-face the corresponding n-layer. When the amount of light more than 70,000 Lux metal on meze not find.In the process of deposition of a metal anodic oxide is dissolved, contaminating the electrolyte. According to the proposed method the surface area of the anodic film is minimal, as they form only in the channel of the transistor. The dissolution rate of oxide reduce heat treated.Fuse ohmic contacts on the installation of the lamp annealing "Impulse 5" at a temperature of 450aboutWith 3 pulse duration of 4 C. After the mould surface contacts preserves the original morphology. When the thickness of the contacts larger than 0.1 μm develops relief, at thicknesses of less than 400 increases the ohmic resistance. The ohmic resistance of the formed contacts 0.1 Ohm mmCreate a photoresistive mask with a pattern of the gate. Remove the anodic oxide remaining after the manifestation of the mask, in a solution of NH4OH:H2O=1:20 for 20 sec. Hold chemical etching of gate regions to provide a specified current saturation in a solution of NH4OH:H2O2:H2O=1:0,5:40. Sprayed layer of gate metallization V-Au-V with a thickness of 0.7 μm. "Explosion" photoresistive mask to form the gate. In areas kanaal the surface of a semiconductor. This increases the breakdown voltage of the transistor.According to the proposed method, the deposition of ohmic contacts on the n+-the surface of the active regions is carried out only on the mask anodic oxide in the channel. This allows to decrease in the deposition of metal, the amount of soluble anodic oxide, to reduce contamination of the electrolyte to increase its service life. Carrying out heat treatment increases the chemical resistance of the anodic film. Anodic oxide in the channel increases the breakdown voltage of the transistor.Samozavestna area of channel deposition of ohmic contacts eliminates the need for the formation of the photoresist mask, allows to minimize the distance of the source - drain.Formed by deposition from the electrolyte thin (400-1000 ) Au-Ge contacts remain after the mould of the original morphology of the surface are low, 0.1 Ohm mm, ohmic resistance. A method of MANUFACTURING a SEMICONDUCTOR device, comprising forming on the surface of the wafer of gallium arsenide with an active structure of the mask of silicon dioxide, the formation of the Mesa structure, the formation of a protective mask anodic oxidation, removing the mask of silicon dioxide n the side plates, characterized in that as the plate material used politology gallium arsenide, mesostructure formed before formation of the mask of silicon dioxide, a mask of silicon dioxide is formed with a window above the active region of the device, after removing the mask of silicon dioxide spend annealing protective mask anodic oxide, the contact to the back side of the plate is formed before the deposition of ohmic contacts, and in the deposition of ohmic contacts plate additionally light.
FIELD: technologies for making transistors.
SUBSTANCE: method includes following stages: precipitation of electric-conductive material on substrate of semiconductor material, forming of shape of first parallel band electrodes with step, determined by appropriate construction rules, while areas of substrate in form of stripes between first electrodes are left open, precipitation of barrier layer, covering first electrodes down to substrate, alloying of substrate in open areas, precipitation of electric-conductive material above alloyed areas of substrate with forming of second parallel band electrodes, removal of barrier layer, near which vertical channels are left, passing downwards to non-alloyed areas of substrate between first and second electrodes, alloying of substrate in open areas of lower portion of channels, filling channels with barrier material, removal of first electrodes, during which gaps between second electrodes are left and substrate areas are opened between them, alloying of open areas of substrate in gaps, from which first electrodes were removed, removal of electric-conductive material in said gaps for restoration of first electrodes and thus making an electrode layer, containing first and second parallel band electrodes of practically even width, which are adjacent to alloyed substrate and separated from each other only by thin layer of barrier material, while, dependent on alloying admixtures, used during alloying stages, first electrodes form source or discharge electrodes, and second electrodes - respectively discharge or source electrodes of transistor structures, precipitation of insulating barrier layer above electrodes and separating barrier layers. Precipitation of electric-conductive material above barrier layer and forming in said electric-conductive material of shape of parallel band valve electrodes, directed transversely to source and discharge electrodes, thus receiving structures matrix for field transistors with very short channel length and arbitrarily large width of channel, determined by width of valve electrode.
EFFECT: ultra-short channel length of produced transistors.
11 cl, 17 dwg
FIELD: electronic engineering; high-power microwave transistors and small-scale integrated circuits built around them.
SUBSTANCE: proposed method for producing high-power microwave transistors includes formation of transistor-layout semiconductor wafer on face side, evaporation of metals, application and etching of insulators, electrolytic deposition of gold, formation of grooves on wafer face side beyond transistor layout for specifying transistor chip dimensions, thinning of semiconductor wafer, formation of grooves on wafer underside just under those on face side, formation of through holes for grounding transistor leads, formation of integrated heat sinks for transistor chips around integrated heat sink followed by dividing semiconductor wafer into transistor chips by chemical etching using integrated heat sinks of transistor chips as mask.
EFFECT: enhanced power output due to reduced thermal resistance, enhanced yield, and facilitated manufacture.
2 cl, 1 dwg, 1 tbl
SUBSTANCE: manufacturing method of microwave transistor with control electrode of T-shaped configuration of submicron length involves formation on the front side of semi-insulating semi-conductor plate with active layer of the specified structure of a pair of electrodes of transistor, which form ohmic contacts by means of lithographic, etching method and method of sputtering of metal or system of metals, formation of transistor channel by means of electronic lithography and etching, application of masking dielectric layer, formation in masking dielectric layer of submicron slot by means of electronic lithography and etching; at that, submicron slot is formed with variable cross section decreasing as to height from wide upper part adjacent to the head of the above control electrode to narrow lower part adjacent to transistor channel, formation of topology of the above control electrode by means of electronic lithography method, formation of the above control electrode in submicron slot by means of sputtering of metal or system of metals; at that, configuration of its base repeats configuration of submicron slot. During formation of submicron slot with variable cross section in masking dielectric layer, which decreases throughout its height, by means of electronic lithography and etching, the latter of masking dielectric layer is performed in one common production process in high-frequency plasma of hexafluoride of sulphur, oxygen and helium and discharge power of 8-10 W.
EFFECT: increasing output power and amplification factor, increasing reproducibility of the above output parametres and therefore yield ratio, simplifying and decreasing labour input for manufacturing process.
2 cl, 1 dwg, 1 tbl, 5 ex
SUBSTANCE: field transistor manufacturing method includes creation of source and drain contacts, active area identification, application of a dielectric film onto the contact layer surface, formation of a submicron chink in the dielectric film for the needs of subsequent operations of contact layer etching and application of gate metal through the resistance mask; immediately after the dielectric film application one performs lithography for opening windows in the dielectric at least one edge whereof coincides with the Schottky gates location in the transistor being manufactured; after the window opening a second dielectric layer is applied onto the whole of the surface with the resistance removed; then, by way of repeated lithography, windows in the resistance are created, surrounding the chinks formed between the two dielectrics; selective etching of the contact layer is performed with metal films sprayed on to form the gates.
EFFECT: simplification of formation of under-gate chinks sized below 100 nm in the dielectric.
SUBSTANCE: method for UHF high-power transistors manufacturing includes formation of transistor topology semiconductor substratum on the face side by electronic lithography and photolithography methods, metals spraying on, dielectrics application and etching, cathodic electrodeposition of gold, formation of preset size grooves on the face side outside the transistor topology, substrate thinning, formation of grounding through holes for the transistors source electrodes, formation of a common integrated heat sink, formation of a integrated heat sink for each transistor crystal, semiconductor substrate division into transistor crystals; one uses a semiconductor substrate with the preset structure of active layers having two stop layers with the preset distance between them, the stop layers ensuring minimum thermal resistance; the semiconductor substrate reverse side thinning is performed down to the stop-layer located close to such side; grounding through holes are formed immediately on the source electrodes with the common integrated heat sink thickness is set by the type of the transistor crystal subsequent mounting.
EFFECT: enhanced output capacity through reduction of thermal resistance, parasitic of the electric resistance in series and source electrodes grounding inductance; increased yield ratio, repeatability and functionalities extension.
4 cl, 1 dwg, 1 tbl
FIELD: electrical engineering.
SUBSTANCE: method for manufacture of a powerful UHF transistor includes formation of the topology of at least one transistor crystal on the semiconductor substrate face side, formation of the transistor electrodes, formation of at least one protective dielectric layer along the whole of the transistor crystal topology by way of plasma chemical application, the layer total length being 0.15-0.25 mcm, formation of the transistor crystal size by way of lithography and chemical etching processes. Prior to formation of the transistor crystal size, within the choke electrode area one performs local plasma chemical etching of the protective dielectric layer to a depth equal to the layer thickness; immediately after that one performs formation of protectively passivating dielectric layers of silicon nitride and diozide with thickness equal to 0.045-0.050 mm; plasma chemical application of the latter layers and the protective dielectric layer is performed in the same technological modes with plasma power equal to 300-350 W, during 30-35 sec and at a temperature of 150-250°C; during formation of the transistor crystal size ne performs chemical etching of the protectively passivating dielectric layers and the protective dielectric layer within the same technological cycle.
EFFECT: increased power output and augmentation ratio or powerful transistors with their long-term stability preservation.
4 cl, 1 dwg, 1 tbl
SUBSTANCE: semiconductor device comprises a thinned substrate of single-crystal silicon of p-type conductivity, oriented according to the plane (111), with a buffer layer from AlN on it, above which there is a heat conducting substrate in the form of a deposited layer of polycrystalline diamond with thickness equal to at least 0.1 mm, on the other side of the substrate there is an epitaxial structure of the semiconducting device on the basis of wide-zone III-nitrides, a source from AlGaN, a gate, a drain from AlGaN, ohmic contacts to the source and drain, a solder in the form of a layer including AuSn, a copper pedestal and a flange. At the same time between the source, gate and drain there is a layer of an insulating polycrystalline diamond.
EFFECT: higher reliability of a semiconducting device and increased service life, makes it possible to simplify manufacturing of a device with high value of heat release from an active part.
3 cl, 7 dwg
SUBSTANCE: invention relates to semiconductor technology. Proposed method comprises removal of photoresist from at least one surface of conducting layer with the help of the mix of chemical including first material of self-optimising monolayer and chemical to remove said photoresist. Thus self-optimising monolayer is deposited on at least one surface of said conducting ply. Semiconductor material is deposited on self-optimising monolayer applied on conducting layer without ozone cleaning of conducting layer.
EFFECT: simplified method.
15 cl, 4 dwg
SUBSTANCE: method for manufacture of powerful SHF transistor includes application of a solder layer to the flange, shaping of pedestal, application of a sublayer fixing the transistor crystal to the pedestal, formation of p-type conductivity oriented at the plane (111) at the base substrate of single-crystalline silicon and auxiliary epitaxial layers, application of the basic layer and buffer layer for growing of epitaxial structure of a semiconductor device based on wide-gap III-nitrides, application of heat conductive layer of CVD polycrystalline diamond to the basic layer, removal of the basic substrate with auxiliary epitaxial layers up to the basic layer, growing of heteroepitaxial structure based on wide-gap III-nitrides on the basic layer and formation of the source, gate and drain. The heat conductive layer of CVD polycrystalline diamond is used as a pedestal; nickel is implanted to its surficial region and annealed. Before formation of the source, gate and drain an additional layer of insulating polycrystalline diamond and additional layers of hafnium dioxide and aluminium oxide are deposited on top of the transistor crystal; the total thickness of the above layers is 1.0-4.0 nm.
EFFECT: invention allows increased heat removal from the active part of SHF-transistor and minimisation of gate current losses.
6 cl, 4 dwg
FIELD: electronic equipment.
SUBSTANCE: invention is intended to create discrete devices and microwave integrated circuits with the help of field-effect transistors. Method of making field-effect transistor, including creation of drain and source contacts on the contact layer of semiconductor structure and extraction of active region, metal or metal and dielectric mask is applied directly on the surface of contact layer, formation of submicron slot in the mask for further etching operations of contact layer etching and application of T-shaped gate metal through resist mask, after application of the first metal mask lithography for opening windows is carried out when one of the edges coincides with location of Schottky gates in manufactured transistor, and after opening windows the second metal or dielectric mask is applied on the whole surface, remove resist and by lithography create window in resist surrounding slits formed between two metals or between metal and dielectric, perform selective etching of contact layer, after which spray metal films to form T-shaped gates. As a result, edges of T-shaped gate heads on both sides resting on metal or metal and dielectric masks. Then, via selective etching the mask is removed from under the "wings" of T-shaped gate and from the surface of transistor active area. After that, the surface of transistor active area, containing drain, source contacts and Schottky gates, is coated with a passivating layer of dielectric so that under "wings" of T-shaped gate cavities are formed filled with vacuum or gas medium.
EFFECT: technical result is production of gated with length less than 100 nm, as well as reduced thickness of the metal mask and elimination of intermediate layer of dielectric placed between the active region surface and mask.
1 cl, 1 dwg