# The orthogonal signals generator

(57) Abstract:

The invention relates to automatic control and computer engineering and is intended to generate orthogonal signals. The aim of the invention is the extension of functionality by forming a complete system of quadratic signals. The generator includes a clock generator, a counter, six adders modulo two the first and second groups, eight integrators and fifteen multipliers. 2 Il. The invention relates to automatic control and computer science, and is intended to generate a new class orthogonalen quadratic signals.Generating signals other than binary, great attention is paid. So piecewise linear orthogonal signals (functions) allow for comparison with the binary higher accuracy of approximation of functions, and consequently, at a given fidelity function uses a smaller number of spectral coefficients. Piecewise quadratic signals (functions) offer even greater fidelity compared to the piecewise linear. Therefore, a complete orthogonal system of quadratic signals (functions) is gallaecia as follows.For this purpose let us take, for example, the system of the sixteen signals Walsh++ + + + + + + + + + + + + + + +

+ + + + + + + + - - - - - - - -

+ + + + - - - - + + + + - - - -

+ + + + - - - - - - - - + + + +

+ + - - + + - - + + - - + + - -

+ + - - + + - - - - + + - - + +

+ + - - - - + + + + - - - - + +

+ + - - - - + + - - + + + + - -

+ - + - + - + - + - + - + - + -

+ - + - + - + - - + - + - + - +

+ - + - - + - + + - + - - + - +

+ - - + + - - + + - - + + - - +

+ - + - - + - + - + - + + - + -

+ - - + + - - + - + + - - + + -

+ - - + - + + - + - - + - + + -

+ - - + - + + - - + + - + - - + Now replace the smallest discrete piecewise quadratic function with a positive value, if the signal discretes Walsh positive, and negative, if negative. Thus obtained quadratic system of signals (functions) is walkopedia, orthogonal, complete, and presented in Fig. 1.The aim of the invention is to enhance the functionality of the generator, such as the ability to generate a complete orthogonal system of quadratic signals. This objective is achieved in that the generator orthogonal quadratic signal containing a clock generator, a five digit counter, four modulo two of the first group, the first integrator and four multiplier p is cerned (i=) connected to inputs of the i-th modulo two of the first group, contains from second to eighth integrators, two modulo two of the second group and eleven tubes of the second group on the 2

^{to}-1 multipliers in 1K-th subgroup (=), and the output of the i-th modulo two of the first group is connected to the input of the first integrator, the output of which is connected to the first input of the first multiplier of the first group, a second input connected to the output of the i-th digit counter, and the output of the i-th multiplier of the first group is connected to the input (i+4) th integrator, the output of which is connected with the i-th generator output, the output of the (K+5)th integrator connected to the first inputs of all multipliers to nd subgroups of the second group, the outputs of all multipliers of the second group are from the fifth to the fifteenth outputs of the generator, the output of the j-th digit counter (j=) is connected with the second inputs of the j-th multipliers of all subgroups of the second group, the output of the first digit of the counter is connected with the first inputs of the first and second adders modulo two of the second group, the second inputs of which are connected respectively with the output of the third digit counter and the output of the second modulo two of the first group, the output of the third digit counter and the output of the second modulo two are connected respectively to the second inputs of the third and Savoy group connected to the second input of the third multiplier of the second subgroup and the fourth multiplier of the third subgroup of the second group, the second inputs of the fifth and seventh multipliers which are connected to the outputs of the first and second adders modulo two of the second group, respectively.Generator orthogonal quadratic signals intended for the formation of sixteen quadratic signals shown in Fig.1, shown in Fig. 2. It contains a clock generator 1, five digit binary counter 2, four adder 3 modulo two of the first group, the first integrator 4 and four multiplier 5 of the first group. Thus the output of the clock generator 1 is connected to the input of counter 2, the outputs of the i-th and (i+1)-th digits (i=) connected to inputs of the i-th adder 3 modulo two of the first group. In addition, the generator contains from second to eighth integrators 4, two adder 3 modulo two of the second group and eleven multipliers 5 of the second group on the 2

^{to}-1 multipliers 5 in the K-th (K=) subgroup. The yield of the i-th adder 3 modulo two of the first group is connected to the input of the i-th integrator 4, the output of which is connected to the first input of the first multiplier 5 of the first group, a second input connected to the output of the i-th digit of the counter 2, and the output of the i-th multiplier 5 of the first group connected to the input (i+4) th integrator 4, the output of which is connected with the i-m o is the group. The outputs of all multipliers 5 of the second group are from the fifth to the fifteenth outputs of the generator. The output of the j-th digit of the counter 2(j=) is connected to the second inputs of the j-th multipliers of all subgroups of the second group. The output of the first digit counter 2 is connected with the first inputs of the first and second adders 3 modulo two of the second group, the second inputs of which are connected respectively with the output of the third digit counter 2 and the output of the second adder 3 modulo two of the first group. The output of the third digit counter 2 and the output of the second adder 3 modulo two are connected respectively to the second inputs of the third and sixth multipliers 5 a third subgroup of the second group respectively. The output of the first adder 3 modulo two of the first group connected to the second input of the third multiplier 5 of the second subgroup and the fourth multiplier 5 of the third subgroup of the second group, the second inputs of the fifth and seventh tubes 5 which are connected to the outputs of the first and second adders 3 modulo two of the second group, respectively.The generator shown in Fig. 2, operates as follows. In the beginning of his work the clock pulses from the output of the clock generator 1 is fed to the input five digit binary counter 2, modulo two of the first group. From the outputs of the adders 3 modulo two of the first group shoot signals Walsh, subject integration for the first four integrators 4, the outputs of which are removed piecewise linear orthogonal signals which are fed to the first inputs of the sign multiplier products 5 of the first group, the second inputs of which are connected to the outputs of bits of the counter 2. Thus obtained signals are received on the fifth, sixth, seventh and eighth integrators 4, with output 6,7,9 and 13 which are removed orthogonal quadratic signals occupying the second, third, fifth and ninth position in Fig. 1. These signals, except the first, are the initial to obtain the missing quadratic signals, which are obtained by passing a landmark multiplier products 5 three subgroups of the second group of coded multiplier products. Respectively from exit 8 off signal, occupying the fourth position in Fig. 1, with the outputs 10, 11, 12 remove signals occupying the sixth, seventh and eighth position in Fig. 1. Similarly with outputs 14-20 remove signals occupying the tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth position in Fig. 1. Thirty two stroke generator back to its original state.From II quadratic signals. Therefore posed in the purpose of the invention is made in full. GENERATOR ORTHOGONAL SIGNAL containing a clock generator, a five digit counter, four modulo two of the first group, the first integrator and four multiplier of the first group and the output of the clock generator is connected to the input of the counter, the outputs of the i-th and (i + 1)-th digits which are connected with inputs of the i-th modulo two of the first group, characterized in that, to increase functionality by forming a complete system of quadratic signals, it contains from the second to the eighth integrators, two modulo two of the second group and eleven tubes of the second group on the 2

^{k}- 1 multipliers in the k-th subgroup and the output of the i-th modulo two of the first group is connected to the input of the first integrator, the output of which is connected to the first input of the first multiplier of the first group, a second input connected to the output of the i-th digit counter, and the output of the i-th multiplier of the first group is connected to the input (i + 4) th integrator, the output of which is connected with the i-th generator output, the output of the (k + 5)th integrator connected to the first inputs of all of the multipliers k-th subgroup of the second group, the outputs of all the mind is dine with the second inputs of the j - x multipliers of all subgroups of the second group, the output of the first digit of the counter is connected with the first inputs of the first and second adders modulo two of the second group, the second inputs of which are connected respectively with the output of the third digit counter and the output of the second modulo two of the first group, the output of the third digit counter and the output of the second modulo two of the first group are connected respectively to the second inputs of the third and sixth multipliers third subgroup of the second group, respectively, the output of the first modulo two of the first group connected to the second input of the third multiplier of the second subgroup and the fourth multiplier of the third subgroup of the second group, the second inputs of the fifth and seventh multipliers which are connected to the outputs of the first and second adders modulo two of the second group respectively.

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