The receiver majority compacted signals with parity

 

(57) Abstract:

The invention relates to computing and communications. Its use in multichannel systems transmit digital information can improve the accuracy of reception of the information by correcting single errors detected. The receiver contains N + 1 correlators 1 (N is the number of aggregated signals), N + 1 critical blocks 2, the generator channel signals 3, a multiplier 4 and the block of the even parity 5. With the introduction of the shift register 6, a key element 7, the pulse counter 8 and the N processing units 9 in the receiver is determined by the beat on which the error occurred, and the channel, where it happened, then correction of this error. 1 C.p. f-crystals, 2 Il.

The invention relates to computing and communication and can be used in multichannel systems transmit digital information.

Known receiver majority compacted signals (ICC), which administers the decoding and separation.

However, this receiver has, ceteris paribus, low reliability, because even a single error occurring in the transmission channel of the ICC, leads to the separation process errors compacted signals, allows you to identify any emerging odd errors, and containing N correlators, N computing units and generator channel signals, and the first inputs of correlators connected to the outputs of the generator channel signals, the second inputs of the correlators are connected, and the outputs of the correlators are connected to the inputs of the corresponding decision signals, in addition, put a block error detection and connected in series multiplier, additional correlator and more decisive block, the output of which is connected to the first input of the error detection, the remaining N input of which is connected to the output of the corresponding N computing units, the second input of the correlator is connected to the combined inputs of N correlators, and the inputs of the multiplier are connected to the outputs of the generator channel signals.

The disadvantages of this device is the inability to correct detected errors.

The purpose of this invention is to improve the reliability of reception of the information by correcting single errors detected.

In Fig.1 shows a structural circuit diagram of the receiver majority compacted signals with a check for the free period 1, N+1 critical blocks 2, the generator channel signals 3, a multiplier 4, block parity 5, the shift register 6, a key element 7, the pulse counter 8, N processing units 9.

The processing unit 9 includes accumulating adder modulo two 10, the first pulse counter 11, the first key element 12, a second pulse counter 13, the second key element 14, the shift register 15 and a controlled inverter 16.

The device operates as follows.

On the transmission side before the operation of the majority seal a sequence of M binary information symbols in each of the N channels is complemented (M+1)-th symbol of the even parity so that the sum modulo two of all M+1 characters was equal to "0". Receiver after the split operation channels on each step detects the presence of errors is odd difference in the set of characters contained in the N channels.

In case there are errors in any of the N channels, the output of block parity 5 is formed by the symbol "1", otherwise a "0".

The channel in which the error occurred is determined in the processing unit 9 by testing in each of the N channels of the array of M+1 incoming characters on parity. There ghadi N+1 correlators 1, of which N correlators to process information symbols and (N+1)-th correlator is optional. On the second inputs of the N correlators 1 serving channel signals from generator channel signals 3. To the second input of the (N+1)-th correlator 1 is the signal resulting from the multiplication of the channel signals. The multiplication operation is performed in the multiplier 4. Output computing unit 2 in each of the N+1 parallel processing channels is formed by the symbol "1", if the signal at the output of the corresponding correlator 1 positive polarity, or the symbol "0" in the opposite case. In block 5 is the sum modulo two signals from the output of all (N+1)-th computing blocks.

If there are errors in the odd number of the N information channels, the resulting sum will be equal to "1", if no error is "0". From the output of the block parity 5 signal is supplied to the shift register 6, performing a delay of a (M+1) tact required for synchronous operation of the processing unit 9. The counter 8 provides an account of incoming characters to the value of M and (M+1)-th also delivers a control signal to the second input of the key member 7 to the first input of which receives signals from the output of the register digallate correlation of single errors, occur in the majority compressed signal during its transmission over the communication channel and division. The information signal output from each of the N computing units 2 respectively supplied to the first input processing 9, where in parallel as it is input to the first 11 and second 13 meters, and the first inputs of the accumulating adder modulo two 10 and a key element 12. The adder 10 performs the summation modulo two blocks of M+1 received at its first input symbols, (M+1)-th of which is a check symbol. The result of the sum ("1" or "0") according to the output signal of the counter 11, performing account up to M+1 and after issuing a control signal to the second input of accumulating adder 10, enters the first inlet 14, in which the input signal ("1" or "0") output 7. The counter 13 performs the expense of incoming characters to the value of M and (M+1)-th stage delivers the control signal to the second input of the key element 12, by removing (M+1)-th step of the signal from further processing. The shift register 15 provides a delay on the M+1st time required for synchronous operation controlled inverter 16, at the first input of which receives the delayed signal from the output of the shift register 15. On vtoroe the symbol "1", the controlled inverter changes the information symbol ("1" or "0") on the opposite, thereby performing correction of errors in a given channel in a given quantum. If the outputs of the core element 14 corresponds to the symbol "0", then managed the inverter does not change the state of the input signal in a given quantum.

Thus, the proposed receiver majority compacted signals with parity provides the definition of the measure which the error occurred, specifies the channel where the error occurred, and performs the correction of single errors.

1. The RECEIVER MAJORITY COMPACTED SIGNALS WITH PARITY, containing the first - (N + 1)-th correlators (N is the number of aggregated signals), the first inputs of which are combined and the input of the receiver, generator channel signals, the first to N-th inputs of which are connected to second inputs respectively of the first to N-th correlators and the first to N-th inputs of the multiplier, the output of which is connected to the second input of the (N + 1)-th correlator, the output of each correlator is connected to the input of the eponymous final block, block parity, characterized in that, to improve the reliability of data reception by fixing Omni - The N-th processing units, the output of each of the first to N-th computing units connected to the first input of the same processing unit and a corresponding input power parity, the output (N + 1)-th of the decision making unit is connected to the (N + 1)-th input unit of parity, the output of which is connected to the input of the shift register, the output of which is connected to the information input key element and the input of the pulse counter, the output of which is connected with the control input of the key element, the output of which is connected to the second inputs of the first to N-th processing units, the outputs are the same outputs of the receiver.

2. The receiver under item 1, characterized in that the processing unit contains the accumulating adder modulo two, the first and second core elements, the shift register controlled inverter, the first and second counters, inputs are combined with the information input of the first key element and the first input of the modulo two and are the first input unit, the outputs of the first and second pulse counters connected respectively to the control input of the first key element and the second input of the modulo two, the outputs are connected respectively to the input register add the waters of the shift register and the second key element is connected respectively to the information and the control inputs of the controlled inverter, the output which is the output of the block.

 

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