The device for decoding group codes

 

(57) Abstract:

The invention relates to a device for the transmission of discrete data and can be used in systems of automatic locomotive alarm, Autolock and other devices of railway automatics. The purpose of the invention - raising awareness of the device by simultaneously decoding two channels. To achieve this, the device containing the register 1 shift, unit 4 memory entered conversion unit 5, the register 7, the first 10 and second 11 blocks comparison, the first 12 and second 13 elements AND IS NOT, the first 15 and second 16 D-triggers, the inverter 17, the first 18 and second 19 buffer registers, the selector 21 of the frame synchronization signal. Conversion unit 5 includes first, second four-bit binary counters and the element I. the Selector 21 of the frame synchronization signal contains a D-flip-flop, a four-digit binary counter, chetyrehhodovogo element AND - NOT, tokodai element and the inverter. 2 C.p. f-crystals, 3 ill., table 1.

The invention relates to a device for the transmission of discrete data and can be used in systems of automatic locomotive alarm, Autolock and other devices of railway automatics and contains a shift register, the pulse generator, a storage unit, element, OR an additional source of pulses.

A disadvantage of this device is the low information content, since the decoding is performed only on one channel.

The purpose of the invention - raising awareness of the device by simultaneously decoding two channels.

In Fig.1 is a block diagram of the device of Fig.2 is an example implementation of the selector frame synchronization signal of Fig.3 is an example of executing update block.

The device comprises (Fig.1) the first shift register 1, clock 2, the first media entrance 3, block 4 memory update unit 5, engraved 6, the second shift register 7, the second information input 8 input 9 installation in the initial state, the blocks 10, 11 comparisons, elements, AND NOT 12, 13, a bus 14, the zero potential of the D-flip 15, 16, an inverter 17, the buffer registers 18, 19, the positive power bus 20, the selector 21 of the frame synchronization signal.

The selector 21 of the frame synchronization signal (Fig.2) contains a D-flip-flop 22, a four-digit binary counter 23, chetyrehhodovogo element 24 AND, tokodai element (resistor) 25 and an inverter 26.

Update block 5 (Fig.3) contains the following way.

At a clock input 2 register 1 receives the signal of frequency Fm, the period of this signal is equal to the duration of elementary bits of the sequence are transmitted to the inputs 3 and 8 registers 1 and 7. Assume that the inputs 3 and 8 receives the eight-bit code group code (in particular, code, Bauer or code of Amiga), containing four information bits and four check bits. Falling edge of the clock pulse time falls in the middle of elementary bits. Code synchronized on the transmission side with respect to each other, so the beginning and end of the code combinations of two subchannels 3 and 8 are the same. It is assumed that the code combination at the input of 8, have priority over code combinations at the input 3, i.e., to perform decoding on input 3 is permitted only in case of correct decoding for input 8. The device is intended for use in systems with cyclic transmission of constant information, a change which occurs no more often than one time every five-ten time intervals of transmission of one code combination, but also from different transmitters, switches which are random in nature, in cichecki locomotive alarm.

First, consider the situation when a constant is passed information from one transmitter. Then in the worst case for eight clock cycles (relative to the trailing edge) of the Fm signal at the input 2 to outputs of the registers 1 and 7, will be installed in parallel code received code combination. When four informatsionnnyh discharges may sixteen permitted code combinations stored in the storage unit 4. Counter 5 it is at 1024*Fm, which provides for a time shift of one bit of information in registers 1 and 7 fourfold enumeration of all permitted code combinations from the storage unit 4. Received code combinations of the outputs of the registers 1 and 7 are received in the first 10 and second 11 blocks comparison, where continuously compared with the set of permitted code combinations coming in parallel with the outputs of the storage unit 4 on the second inputs of the first 10 and second 11 units of comparison. At the time of coincidence of the received code with one of the permitted output of the Comparer you receive a single pulse. When this information is received at the input 8 has a higher priority than information on input 3, so the signal match output unit 10 to the output a element AND-NOT 13, D-flip-flop 16 and the block selection signal frame synchronization 21. As for the two subchannels information in General different, the points of agreement permitted code combinations on different subchannels are not the same, so to remember the fact of the coincidence device introduced triggers 15 and 16, the S-inputs of which are connected to the outputs of the elements AND NOT 12, 13. A zero signal at the output of element AND-NOT 12 trigger 16 is set in one state, in which it will be until the arrival of the next front of the clock pulse Fm, arriving at the s-input of the trigger 16 and recording it with zero D-input connected to the shared bus. Over the time the trigger 16 in a single state is a comparison of the code received over the first subchannel 2, with the permitted code combination, and the trigger 15 will be written to the logical unit. When the logical unit at the output of the trigger 15 is correct for the received information, so this signal writes into the buffer registers 18 and 19, the information bits corresponding code combinations (in this case, four digits; in the General case, if further processing is conducted in a redundant encoding, registers Zap is s false pulse comparison on the outputs of the elements AND NOT 12, 13, called logical competitions in blocks 10, 11, 4, to the inputs of elements AND NOT 12, 13 served the gate signal of a single level of exit 14 (STB) unit 5, and the fronts of the signal do not coincide with the moments of change of signals at the inputs 5.1-5.4 unit 5. The input 9 of the decoding device is designed for installation in the initial state of all blocks of the device. A single pulse on this input sets the blocks 1, 5, 7, 15, and 16 in the zero state, the block 21 is in one state. When this blocks 15, 16 and 21 are set to the zero level signals from the output of the inverter 17.

Update block 5 (Fig.3) divides the frequency of 1024*Fm with two four-bit binary counter 29 and 27. The signals from the two high-order bits of the counter 29 are fed to the inputs of the element And 28, the output of which 14 is the gate output unit 5.

Block allocation of the frame synchronization signal 21 (Fig.2) is designed to generate an enable signal to the signal comparison code combinations at the output of element AND-NOT 13.

This unit works as follows.

Upon receipt of the signal initial setup of the zero level in the four-digit binary counter 23 is written unit in all the bits on the output element of the group of clock pulses Fm output of the block With the input of the counter 23. At the output of inverter 26 is formed of a single signal, which allows the signal comparison output unit 11 on the S-input of the trigger 16 through an AND-NOT 13. Once the signal comparison will set the trigger 16 in one state, the counter 23 is set to the zero state, causing the output element AND-NOT 24 is formed of a single signal, which permit the passage of clock pulses Fm-input binary counter 23. At the output of inverter 26 is formed a signal of logical zero, which prohibits the formation of a signal comparison code combinations at the input 8 of the device. The enable signal output unit 21 will appear only after sixteen clock pulses Fm. This is done in order to exclude false acceptance code combinations obtained when changing information in the communication channel, when a part of bits of the code refers to the old information, and some discharges to new information. For example, the transmitted code combination code Bauer 00011111, which has changed to a code combination 11100000. The latter is cyclically repeated at least five times. Because bitwise shift information in the register 7, the pulse of the comparison is generated at the output of the unit 11 included four is that a true pulse of the comparison, the corresponding code combination 11100000.

On this basis it was possible to generate the enable signal output unit 21 after eight clock pulses. However, it is possible accidental change, for example, combination 01001010 on 00101100 on the fifth bit, then on the ninth clock pulse appears false pulse comparison, the corresponding code combination 10011000, which at this time is not transmitted. In the General case in this situation, a false pulse comparison may appear in number of clock cycles from 8 to 15 after receiving the previous pulse comparison.

Thus, the block 21 eliminates a false admission, is not transmitted in the moment permitted code combinations.

The block 4 may be made in the form of combinational circuits based on the following ratios (code Bauer):

Y7=A3; Y6=A2; Y5=A1; Y4=A0;

Y3=A1+A2+A3;

Y2=A0+A2+A3;

Y1=A0+A1+A3;

Y0=A0+A1+A2,

for the implementation of these logical expressions will require two buildings chip type CLP, containing in its composition with the XOR, and one inverter, for example, chip KLN.

1. A DEVICE FOR DECODING a GROUP of CODES containing the first re the new inputs of the device, and the memory block, wherein, with the aim of increasing the explanatory power of the device, it introduced a second shift register, update block, blocks comparison, the selector signal frame synchronization, D-trigger buffer registers, elements, AND IS NOT, the inverter, the positive power bus and the bus is zero potential, the first outputs of the scaler unit connected to respective address inputs of the memory block, the information outputs of which are connected with the first information input of the first and second units of comparison and information inputs of the first and second buffer registers, the outputs of which are the outputs of the device, the outputs of the first and second shift registers connected to respective second information inputs respectively of the first and second units of comparison, the outputs of which are connected with the first inputs respectively of the first and second elements AND whose output is connected to the S inputs respectively of the first and second D-flip-flops, D-inputs are connected to the bus zero potential, the output of the inverter is connected with the input set to "1" of the selector signal frame synchronization and R-inputs of the first and second D-flip-flops, the output of the first D-flip-flop is connected to the input of synchro to the input of the initial setup of the selector frame synchronization pulses, the output of which is connected to a second input of the second element AND IS NOT, the third input element and NOT engraved selector pulse cycle are combined and connected to the second output of the conversion unit, the information input selector signal frame synchronization, C-inputs of the D-flip-flops and the clock input of the second shift register is connected to the clock input of the device, the power input selector signal frame synchronization is connected to the positive power bus, the inverter input and inputs the initial installation of update of the block and shift registers are input initial setup of the device, the information input of the second shift register and the input of the synchronization update block are, respectively, the second information input and synchronization input device.

2. The device according to p. 1, wherein the update unit is made on the counters and the element And the outputs of the last bits of the first counter connected respectively with the synchronization input of the second counter and the first input element And a second input element, And the synchronization input of the first counter and the input setup in the initial state of the first and second counters are respectively the respectively first and second outputs of the block.

3. The device under item 1, characterized in that the selector signal frame synchronization is performed on the D-trigger, counter, element, AND IS NOT, the inverter and tacosode element, the output of which is connected to the S-input of D-flip-flop and the input parallel load counter, the outputs of the bits which are connected to corresponding inputs of elements AND IS NOT, the output of which is connected to the R-input of D-flip-flop and the input of the inverter whose output is the output of the selector, the output of D-flip-flop is connected to synchronator counter, the enable input of the load and the input set to the initial state which are respectively the input set to the state "1" and input the initial installation of the selector, the input dakotadashako element and C - and D-inputs of the D flip-flop are respectively the input power, synchronator and information input selector.

 

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