A device for determining the start of the data block in the external memory

 

(57) Abstract:

The invention relates to computing, and in particular to an external storage device (DDT), and can be used in controllers external storage devices. The purpose of the invention is the simplification of the device and improving the reliability of determining the beginning of the data block. The simplification is achieved by the transition from parallel processing (r) markers to the serial. When the length of the shift register is reduced to (r) times the detection scheme markers degenerates into a much simpler scheme selector code. Improving the reliability of determining the beginning of the block of data is achieved by introducing into the device blocks and links, allowing you to use the encoding of the names of the markers of error-correcting code, so that concatenate names (r) neighboring markers forms a code word. 4 Il.

The invention relates to computing, and in particular to an external storage device (DDT), and can be used in controllers external storage devices.

A device that determines the beginning of the data block in the external memory computers [1] and contains a demodulator, counter, six RS-triggers, eight members, seven of the items OR the item is NOT.

The disadvantage is owner errors in data read.

A device that determines the beginning of the data block in the external memory computers [2] and contains the selector signals, shift registers, counters, two thresholds, unit, trigger, elements, items, OR items NOT.

The drawback is the large amount of equipment, increasing in proportion to the number of tokens in the header block.

The closest in technical essence to the invention is a device which determines the beginning of the data block in the external memory computers [3] and contains a shift register, a decoder channel code detect circuit markers, the counter, the code Converter. The device determines the start of the data block detecting any sequence r markers from a variety of markers header block.

The disadvantages of the considered devices are a large amount of equipment, increasing in proportion to the number of allocated consecutive markers in the header block, and insufficient reliability of determining the beginning of the data block.

The purpose of the invention is the simplification of the device by reducing the bit shift register circuit and the detection sequence markers and increased reliability definition start of block data, contains a shift register, a decoder channel code, the first selector code, the first counter, the code Converter, the D-input shift register receives read from the media information, With inputs shift register, and a first counter and a second input of the first selector code receives the clock pulses, the second outputs of the shift register is connected to the first inputs of the first selector code is entered, the register block comparison of codes, the second selector code, the second counter, the first and second switches, the first and second elements And the EXCLUSIVE OR element, the element OR NOT, the first outputs of the shift register are connected to the inputs of the decoder channel code, the second outputs of the decoder channel code is connected to the first inputs of the block comparison of codes and the second inputs of the first switch, the output of the first selector code connected to the first input of the first element And the second input of the second switch, the second input of the element OR NOT, the input of the Doa second counter, the output of the Comparer codes connected to the second input of the first element And the output of the first element And connected to the first input of the EXCLUSIVE OR element, the outputs of the first switch is connected to D-input register, output register connected to the input pre of the first switch and the second input unit of the comparing, the output of the second switch is connected to the input register and the R-input of the first counter, the output of the first counter connected to the first input of the second switch, the second input of the second element And the second input of the EXCLUSIVE OR element, the first input of the element OR NOT, the output of the second selector code connected to the first input of the second element And the output of the EXCLUSIVE OR element connected to the control input mode reception/the expense of a second counter, the output of the element OR NOT connected to the input of a second counter, a second counter connected to the control inputs of the first and second switches, to the third inputs of the second element And the element OR NOT, to the inputs of D1-Dv-1a second counter signals are logic zero, the R-input of the second counter signal RESET, the first outputs of the decoder channel code information output device, the output of the second element And an output device indicating the beginning of the data block.

Additionally there is a second counter, the second element, And, XOR, OR NOT allow you to switch from parallel highlight any sequence of r tokens in a row, when they are in the shift register to the serial. Ave is in, the first scheme And lead to the degeneration scheme tokens prototype in a much more simple the first selector code.

Added register, switches and the appropriate inclusion of the code Converter allows you to use to encode the name of the token error-correcting code, which reduces the probability of an incorrect identification of the beginning of the block.

The result of a comparative analysis of the proposed technical solution and similar solutions found in the patent and technical literature, it was concluded that there were significant differences among the proposed solutions.

In Fig. 1 shows a diagram of the device for determining the start of the data block (WANBT in the external memory of the computer of Fig. 2 - shift register and decoder channel code IMF; Fig. 3 is a timing diagram of operation of WANBT if there are errors in the token sequence; Fig. 4 is a graph explaining the operation of the meter markers (second counter).

A device for determining the start of the data block (Fig. 1) contains a shift register 1, the channel decoder code 2, the first selector code 3, the first counter 4, the code Converter 5, case 6, the block comparison code (BSC) 7, wtnt EXCLUSIVE OR 14, the element OR NOT 15. In Fig. 1 and 2 the numbers indicate the first and second outputs of the shift register 16 and 17, first and second outputs of the decoder channel code 18 and 19, the signals of logical zeros - 20.

On the figures the following symbols are used signals: DI- input data in serial form; Do- output in parallel form; T - heartbeats; CCA - signal is active; KS codes at the inputs of the block comparison codes coincided; SDF - final state of the register; PSB - transfer bit counter (first counter); ND - start data; FSS - final state of the counter markers (second counter).

In addition, in the description, the following notation is used:

k is the number of tokens in the token sequence;

r - the number of allocated consecutive markers, at which the decision about the location of the header data;

v is the smallest integer greater than or equal to log2(r+1);

l is the length of the marker (in bits channel code);

w is the smallest integer greater than or equal to log21;

p is the length of the clock (in bits channel code);

q - bit code name token;

m - bus width Do;

n - length code words, pouch elements in the block;

i- the name of the i-th token.

In Fig. 1 and 2 the first 16 outputs shift register 1 are l-bit; the second outputs 17 shift register 1 - p-bit; the second yields (19) decoder channel code 2, the outputs of the first switch 10, the register 6 and the code Converter 5 - q-bit; the first outputs (18) of the channel decoder code 2 - m-bit; signal logic zero 20-(v-1)-bit.

The shift register 1 is the l-bit; the first counter 4 - w-bit (with multiplier l); Registrar 6 - q-bit; a second counter 9 - v-bit (with a conversion factor r+1).

The channel decoder code 2 represents a combinational logic circuit l inputs and m outputs (signals of the second outputs of the decoder are a subset of the signals of the first output) and can be implemented in ROM, PLA, or discrete logic components. When using channel code IMF decoder degenerates into a set of jumpers (see Fig. 2). While the 18 outputs of the decoder are connected with all its odd inputs, outputs 19 are connected with q Junior odd inputs.

The 4 counters (counting mode and reset) and 9 (accounts and receiving information), register 1 triggered by a positive is to control the intake/score served logical zero; otherwise, the counter 9 information is loaded with D-inputs. The input R of the counter 9 is asynchronous. In the register 6 is loaded information from the D-inputs on the negative edge of the signal applied on input.

The output of counter 4 (PSB) is a logical unit when the counter is at l-1, and the signal at its C-input is equal to zero. At the output of the counter 9 (FSS) is a logical unit when the counter is in state r.

The outputs of the switches 10, 11 signals with their second inputs (19 and SSA, respectively) in the presence of a logical zero on the control inputs, otherwise at their outputs signals with their first inputs.

At the output of the Comparer code 7 is formed logical unit only in case of equality codes on its inputs, the output of the selector code 3 is formed logical unit only in the case of on his first inputs of a given code combination and the logic zero at the second input (gate), the second selector code 8 works the same as the first but without Gating. The Comparer codes 7 and selectors codes 3, 8 can be implemented as combinational circuits in a known manner on the ROM, PLA, or discrete logic components.

To determine the start of the data block on the storage medium immediately before the data bytes are written to the header (see Fig. 3). The header contains the region of pulses required to establish synchronization of the PLL (Fig. 3 the area marked: SYNC) and a sequence of k l-bit token - pointers start of the block. Each token contains the p-bit of the synchronization signal SS and the q-bit namei(in bits channel IMF code width code name equals 2q).

As the clock uses a sequence of bits of the channel code that is different from any combination of bits of the channel code, recorded on the media.

Each token is from the beginning of the data block at a distance defined by a name token. Concatenate code name r neighboring markersi, ...,i-r+1forms n-bit word block error-correcting code with minimum code distance d. Thus any two sequences of r markers, including overlapping, differ from each other not less than d digits. This reduces the probability of incorrect detection of the beginning of the block with the defeat of the S="ptx2">

Error-correcting code is chosen so that for given k and n to maximize the minimum code distance d. An example of such a code for r=2 is shown below.

Consider the processing of the header of the data block WANBT in accordance with Fig. 3. In WANBT can be divided into two stages: first, the allocation of r tokens in a row, the second is the formation time delay from the time of allocation of the r-th token before the start of the data block. In Fig. 3 these stages correspond to the time intervals And the time interval from when the zero of the second counter signal RESET in the field SYNC up to the time of transition of the second counter 9 in the state number r; the time interval from the moment of fixation r markers in a row until the formation of the pulse start of the data block.

The process of allocating consecutive r markers from the received WANBT information presented in graph form in Fig. 4. Vertex numbered from 0 to r, the display state of the counter 9, count allocated consecutive markers. The transition from one state to another occurs when certain conditions are met (a, b, c, d), which is the logical functions of the signals SSA, PSB, KS (see Fig. 4). The signal RESETS the counter of any the state of the counter will be as long until you've selected at least one synchronization signal marker. The transition from the zero state of the counter in the unit occurs in the case of detection of the sync marker regardless of its name. The transition from i-th to i+1 (i = 1, 2, 3, ..., r-1) occurs if the next selected marker is detected after exactly l bits of the channel code from the beginning of the previous repetition period markers - l) and his name is what you expected. Otherwise, there is a transition in the zero state, if the next sync signal is not detected at a distance less or equal to l bits from the beginning of the previous, or in one state, if the code name of the next selected token does not match the expected or the synchronization signal detected at a distance smaller than l bits from the beginning of the synchronization signal of the previous token.

The work of WANBT in the process of allocation of r tokens in a row explains Fig. 3. In Fig. 3 shows an example of processing WANBT header block with three errored marker: second marker errored name, the fourth signal, the last and name, and the synchronization signal.

WANBT works in the interval As follows.

The RESET signal sets to zero the second counter 9. Nolivos and SSA from the first or second input element OR NOT 15 at its output; the third input element And 13, closing it; and on the control inputs of the switches 10 and 11, resulting in the outputs of these switches are logically connected with the second of their inputs.

In the field SYNC pulse of the transfer counter 4 PSB is fed to the input of the counter 9 through the open low signal levels FSS and FSA, the element OR NOT 15. The counter 9 is loaded zero code with the D-inputs as its input V receives a single potential obtained by adding modulo two to the EXCLUSIVE OR element 14 active signal PSB and passive signal obtained from the output of a closed low-level signal SSA, item, And 12. The procedure corresponds to the column (Fig. 4) the transition from vertex 0 to vertex 0 by the condition.

Detecting the first synchronization signal token in the sequence of bits of the channel code, the selector 3 produces a signal SSA. The content of the counter 9 is incremented by front signal SSA received through the element OR NOT input From the counter as input to the mode control counter V receives a low level signal obtained by adding modulo two to the EXCLUSIVE OR element 14 low level signal PSB and the low level output signal, the closed passionem will be copied into the register 6 to the front of the pulse SSA, which is fed to the input C of the register 6 through the switch 11. The clock SSA flowing through the switch 11 to the input R of the counter 4 is set this counter to zero.

Since the initial state of the register 6 is not defined and PSB to detection of the first pulse SSA is not tied to the title, also considered the following situation:

- at the moment of detection of the first clock signals PSB and COP have high levels;

- at the moment of detection of the first clock signal CS has a high level, and PSB - low. In the first case, the content of the counter 9 is incremented, the second - in counter 9 is written to the unit. All three discussed the situation on the graph correspond to the transition from vertex 0 to vertex 1 by condition d.

The code Converter 5 converts the codek-1coming to its inputs from the outputs of the register 6, in the codek-2that comes to the second input of the block comparison codes. At the time of selection by the selector 3 clock of the second token to the first inputs of the block comparison codes will be errored code name of the marker (Xk-2) from the second outputs of the decoder 2. Passive signal CS output capacitor 7, when the second input element And 12, closes it is lementa EXCLUSIVE OR receives an active signal PSB output of the counter 4. The counter 9 is set to one edge of the signal CAS, at the input To the meter through the element OR NOT 15, so as to control input mode V filed logical unit from the output of the EXCLUSIVE OR element, and the inputs of the parallel load Do-Dv-1served code units. Code X will be copied into the register 6 to the front of the pulse SSA. Procedure on the graph corresponds to a transition from vertex 1 to vertex 1 by condition b.

The code Converter 5 converts the code X code X1 (X1k-3), which is supplied to the second inputs of the block comparison codes. At the time of selection by the selector 3 clock of the third marker on the first input unit of the comparing code will be the code name of the third tokenk-3second outputs of the decoder 2. Passive signal CS output capacitor 7, when the second input element And 12, closes it. The output signal of the closed element And 12 is supplied to the first input of the EXCLUSIVE OR element 14. To the second input of the EXCLUSIVE OR element receives an active signal PSB output of the counter 4. The counter 9 is set to one edge of the signal CAS, so as to control input mode V filed logical unit, and inputs the parallel load Do-Dv-1is supplied to the s 1 in the top 1 by condition b.

Consider the reaction of WANBT on the token struck by the clock. Errored code synchronization signal from the second output register 1 is supplied to the first inputs of the selector 3 during the formation of the signal transfer PSB from the first counter 4. Passive signal output from the selector 3, when the first input element And 12, closes it. The counter 9 is set to zero at the front of the signal PSB at the input of the counter 9 through the element OR NOT 15, as at the time of formation of the transfer counter 4 active signal at the output of the EXCLUSIVE OR element 14 (logical zero at the first input of the EXCLUSIVE OR element, and a logical unit is at its second input). Setting to zero of the counter 9 will be going through the entries in the counter code of zero from its parallel inputs, boot Do-Dv-1. Procedure on the graph corresponds to a transition from vertex 1 to vertex 0 by condition a.

Selecting the fifth signal token from the stream bit channel code, the selector 3 produces a signal SSA. Passive signal CS output capacitor 7 (on the input capacitor filed codek-5second outputs of the decoder 2, and the second input is fed codek-4with the outputs of the code Converter), when the second input element And 12, zakrya the second input of the EXCLUSIVE OR element receives an active signal PSB output of the counter 4, the counter 9 is set to one edge of the signal CAS, at the input To the meter through the element OR NOT 15, so as to control input mode V filed logical unit from the output of the EXCLUSIVE OR element, and the inputs of the parallel load Do-Dv-1served code units. If the second input of the EXCLUSIVE OR element at the time of the selection signal SAA enters passive signal PSB output of counter 4 (in case of violation of synchronization selector after the second defect), the content of the counter 9 (previously set to zero) will increase by one edge of the signal CAS, so as to control input mode V filed logical zero from the output of the EXCLUSIVE OR element. On the front of the pulse SSA codek-5will be copied into the register 6, and the counter 4 is reset to zero. Procedure on the graph corresponds to a transition from vertex 0 to vertex 1 by condition d.

At the time of selection by the selector 3 clock sixth token on the input unit of the comparing code will be the code name of the sixth tokenk-6second outputs of the decoder 2. The code Converter 5 converts the codek-5coming to its inputs from the outputs of the register 6, in the codek-6that comes to the second input of ignal SSA through the open item And 12 is supplied to the first input of the EXCLUSIVE OR element 14. To the second input of the EXCLUSIVE OR element receives an active signal PSB output of the counter 4. The content of the counter 9 is incremented by front signal SSA received at the input To the meter through the element OR NOT 15, so as to control input mode V filed logical zero from the output of the EXCLUSIVE OR element. Code k-6will be copied into the register 6 to the front of the pulse SSA. Procedure on the graph corresponds to a transition from vertex 1 to vertex 2 in condition C.

Similarly, WANBT will react to the seventh, eighth, .., r+4 marker. The content of the counter 9 is incremented at the front of the signal CAS, and the code name of the last selected marker will be overwritten in the register 6. On the graph, this corresponds to successive transitions in condition with in peaks 3, 4, ..., r.

When the counter reaches 9 status r completes the first stage of WANBT - allocation of r tokens in a row (the interval a of Fig. 3), and starts the second phase - forming time delay (interval In Fig. 3).

Each token is from the beginning of the data block at a distance defined by a name token. In register 6 at the end of the interval And the code will be stored name of the last marker of the selected poitra 6 in the interval In each time through the l-bit channel code (the repetition period markers - l) according to the law of repetition of the names of the markers to obtain the final stateo.

Works of WANBT in the interval In the following way.

When the counter reaches 9 status r at its output the signal SIF. A single potential at the output of the counter 9 is supplied: to the third input element OR NOT 15, preventing the passage through the element OR NOT 15 to the input of counter 9 signals SSA and PSB; on the third input element And 13, opening it; and on the control inputs of the switches 10 and 11, resulting in the outputs of these switches are logically connected with the first of their inputs. The signal FSS is active as long as the counter 9 will not be set to zero by the signal RESET.

In the interval IN WANBT does not respond to the input sequence of data. The counter 4 is reset at the end of the pulse PSB flowing through the switch 11, to the input R of the counter 4. The signal transfer counter 4 through the switch 11 is fed to the input of the register 6, causing a write to this register code following the name of the marker obtained by the conversion unit 5 previously stored in the register 6 of the code.

At the output of the selector code 8 is formed by a logical unit in case of presence at its inputs the code name after the TA And 13.

Signal ND, signaling the beginning of a data block that is generated at the output of the element And 13 of the signal SDF by its Gating pulse transfer counter 4.

The controller DDT, which includes the proposed device, receiving a signal ND, starts receiving a block of data bus Do.

Consider an example implementation of a device for r = 2, k = 8, n = 8 and the channel code of the IMF. The synchronization signal is a sequence of eight channel bits type 01000001. This device uses two token sequences: the first to determine the start block address information is recorded separately; the second to determine the start of a block of user data. For coding the names of the markers are perfectly related class of the extended Hamming code. Code word form two chains (for two marker sequences), in which the second half of the code words is the first half of the next code word. All words related class in the table.

Minimum code distance between two words in the related class is 4. Thus, if properly reading the signals wrong definition start of block due to distortion of the brand names the fact that case 1 can be made two circuits of the type TO 555 IR, register 6 on the chip TO 555 TM9, the counter 4 on the chip TO 555 IE, the counter 9 on the chip TO 555 IE, the selector 3 on the chip TO 556 RT, blocks BSC, PC, a selector 8, the switches 10 and 11, the elements 12 And 13, OR 15, EXCLUSIVE OR 14 can be performed on the chip TO 556 RT.

The introduction of a small number of additional simple blocks reduces the length of the shift register in r times. In this scheme tokens degenerates into a much simpler scheme selector code.

Estimate the increase in volume of the prototype and the claimed device with increasing r. In the prototype is directly proportional to r increases the capacity (and hence the number of trigger elements) shift register 1: = lr. And l, as a rule, quite a large amount. In the prototype is also directly proportional to r increases the number of inputs schema tokens, which leads to a proportional increase in the number of logic elements in the schema.

In the inventive device with increasing r increases only bit counter 9, and in logarithmic scale: = =log2(r+1).

Obviously, because the hardware prototype is growing significantly faster than the volume of oborudovaniya hardware prototype. We define this value of r in the case of using the header of the data block shown in the example.

The case r = 1 is not of interest: this device [3] and the proposed device degenerate in the device [1]. Compare the amount of hardware of the prototype and of the inventive device when r = 2.

In the device, enter the following additional equipment: 4-bit register 6, block compare two 4-bit codes 7, the selector 4-bit code 8, 2-bit counter 9, a 4-bit switch two input 10, the bit switch two input 11, the two elements 12 And 13, the EXCLUSIVE OR element 14, the element OR NOT 15.

At the same time, the bit shift register 1 is reduced from 32 bits to 16 bits. Represnet counter 4 is reduced from 7 digits to 4. Schema selection marker prototype, containing a single selector code 17 inputs (one input - gate), seven selectors code 16 inputs, scheme OR 7 inputs, scheme, And for the two inputs, in the inventive device remains the same selector code 9 inputs (one input - Gating).

Express the difference of the volumes of the hardware prototype and the inventive device in the form of a number of elementary logical elements. The inversion of signalof code the number and width of which in the prototype is significantly greater than in the inventive device.

The introduction of the counter 9 with regard to the more complex it organization roughly equivalent to reducing the capacity of the counter 4. The introduction of a 4-bit register 6, and volume reduction equipment shift register 1 to 16 triggers results in a simplification of the device 12 D-flip-flops operating on the front, which is equivalent to 60 items AND NOT on 2 inputs and 12 elements AND IS NOT 3.

The Comparer 7 contains 12 items AND NOT on two inputs and one on the 4 inputs. The selector contains 8 item AND NOT on the 4 inputs. The switch 10 contains 12 items AND NOT for 2 entries. The switch 11 contains 3 item AND NOT on the 2 inputs. The elements 12 and 13 can be implemented by means of the elements AND IS NOT, respectively, at 2 and 3 inputs. The EXCLUSIVE OR element 14 can be implemented using 3 elements AND NOT on the two inputs. The element OR NOT 15 can be implemented using the element AND NOT on the 3 inputs. Ultimately introduced additional units (except for units 4 and 9) complicate the inventive device 31 of the element AND NOT on the two inputs, 2 element 3 inputs, 2 item 4.

By reducing schemes tokens prototype device Oprah, the sample, and r=2 the proposed device is simplified by about 29 items AND NOT on 2 inputs, 10 items-NOT on 3 inputs, 6 elements AND NOT on the 16 inputs. With increasing r the simplification of the device compared to the prototype will be much more.

Provided in the device use to encode the name of the token error correcting code so that concatenate any r adjacent markers is the word error correcting code that allows you to minimize the probability of incorrect detection of the beginning of the data block in case of defeat by the error token names.

The above encoding can be used in the case of the use of any channel code, with the words of constant length.

A DEVICE FOR DETERMINING the START of the DATA BLOCK IN the EXTERNAL MEMORY containing the shift register, the information whose input is connected to the bus input serial data, engraved - bus clock pulses, and the second outputs to the first inputs of the first selector code, the first counter, engraved which is connected to the bus clock pulses, the code Converter, the decoder channel code, the bus output parallel data, characterized in that order Opredelenie register, the output of which is connected to the input of the code Converter, the second selector codes, the second element And the first input and the beginning of the data bus, the bus reset, bus logic zero, serially concatenated block code compares the first and second inputs which are connected respectively to the second output of the channel decoder code and the output of the code Converter, the first element And the other input of which is connected to the output of the first selector code, and the EXCLUSIVE OR element, another input of which is connected to the second input of the second element And to the output of the transfer of the first counter, two switches, the element OR NOT and the second Svetsik, the output of which is connected to the third input element OR NOT, to a third input of the second element And the control inputs of the first and second switches, the outputs of which are connected respectively with the D-input and C input register connected to the reset input of the first counter, the first and second inputs of the first switch are connected respectively with the output of the code Converter and the second output of the channel decoder code, the first output of which is connected to the bus output parallel data, the first and second inputs of the second switch are connected respectively to a second input of the second element of the input element OR NOT to D0-the input of the second counter, the rest of the D-input of which is connected to the bus logic zero, the control input mode receive/invoice to the output of the EXCLUSIVE OR element, C is the entrance to the exit of the element OR NOT, R-entrance to the bus reset, and the second input of the first selector code is connected with the bus clock pulses.

 

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4 cl, 6 dwg

FIELD: technology for recording encoded bit flow consisting of multiple video objects, containing a series of cells, which together form a portion of software stream corresponding to MPEG-2 standard, onto optical disc.

SUBSTANCE: method includes recording additional series of video objects one following another in storage area of disc for video objects. In disc control information area, control information is recorded, wherein aforementioned set of video objects is split on adjacent records, which represent content lists to be reproduced. Content lists for reproduction are determined as series of reproduction of all filled cells or sub-set of filled recording cells in order of placement in video objects storage area on disc, and content list is formed of contents, sorted in order of position in video objects area on disc. Recording device has system control means, adopted for determining reproduced content list, as series of reproduction of all filled cells or sub-set of filled recording cells in placement order in area for video objects storage on disc and for forming content list, sorted in order of position in video objects area on disc.

EFFECT: possible recording of software stream according to MPEG-2 standard in real time, supported compatibility of DVD video format.

2 cl, 14 dwg

FIELD: methods and devices for recording encoded bit flow onto data carrier of disk type.

SUBSTANCE: method includes recording at least two sets of video objects onto disk. Each set of video objects consists of video objects following one another. Each video object has a series of cells, together forming a portion of MPEG2 software stream. At least two sets of video objects are joined as single video objects set. First and at least second control information is recorded before aforementioned joined set of video objects. After aforementioned joined set of video objects, a copy of first and at least of second control information is recorded. Method is based on recording device, including system control means, allowing recording of at least two aforementioned video object sets onto disk; joining them as single set of video objects; recording first and at least second control information before aforementioned joined set of video objects; recording a copy of first and, at least, second control information after aforementioned joined set of video objects.

EFFECT: positioning of control information before all video objects simplifies addressing and allows to perform recording in real time scale, while DVD-video format compatibility is maintained.

2 cl, 17 dwg

FIELD: technology for creating subtitles by reproducing a digital stream, formed by multiplexing of video stream and graphical stream.

SUBSTANCE: in accordance to the invention, a record carrier, primarily of BD-ROM type, stores an audio and video clip recorded on it, built by multiplexing of video stream and graphic stream. The graphic stream represents a moving image, composed of a set of images, where the graphic stream includes graphic data, which represent graphics subject to combining with images. The graphic stream also includes window information (WDS), which defines the graphic visualization window, and which denotes width, height and position of the window on the plane which is the graphic memory of reproduction device, which combines graphics with images.

EFFECT: increased efficiency.

5 cl, 42 dwg

FIELD: physics, computer facilities.

SUBSTANCE: invention concerns granting of numbers of the enhanced temporary code for devices of multimedia which make multimedia presentation content. The dilated time code which can be presented in the table of temporary conformity, for example such which use on the carrier of data, such as DVD is entered unique, and can be presented separately from devices of multimedia. Such table of temporary conformity is associated to earlier existing information file or give as an exchanging file of the dilated information which includes the inherited information file.

EFFECT: distinction of devices of the multimedia having identical linear time code.

38 cl, 10 dwg

FIELD: physics; computer facilities.

SUBSTANCE: invention provides the device driving mapping of additional data to data content data. The device maps the given number of devices of the information on the chosen objects of reproduction consistently exchanging one another during the given continuance of time at reproduction in a mode with takeoff of data of the content.

EFFECT: making of the device driving mapping of additional data to content data.

15 cl, 24 dwg

FIELD: physics; computer engineering.

SUBSTANCE: device reads information from a storage medium and identifies information on access points. The device then sets the priority level for each access point. The priority level allows for determining whether the access point for video data is the beginning of the video data section, or whether change in scene for this access point is important.

EFFECT: design of an efficient method and device for recording data onto a recording medium.

10 cl, 68 dwg

FIELD: information technologies.

SUBSTANCE: invention refers to content reproduction device and content reproduction method which both make possible to select and reproduce content, for example music in accordance with movement rate of user who wears this device. Reproduction device contains facility for detection of movement rate change intended for detection of detected movement rate change, and control facility. Control facility is intended for control execution in such a way when content is selected that when detected rate change increases the content changes quickly in accordance with movement rate change. In case when detected movement rate change remains constant content does not change. When movement rate change decreases content changes with delay relative to rate change.

EFFECT: possibility to select musical content in accordance with user movement rate change which let musical content to follow user movement rate changes well.

6 cl, 4 dwg

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to high density recording medium such as a read-only Blu-ray disc (BD-ROM), as well as to methods and devices associated with the said disc. In the data structure for managing playback of graphic information, graphic information and indicator associated with the graphic information are stored on a recording medium. The indicator indicates whether the graphic information is meant for display in response to a user request.

EFFECT: design of a high density recording medium.

24 cl, 8 dwg

FIELD: physics; computer engineering.

SUBSTANCE: method of playing back optical disc comprises the following steps: obtaining information describing content which should be played back, creation of a playback file system in accordance with the said information. Said information can be accessed and played back using a single application program interface in accordance with the said playback file system. Content which should be played back contains optical disc content and extended content stored on other storage media (for example networks).

EFFECT: easier operation of the playback system by separating the playback mechanism from specific recording media.

16 cl, 5 dwg

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