A method of manufacturing the mos transistor

 

(57) Abstract:

Usage: in microelectronics, technology of manufacturing field-effect transistors with a high degree of integration. The essence of the invention: in the manufacture of a MOS transistor after formation of the field oxide to form polysilicon gate electrode. To do this, on the surface of a silicon substrate with a structure formed by a silicon dioxide - silicon nitride consistently applied the first layer of silicon dioxide, polycrystalline silicon, silicon nitride, a second layer of silicon dioxide, which form a groove corresponding to the shape of the gate electrode, and a depth equal to its thickness, polysilicon wall of the groove is thermally oxidized, and then from the bottom of the groove to remove the layers of silicon nitride and silicon dioxide and form the gate oxide, and then put a layer of polycrystalline silicon with the same thickness as the gate electrode, the layer of polycrystalline silicon planarized on the level of the upper edge of the groove, the surface layer of polycrystalline silicon in the trench is thermally oxidized, then remove the second layer of silicon dioxide, a layer of silicon nitride, a layer of polycrystalline silicon, the first is STI drain and the source by the method of ion doping, remove the silicon dioxide from the surface of the gate electrode, sprayed a layer of titanium, conduct siliconhouse annealing and chemically remove unreacted titanium. 13 Il.

The invention relates to microelectronics and can be used in various types of integrated circuits with a high degree of integration.

The main element of most BIS with high performance are MOS transistors with shallow areas of the drain and the source. The electrodes of the shutter to the structure of the refractory metal silicide - polysilicon (police) and bypass areas of the drain and source of the transistor film of silicide of the refractory metal with low resistivity increases the operating speed of the transistor and reduce its power.

The known method of forming a MOS transistor with a siliconized areas drain, source and gate electrode [1], providing Salaspilsa alloy Ti and Si in a ratio of 1:1 to the surface of the structure formed by standard polysilicon technology shutter. Next, the structure is subjected siliconhouse annealing. Titanium disilicide thus formed on the surfaces of the drain regions, the source, polysilicon elec is the established levels of oxidized, while on the surface titaniun disilicide growing film of silicon dioxide over the other regions are formed of a film of oxides of metals of complex composition. During the oxidation of the polysilicon gate electrodes are reduced in size (due to the consumption of silicon during oxidation), and the film titaniun disilicide is immersed in the deep areas of the drain and the source, resulting in the gate electrode is electrically isolated from the drain and source region of silicon dioxide.

The disadvantages of this method are the need for strict control of the operation of oxidation, and in addition, the difficulty of determining the end of the process of formation of structure and, as a consequence, poor sensitivity of the process, as well as the possibility of unwanted redistribution of impurities in the areas of the drain and the source.

These shortcomings are resolved by separating the gate electrode and drain regions and source of the film of silicon dioxide formed before the operation siliconware. A known method of manufacturing a MOS transistor with a siliconized areas drain, source and gate electrode [2], providing for the formation of regions of silicon dioxide, preventing short-circuit areas of the drain and the source with ele is down.

This method requires the use of gate dielectric with complex structure silicon dioxide - silicon nitride. The disadvantage of this method is the presence of additional boundaries in the structure, which leads to a change in the value of the embedded charge in the gate dielectric, deteriorating the reproducibility of the threshold voltage of the transistor. This method of forming the MOS transistor is very critical to the cleanliness of the process of applying a film of silicon nitride.

As a prototype the selected method of manufacturing a MOS transistor with a siliconized areas drain, source and gate electrode [3], providing for the formation of the polysilicon gate, the subsequent application of a layer of silicon dioxide and its removal by the method of reactive ion etching (RIT). This polysilicon gate electrode moves away from the drain and source region of silicon dioxide, preventing short-circuit electrode and the gate regions of the drain and the source in the process of siliconware. Next, on the surface of the structure put a layer of titanium, produce siliconhouse annealing and removing unreacted titanium in liquid provide the Etchant. Then follow the standard operation of forming the interlayer idea the method prototype is RIT system silica - polycrystalline silicon, the disadvantages of which are the variety generated in the plasma chemically active particles, making it difficult to control their concentration and leads to a low speed and a low value of the selectivity of the etching patterns of the silicon dioxide - silicon (increasing values of the selectivity of the etching due to the addition of plasma to the formation of hydrogen in the chamber vapor HF, cause corrosion and shorten the life of the equipment) (Ivanovo, F. Ion-plasma processing of materials. M: Radio, 1986); the formation of radiation defects in the MOS (the irradiation of particles with energies 1-1,5 Kev, the depth of the damaged layer is 30 nm), which leads to a surface charge, deteriorating electrical characteristics of the MOS structure (Danilin, B. C. the Use of low-temperature plasma. Energoatomizdat, 1987); the high cost of technological equipment. The application of the RIT complicates the manufacturing process of the MOS transistor, lowers the percentage of yield, reduces the reliability of the MOS transistor increases its cost.

The aim of the invention is to simplify the technological process of manufacturing the MOS transistor, the improvement process is P CLASS="ptx2">

The aim is achieved in that after the formation of a local protective oxide on the surface of a silicon substrate formed with the structure of silicon dioxide - silicon nitride are sequentially applied layers of silicon dioxide, polycrystalline silicon, silicon nitride, silicon dioxide, which form a groove corresponding to the shape of the gate electrode, and a depth equal to its thickness, polysilicon wall of the groove is thermally oxidized, and then from the bottom of the groove to remove the layers of silicon nitride and silicon dioxide and form the gate oxide, and then put a layer of polycrystalline silicon with the same thickness as the gate electrode, the layer of polycrystalline silicon planarized on the level of the upper edge of the groove, the surface of the polycrystalline silicon in the trench is thermally oxidized, and then outside of the gate electrode sequentially remove layers of silicon dioxide, nitride silicon, polycrystalline silicon, silicon dioxide, silicon nitride, silicon dioxide, is the formation regions of the drain and the source by the method of ion doping, removing a layer of silicon dioxide from the surface of the shutter, sputtering a layer of titanium, siliconhouse annealing, removing neprology the BOV is a change in the sequence of technological operations after the formation of a local protective oxide, forming a region of silicon dioxide, separates the polysilicon gate electrode and drain and source in the process of siliconware, before forming the gate electrode, an exception from the sequence of technological operations RIT.

Formation region separating the gate electrode and drain and source in the process of siliconware not previously been used to simplify the technological process of manufacturing the MOS transistor, increasing the percentage of yield in its production, increase reliability and reduce the cost. Therefore, this difference is significant.

In Fig.1 - 13 shows the sequence of the basic technological operations of manufacturing the MOS transistor according to the present method.

On a silicon substrate is grown a layer 1 of silicon dioxide (Fig.1) on which is deposited a layer 2 of silicon nitride (Fig.2), and then by photolithography masking region in which the transistor will be formed. Outside this area the layers of silicon nitride and silicon dioxide are removed and grown thick protective oxide 10 (Fig.3). Next, on the surface of the structure obtained sequentially applied layers of silicon dioxide 3, polysilicon is formed at the image of the slit, corresponding in shape to the gate electrode, and then the structure is etched groove depth equal to the thickness of the gate electrode (sequentially compares the layers of silicon dioxide, silicon nitride, polycrystalline silicon, silicon dioxide (Fig.5). Next, the resulting structure is subjected to heat treatment in an oxidizing atmosphere. When this oxidized polysilicon wall 11 of the groove (Fig.6), then removed the layers of silicon nitride 2 and silicon dioxide is 1 and there is formed a gate oxide layer 7 (Fig. 7). Then the deposited layer 8 of polycrystalline silicon (Fig.8) and planarization to the level of a layer 6 of silicon dioxide (Fig.9). On the surface of the polycrystalline silicon to form a layer 9 of silicon dioxide (Fig. 9), then removed the layers of silicon dioxide 6, silicon nitride 5, polycrystalline silicon 4, silicon dioxide 3, of silicon nitride 2, silicon dioxide 1. Thus is formed the gate electrode, protected on all sides by a layer of silicon dioxide (Fig.10). The method of ion implanted region 13 are formed source and drain (Fig.10), is performed to activate the impurities, removes the layer 9 of silicon dioxide (Fig.11). On the surface obtained structure.however metal from the surface of silicon dioxide (Fig.13). Further, when manufacturing the MOSFET follow the standard operation of forming the interlayer isolation, switching wiring and passivation.

The essence of the proposed method lies in the fact that after the formation by known techniques of isolation of local oxide on the surface of the substrate is formed of a multilayer structure of silicon dioxide (layer 1) - silicon nitride (layer 2) - silicon dioxide (layer 3) and polycrystalline silicon (layer 4) - silicon nitride (layer 5) - silicon dioxide (layer 6), the total thickness of which is equal to the thickness of the gate electrode. In this structure, methods of photolithography, plasma-chemical (PCT) and liquid etching groove is formed corresponding to the shape of the gate electrode, the depth equal to its thickness.

When the etching of the multilayer structure is considered high selectivity PCT systems = 80 and = 100 in the atmosphere of sulfur hexafluoride (I.e. True. Basics of VLSI technology. M.: Radio and communication, 1985), as well as high selectivity etching system = 80 in the buffer provide the Etchant (HF:NH4F=1:10) (Nitride of silicon in microelectronics. Novosibirsk: Nauka, 1982).

The proposed structure allows forming region of silicon dioxide on the ends of the layer polices the region subsequently separates the gate from the drain and the source in the process of siliconware. The locality of the oxidation process is provided by masking the substrate surface at the bottom of the groove and a layer of polysilicon film of silicon nitride. The film of silicon dioxide (layer 6) serves as a mask during PCT underlying layers of silicon nitride (layer 5) and polycrystalline silicon (layer 4). The film of silicon dioxide (3 layer) serves as a stop layer during the etching of polycrystalline silicon (layer 4) and silicon nitride (layer 5). The film of silicon nitride (layer 5) provides masking the surface of the polycrystalline silicon at the local oxidation of the walls of the grooves. The film of silicon nitride (layer 2) prevents oxidation of the surface of the substrate at the bottom of the groove. The film of silicon dioxide (layer 1) serves as a stop layer during the etching of silicon nitride (layer 2). After the formation of regions of silicon dioxide on the sidewalls of the grooves is consistent removal of films of silicon dioxide (layer 3), silicon nitride (layer 2), silicon dioxide (layer 1) at the bottom of the groove. Then at the bottom of the groove is formed a film of silicon dioxide (layer 7), which serves as the gate dielectric of the transistor structure. Later in the groove of the deposited film of polycrystalline silicon (layer 8) thickness equal to the depth of the grooves is diffusive grooves, then, on the surface of polycrystalline silicon (layer 8) in the groove layer is formed of silicon dioxide (layer 9). Thus is formed a polysilicon gate electrode, protected on all sides by a film of silicon dioxide. After that, the multilayer structure outside of the gate electrode sequentially discharged to the surface of a silicon substrate, the formation regions of the drain and the source, removed the film of silicon dioxide (layer 9) and a film of silicon dioxide formed on the surface areas of the drain and source during thermal activation of the impurity, then, as in the prototype, sprayed film of the refractory metal, is solicitously annealing and removing unreacted metal.

To implement the above sequence of processes of manufacturing the MOS transistor is an important ratio of the layer thicknesses. The minimum thickness of a layer 1 of silicon dioxide, providing masking the substrate with chemotherapy film of silicon nitride (layer 2), is determined by the value of the selectivity of the etching system in the plasma of a given composition. The minimum thickness of the layers 2, 5 of silicon nitride, the mask substrate and the polycrystalline silicon film (layer 4) the time from which edatrexate oxidation masking surfaces. The maximum thickness of the layers 1, 2, 5 is determined by the equality of total thickness of layers 1, 2, 3, 4, 5, 6 given the thickness of the gate electrode.

As the layer 6 of silicon dioxide is retained after removal of the layers 3, 1 from the bottom of the grooves may also function as a stop layer during chemotherapy layer 8 of polycrystalline silicon, its thickness should be greater than the total thickness of the layers 3, 1 by an amount equal to the minimum thickness of the layer 1. The layer 9 of silicon dioxide is retained after removal of the layers 6, 3, 1 silicon dioxide outside of the gate electrode and then take the mask function in the formation regions of the drain and the source by the method of ion doping, therefore, its thickness should be greater than the total thickness of these layers on the average mileage of impurity ions with an energy selected for the formation of regions of the drain and the source. As the layer 11 of silicon dioxide is subjected to etching during removal of the layers 9, 6, 3, 1, its thickness should be greater than the total thickness of these layers by an amount necessary to prevent the formation of a film of disilicide refractory metal on the surface of the side walls of the gate electrode.

P R I m e R 1. As an example, the particular application claimed smarky EFC - 2,5 (100) with a thickness of 380 μm, which on the surface by thermal oxidation were grown film of silicon dioxide (layer 1) with a thickness of 70 nm, and on its surface by precipitation from the gas phase at low pressure (LPCVD) was deposited film of silicon nitride (layer 2) with a thickness of 0.1 μm. Then over the areas in which will be formed transistors, the structure was masked with a photoresist, outside these areas, the film of silicon nitride was removed PCT in SF6(the selectivity of the etching system nitride silicon (silicon dioxide in the plasma exceeds 100), and a film of silicon dioxide liquid was removed by etching in a mixture of NH4F:HF=10:1. After this thermal method were formed local protective oxide thickness of 1 μm on the surface of the structure obtained by the method of pyrolytic decomposition of monosilane deposited layer of silicon dioxide (layer 3) with a thickness of 0.1 μm, then the method of LPCVD deposited layer 4 of polycrystalline silicon with a thickness of 0.4 μm and a layer 5 of silicon nitride with a thickness of 0.1 μm. On the surface of the structure obtained by the method of pyrolytic decomposition of monosilane was applied a layer 6 of silicon dioxide of a thickness of 0.25 μm. Then, by photolithography on the surface of the structure formed image of the slit thus the which serves as a mask during PCT system polycrystalline silicon the silicon nitride, the film of silicon dioxide (3 layer) serves as a stop layer when forming the grooves in the structure of polycrystalline silicon - silicon nitride. Then chemical etching of the film of silicon dioxide (layer 3) was removed from the bottom of the groove, the thickness of the film of silicon dioxide (layer 6) was decreased to 0.15 μm. Next, polysilicon wall of the groove oxidized and formed a layer of silicon dioxide (layer 11) with a thickness of 0.7 μm. The method of PCT at the bottom of the grooves was removed layer 2 of silicon nitride and the liquid was travelpulse layer 1 of silicon dioxide, the thickness of the layer 6 of silicon dioxide was decreased to 0.06 μm, and the thickness of the layer 11 is to 0.63 μm. At the bottom of the grooves was formed layer 7 gate oxide thickness of 70 μm, then the method of LPCVD deposited layer 8 of polycrystalline silicon with a thickness of 0.8 μm, were used diffusion doping to ensure the value of the surface resistances= 40 Ohms/. After this was made planarization surface layer 8 of polycrystalline silicon, which on its surface was applied a layer of photoresist OP PH 7, which was subjected to heat treatment and UV irradiation. After developing, the photoresist remained in the groove, where the spreading during thermobreak silicon in the plasma of sulfur hexafluoride, the layer 6 of silicon dioxide serves as a stop layer in the process. After removal of the photoresist surface layer of polycrystalline silicon is oxidized, in consequence of which it was formed layer 9 of silicon dioxide with a thickness of 0.3 μm. Next, the etching liquid was removed layer 6 of silicon dioxide, the thickness of the layer 9 was decreased to 0.2 μm, the method PCTs were removed layers of silicon nitride (layer 5) and polycrystalline silicon (layer 4). The stop layers in this process were the film of silicon dioxide (layers 11, 3). Liquid etching removed the layer 3 of silicon dioxide, the thickness of the layer 11 was decreased up to 0.73 μm, and the thickness of the layer 9 is reduced to 0.08 μm. Next, a method of polychemotherapy was removed layer 2 of silicon nitride and method a liquid etching layer 1 of silicon dioxide, the thickness of the layer 9 was reduced to 0 - to 0.1 μm, and the thickness of the layer 11 to 0.6 μm. The method of ion implanted boron at E=40 Kev, D= 3x1012cm-2formed region of the drain and source of the MOS transistor was produced thermal activation of the impurity at T=950about40 min N2and a liquid etching removed the film of silicon dioxide (layer 9) and formed on the surface areas of the drain and source in the process of thermal activation of the impurity, while 2ABOUT2:H2SO4), and were coated film of titanium with a thickness of 50 nm. Then he produced a vacuum siliconhouse annealing (700aboutC, 15 min, p= 1x10-6mm RT.cent.). After that, unreacted titanium is removed in a mixture of KARO and the structure was annealed in order in vacuum (750aboutC, 15 min, p=1-3x10-6mm RT.cent.).

P R I m m e R 2. The inventive method is tested in the production of n-channel MOS transistor. The starting substrate was a silicon wafer mark EFC-2,5 (100) with a thickness of 380 μm, in which the method of ion implanted boron (E= 120 Kev, D= =6,2x1012cm-2) was formed region of the pocket, then produced thermal justify impurities at 1000aboutC for 5 h under nitrogen atmosphere. Next, on the surface of the substrate thermally grown film of silicon dioxide (layer 1) with a thickness of 100 nm on its surface by the method of LPCVD deposited film of silicon nitride (layer 2) with a thickness of 0.12 μm. Then methods of photolithography and chemotherapy in the atmosphere of sulfur hexafluoride over the areas in which will be formed transistors were made of two-layer mask silicon nitride - silicon dioxide, which protects the area in which will be formed in the transistor during thermal forming locally the structure by the method of pyrolytic decomposition of monosilane deposited film of silicon dioxide (layer 3) with a thickness of 0.12 μm, then by the method of LPCVD deposited layer 4 of polycrystalline silicon with a thickness of 0.45 μm and a layer of silicon nitride (layer 5) with a thickness of 0.15 μm. On the surface of the structure obtained by the method of pyrolytic decomposition of monosilane was applied a layer 6 of silicon dioxide 0.3 microns. Then, by photolithography on the surface of the formed image of the slit corresponding to the shape of the gate electrode. Etching in buffered provide the Etchant (HF:NH4F=1:10) was formed window in layer 6 of silicon dioxide, which served as a mask during PCT system polysilicon - silicon nitride (layers 4, 5), a film of silicon dioxide (3 layer) serves as a stop layer. Then etching liquid in the buffer provide the Etchant film of silicon dioxide (layer 3) was removed from the bottom of the groove, the thickness of the film of silicon dioxide (layer 6) was decreased to 0.18 μm. Next, polysilicon wall of the groove is thermally oxidized, the thickness of the obtained film of silicon dioxide (layer 11) was 1 μm. After this PCT of the bottom of the grooves was removed layer 2 of silicon nitride was etched into the buffer provide the Etchant layer 1 of silicon dioxide, the thickness of the layer 6 of silicon dioxide was decreased to 0.08 μm, and the thickness of the layer of 11 - to 0.9 μm. At the bottom of the groove of thermally formed a gate oxide layer 7 with a thickness yonnie doping to ensure that the surface resistance of 40 Ohms/square After this was made planarization layer 8 of polycrystalline silicon on the level of the upper edge of the groove. Then, after removing a layer of polycrystalline silicon beyond the groove surface of the polycrystalline silicon filled in the groove, thermally oxidized, resulting in the formed film of silicon dioxide (layer 9) with a thickness of 0.32 μm. Next in the buffer provide the Etchant was removed layer 6 of silicon dioxide, the thickness of the layer 9 was decreased to 0.24 μm, PCT removed the layer of silicon nitride 5 and polycrystalline silicon 4 out of the groove. Stop layers when it served as a film of silicon dioxide (layers 11, 3). Then in the buffer provide the Etchant was removed layer 3 of silicon dioxide, the thickness of the layer 11 has decreased to 0.78 μm, and the thickness of the layer 9 is 0.10 μm. Further chemotherapy was removed layer 2 of silicon nitride and travelpulse layer 1 of silicon dioxide, the thickness of the layer 9 was reduced to zero, and the thickness of the layer 11 is to 0.67 μm. The method of ion implanted with phosphorus at E=40 Kev, D=3x1013cm-2formed region of the drain and source of the MOS transistor was produced thermal activation of the impurity at T=950about40 min in nitrogen atmosphere. The structure was processed in a mixture of N2ABOUT2:H2SO4and produced -6mm RT.cent.), after that, unreacted titanium is removed in a mixture of N2ABOUT2:H2SO4and the structure was annealed in order in vacuum (750aboutC, 15 min, p=1,3x10-6mm RT.cent.).

The proposed method is practically feasible, gives a positive effect and can be recommended for the manufacture of BIS MOS-transistors with policyjnym samozavestna gate.

Technical and economic efficiency of the proposed method consists in the following: simplified manufacturing process of the MOS transistor due to the replacement of a complex transfer process RIT closely controlled by the operations of forming and etching films, increases the percentage of the output transistors due to the strict control of parameters of technological processes in 2-2,5 times, increase reliability of the transistor due to the exclusion of the impact of high-energy particles on the MOS structure during its manufacture, reduces the cost of the transistor due to the lack of the need to use costly installation of reactive ion etching by about 10%.

A METHOD of MANUFACTURING a MOS TRANSISTOR, including thermal oxidation of the silicon substrate, causing the thief, the formation regions of the drain and the source by the method of ion doping, sputtering a layer of titanium, siliconhouse annealing and chemical removal of unreacted titanium, characterized in that for forming a polysilicon gate electrode on the surface of a silicon substrate formed with the structure of silicon dioxide - silicon nitride are sequentially applied layers of silicon dioxide, polycrystalline silicon, silicon nitride and a second layer of silicon dioxide, which form a groove corresponding to the shape of the gate electrode, and a depth equal to its thickness, polysilicon wall of the groove is thermally oxidized, then from the bottom of the groove to remove the layers of silicon nitride and silicon dioxide and form the gate oxide, and then put a layer of polycrystalline silicon with the same thickness as the gate electrode, the layer of polycrystalline silicon planarized on the level of the upper edge of the groove, the surface layer of polycrystalline silicon in the trench is thermally oxidized, then remove the second layer of silicon dioxide, a layer of silicon nitride, a layer of polycrystalline silicon, the first layer of silicon dioxide, a layer of silicon nitride and silicon dioxide outside the gate electrode, and

 

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