Device for correcting errors in a multiple repetition of messages


H03M13/02 -

 

(57) Abstract:

The invention relates to a remote control and pulse technique and can be used in the transmission and processing of discrete information for error correction in communication channels. The purpose of the invention is the increased robustness due to the expansion of the set of decision rules and accounting erase signals for correction of the most unreliable symbols. This objective is achieved in that in a device for correcting errors in a multiple repetition of messages, containing three of the shift register 1 to 3, the counter 5, the deciding unit 6, entered the fourth shift register 4, the control unit 7, the detector quality 8 with corresponding connections, which allows to increase the number of combinations is subjected to processing, thereby increasing correcting capacity of the device and the reliability of the received messages. 6 Il., table 4.

The invention relates to a remote control and pulse technique and can be used in systems for the transmission and processing of digital data for correcting errors in communication channels.

A device for adaptive reception and majority decoding, containing 3 of the shift register, key, three switches, reaosning opportunities manifested in the fact that not analyzed all of the States of repetitions of the message.

Closest to the present invention is a device for adaptive majority decoding telemechanics duplicated signals containing three shift register sequentially included a key and a counter whose outputs through the respective elements And shift registers are connected to the inputs of the decision making unit and its installation inputs, while the outputs of the elements And connected to additional inputs of the decision making unit, the output of which is connected with the control input of the key fault input is combined with a second input elements And [2].

The disadvantage of this device is the low immunity, or the inability of the device to accept majority decisions "three" on the sixth, ninth, twelfth repetition, "five" on the eighth, eleventh, "seven" on the tenth, the thirteenth repetitions.

At the same time when using channels of low quality due to intensive interference there may be occasions when not distorted by the fourth or fifth and sixth iterations or when correct one or two of the fourth, fifth, sixth repetitions and properly taken o can be distorted tenth and at least three of the six repetitions, starting with the seventh and so on, so with high probability we can say that the known device is not corrected all errors after receiving thirteen repetitions.

The purpose of the invention is the increased robustness.

In Fig. 1 shows a structural diagram of a device for correcting errors in a multiple repetition of the message based on signal erase. The device has an n-bit shift registers 1-4, the deciding unit 6, the control unit 7, the detector quality 8.

The device performs the majority of the processing in three, five, seven repetitions, starting with the first, fourth, seventh, tenth, thirteenth, which allows the use of channels of low quality to make the right decision in the cases described above.

In Fig. 2 shows an operation algorithm of the device.

In the upper part of Fig. 2 in simplified form, shows that the arrival of the third, sixth, ninth, twelfth repetitions on the output device produces the result of the majority processing "three", by the arrival of the fifth, eighth, eleventh repetition produces the result processing "five" and on the arrival of the seventh, tenth, thirteenth retry is issued the majority obrabotkata 1, 2, 3... indicates the retry messages, line RG1-RG4 indicate the code number of units recorded from the counter in the registers RG1-RG4. And blacked out cells indicate that the decision shall be rendered on the output device simultaneously with the entry in the shift registers. So the arrival of the first repeat in the register RG1 is written first repeat, and in the register RG2 is recorded corresponding to the repeat signals s 1. With the advent of the second repeat information out of RG1 and goes to the counter, where code is generated the number of units of two iterations with a given signal s of the first and second repetitions and recorded in the registers RG1 and RG2, and in the register RG1 is written low-order bits of code, but the register RG2 is the most significant bit. With the advent of the third repeat with the outputs of the registers RG1 and RG2 code number of units 2 repetitions is supplied to the counter where a given signal s of the third repetition code is generated the number of units of three repetitions and recorded in the registers RG1 and RG2 and at the same time information, which is recorded in the register RG2 is supplied to the output device. This is the result of the majority processing on "three" with regard to the erase signals. Similarly, there are registers RG3 and RG4 upon arrival of the fourth, fifth, sixth repetition. At the same time in the registers RG1 and RG2 is minuets from a code number of units of the fourth and fifth iterations and code number of units of the first three repetitions. Read more the principle of the formation of majority decisions with regards to erase signals are described below.

The counter 5 is designed to count the number of units of the same type for the elements taken repeats and their correction using signals erase. The counter consists of two identical circuits are identical in structure and characterized in that they work with different shift registers and at different triples of repetitions.

In Fig. 3 shows a possible variant of the circuit of the counter code number of units and erase signals. The counter contains a synchronous T-triggers installation R-inputs 26-29, items, OR 20-25, 43-46, 53-54, elements, And 1-19, 30-42, 47-51, inputs 1-6, control inputs VI-18, the input clock. Control inputs U1-U3 are the inputs that are served potentials during the repetitions 1-3. On the control inputs u served controlling potentials during 4, 5, 6 repetitions. The control potentials are generated in the control unit.

In Fig. 4 presents the control unit. The principle of construction of the unit and its operation are described below.

The counter works as follows. With the arrival of the first repeat, coming to the first input of the counter by means of the control potentials U1 through elements, opisyvayutsya in the register RG2. After the first repeat in the register RG1 is written first repeat, and in the register RG2 is appropriate unreliable symbols of the first repeat signal erase.

With the advent of the second repeat of the register RG1 is the first repeat, and is supplied to the third input of the counter, on his fourth input signals s of the first repeat. The second repeat is supplied to the first input of the counter, the signal erase is at the second entrance. During the second repetition works items 2-4, 6-9, 20, 22, 14, 16, 24, 25, the control produces a control potential N2. The processing algorithm of the first and second iterations with a given signal erase these repetitions are given in table. 1, where the columns represent different combinations of the first, second replay and erase characters. RG1 and RG2 indicate the result of processing that is written in these registers. Code number of units of the eponymous characters of the first and second iterations are formed as follows:

0 + 0 = 00

0 + 0 = 01

1 + 0 = 01

1 + 1 = 10

Interest combinations of 3, 6, 9, 12 (see table. 1), which is realized accounting signals erase. Other combinations of the erase signals are ignored. Consider a combination of the 3. In the first repeat Simcoe this symbol was "0" signals without erase more likely to say that the second repeat is not a reliable character "0".

Therefore, in the registers RG1, RG2 write the code number of units already given the signal erase. Similar decisions are made for combinations of 6, 9, 12. At the end of the second repeat in the registers RG1, RG2 will be recorded code number of units of the first and second repeat, taking into account signals erase these repetitions, and in the register RG1 is written low-order bits of code, number of units, and in the register RG2 is the most significant bit.

With the advent of the third repeat at the first input of the counter and the corresponding signals s on the second, third and fourth inputs of the counter enters the code number of units of the first and second repetitions of the registers RG1 and RG2. Information processing during the third repetition is implemented in elements 5, 10, 11, 12, 15, 17, 21, 23-28 when the control potential U3. The processing algorithm of the first three repetitions with regard to the erase signals of the third repeat is shown in table. 2.

Interest combinations of 3, 9, in which is recorded signals s of the third repeat. For example, the combination of 9 means that the first two repetitions were two "1", and the third repetition was "0", but it matches the signal erase. The principle is".

The result of the majority processing three repetitions simultaneously with the entry in the registers is given to the output device through a crucial block.

On the arrival of the fourth, fifth, sixth repetitions works the second part of the schema of the counter code number of units and erase signals together with the registers RG3 and RG4, similarly to the first three repetitions. At this time, in the first part of the counter is overwritten code number of units of the first three iterations with the outputs of the registers RG1 and RG2 on their inputs, through the elements 18, 24, 26, 19, 25, 28 (see Fig. 3).

The majority processing "three", "five", "seven" provides a crucial block functional diagram of which is shown in Fig. 6. It contains elements And 1-6, 8-19, 22, 23, items, OR 7, 20, 21, 24, inputs 1-9, control inputs U1-u, the output unit is an output device.

Decision making in the block is as follows with the advent of the third repeat on the second output of the counter is formed the majority of the processing "three", which is supplied to the fifth input of the decision making unit, and in it the item, And 11. By the control potential P3, it passes to the input of the OR element 24 and is supplied to the output device.

Managing potential runs on 3, 9, 15 to repeat the processing of the "three" fourth, fifth, the sixth repetition and arrives at the ninth sign of the decision making unit via the element And 10, outdoor managing potential P6, and the item OR 24 on the output device. Managing potential P6 included 6, 12 repeats (see Fig. 5). With the advent of the fifth repeat with the first and second outputs of the counter for the third and fifth unit of decision rules is served code number of units of the first, second and third repeat, and with the third and the fourth output of the meter at the seventh and ninth input of the decision making unit code number of units of the fourth and fifth repeat. The decision of the majority processing "five" shall be in accordance with table. 3.

Table columns 1-4 correspond to the outputs of the unit-four counter. The column "maj 5 shows the decision diagram for the arrival of a combination code number of units. Columns 4, 3 show in this case that was recorded code number of units of the fourth and fifth repetitions, as in columns 1, 2 code number of units of the first, second and third repetitions, and the digits 2 and 4 high. So the entry in the fourth line means that the first three repetitions was one "1" and in the fourth, fifth repetitions one "1", the output "maj 5" - "0". The entry in the twelfth line means that the first three repeat is this combination code number does not exist, as in the fourth and fifth repetitions cannot be three units.

The implementation table. 3 is obtained (see Fig. 6) using elements 16-19, 21. Element And 23 is used for issuing the majority decision "five" for 5, 11... replays using the control potential P5 supplied from the fifth output control unit on the fifth control input of the block.

the majority of processing five repetitions goes to the output device. Similar processing takes place "five" and with the advent of the eighth repetition. With the first and second outputs of the counter for the third and fifth inputs enters the code number of units of the seventh and eighth iterations, and with the third and fourth outputs of the counter at the seventh and ninth input of the decision making unit enters the code number of units of the fourth, fifth, and sixth repeats.

The majority processing "five" is performed on the elements 12-15, 20, 22 using the control potential P2 supplied from the second output of the control unit to the second control input of the decision making unit. The result of the majority of the processing is supplied to the output device.

The seventh repetition, in addition to recording in the register RG1, is supplied to the first input of the decision making unit and at the same time on the second, fourth, sixth, and eighth inputs of the decision of the CSO, the second and third repetitions. Register RG3, RG4 code number of units of the fourth, fifth, and sixth repeats. The essence of the majority processing "seven" is presented in the table. 4.

Columns RG1-RG4 show the possible combinations of code number of units in six repetitions, and in the register RG4 high-order digits of the code number of units. Column 7 represents the possible States in the seventh repetition. The column "maj 7 shows the result of the majority processing "seven".

So, recording in the fifteenth row of the table. 4 means that the first, second, third repetition was one "1" in the fourth, fifth, sixth or three "1", in the seventh repetition of "1". I.e., seven times five "1". The result of the majority of the processing is "1".

The implementation table. 4 presents in the final block on elements 1-7. The result of the majority processing "seven" on the seventh, thirteenth redo is applied to the input element And 9, to the second input of which is applied a control potential P1 from the first output control unit. With the output element And 9 majorite seven passes through the element OR 24 on the output device.

Similar processing occurs for admission to the first input of the decision making unit of the tenth repetition. In this case, PL. 4 does not change, so the SLA units fourth, the fifth and sixth iterations. Using the control potential A4 result of the majority processing "seven" on the tenth repetition is supplied to the output device.

Detector quality 8 is a diagram for informational inputs and two outputs. The first output (coding scheme) formed themselves information symbols, the second output (two-threshold scheme) the decision on the reliability of the information symbols, i.e., is issued in the case of an unreliable character signal erase.

The authors do not claim novelty detector quality. Read more the principle of its construction and operation are described in the known technical solution.

The control unit 7 is designed for timely supply of clock pulses to the counter and shift registers RG1-RG4 and distribution of control potentials applied to the counter 5 and the deciding unit 6 (see Fig. 1).

A possible embodiment of the control unit shown in Fig. 4. It contains elements And 1-7, elements, OR 8, 9, asynchronous RS-flip-flop 10 and the bit counter 11, six-digit counter 12, a decoder 12, three inputs, eight outputs, control potentials, the output of sync.

Timing diagrams describing raboteg part of this device; 1, 2 control inputs; 3 - input sequence of pulses; P1-P8 - control potentials applied to the respective outputs of the control unit; SI output clock.

The control unit starts the control with the arrival at its first input pulse, indicating that the communication channel is accepted marker sequence repeats messages. This pulse resets the counters 11/12, thereby the control unit is in original condition.

After decoding the first and subsequent markers repetitions on the second input of the control unit pulses corresponding to the end of these markers. The impulse applied to the second input of the control unit goes to the S-input of the trigger 10 and at the counting input of the counter 12. This impulse suscitavit counter 12 and the decoder 13 produces zero output control potential at the input of element 1. The trigger 10 in this moment thrown in one state and at the counting input of the counter 11 through the element And 7 receives the clock. Bit counter 11 corresponds to the number of information symbols in a single repetition. On the arrival of the n-th pulse at the input of the counter he is thrown on his way out and clears the trigger which leads to interruption of the control potential P1 at the output of the element 1.

Thanks to all of the control potentials P1-P6 are valid only during the receipt and processing of characters. Control potentials P7, P8 are formed from the outputs of the elements OR 8, 9, the inputs of which receive the control potentials P1-P6. The sync pulses to the third input of the control unit should come in-phase with the information symbols received at the first input of the counter 5 and a casting unit 6 (Fig. 1). Thus the number of clock pulses and their phase coincides with the phase information symbols.

The device operates as follows: at the first input control unit receives the pulse, indicating that the communication channel is accepted marker of a sequence of repetitions of the message. This pulse resets the counters 11, 12. To the second input of the control unit comes impetus to indicate the presence of the token repeat. From that moment on the first output is managing the potential P1. The first clock pulse arrives at engraved counter and state clock inputs of the registers. Simultaneously with the first clock at the first (information) as an input signal of the first information symbol of the first repeat. If the first element is "1", the trigger 26 under the influence of the synchro is simultaneously using the control potential of the P1 signal is erased will be written into the trigger 28, and then in the register RG2 and also the cut of the clock is reset. Thus at the end of the first repeat, it will be recorded in the register RG1, and the corresponding signals s - register RG2. There follows a pause corresponding to the duration of the token repeat.

At the end token of the second repeat on engraved counter receives the first clock pulse simultaneously with the information symbol received at the first input of the counter, the second input receives a signal corresponding to the Erasure, the third input signal erase the corresponding character of the first repeat. Is forming a code number of units of the two repetitions with regard to their signals s and is recorded in the registers RG1, RG2. At the end of each symbol triggers reset the clock and ready to receive the following characters repeat. At the end of the second repetition code number of units of the first two iterations with a given signal s will be recorded in the registers RG1, RG2.

At the end of the third marker repeat at the first input of the counter received information symbols of the third repetition, the second input corresponding signals s, the third and the fourth input signal ID number of units of the first two pateamine issued the majority of the processing "three" on the output device. At the end of the third repeat in the registers RG1 and RG2 will be recorded code number of units of the first three repetitions.

With the advent of the fourth repeat it using the control potential of the P4 will be recorded in the register RG3, and the corresponding signals s - register RG4.

The fifth repeat is supplied to the first counter input to the second input receives the corresponding signals s, the fifth input signal of the register RG3 fourth repetition, the sixth entry corresponding to the fourth repeat of the erase signals. In the counter of the erase code is generated the number of units of the fourth and fifth iterations with regard to signal the erase and simultaneously with the entry in the registers RG3, RG4 arrives at the seventh and ninth input of the decision making unit, on the third and fifth input of which is fed code number of units of the first three repetitions, and the output block is the result of the majority processing "five".

On the arrival of the sixth repeat it arrives at the first input of the counter, the second input receives the corresponding signals s, on the fifth and sixth inputs enters the code number of units of the fourth and fifth iterations. The third and fourth outputs of the counter code is generated the number of units of the fourth, fifth, and sixth iterations with what about the block, and then on the output device. After the sixth repetition in the registers RG1 code will be written the number of units of the first three repetitions, in registers RG3, RG4 code number of units of the fourth, fifth, and sixth repeats.

With the advent of the seventh repeat it simultaneously with the entry in the register RG1, is supplied to the first input of the decision making unit, on the second and fourth input which receives the code number of units of the first three repetitions, and the sixth and eighth inputs enters the code number of units of the fourth, fifth, and sixth repeats. Using the control potential P1 and items 1-9, the decision of the majority processing "seven". At the end of the seventh repetition in the register RG1 is recorded seventh repetition, in the register RG2 - corresponding signals of erase in registers RG3, RG4 code number of units of the fourth, fifth, sixth repetition. After that, the process continues in a cycle.

DEVICE FOR CORRECTING ERRORS IN a MULTIPLE REPETITION of the MESSAGE, containing the first, second and third shift registers, the outputs of which are connected respectively to the first, second and third information input of the counter and the decision making unit, the output of the decision making unit is an information output device, PTA, the control unit and detector quality, the first input by the information input device, the first detector output quality is connected with the fourth information inputs casting block and counter, the second detector output quality is connected with the fifth information input counter, the first to fourth outputs of which are connected to information inputs respectively of the first to fourth shift registers, respectively, with the fifth - eighth informational inputs of the decision making unit, the output of the fourth shift register is connected with the sixth information input counter information and ninth input of the decision making unit, the first and second inputs of the control unit are the same control inputs of the device,the third input of the control unit and the second input of the detector quality are combined and a clock input of the first, fifth, and sixth outputs of the control unit are connected with the same control inputs of the decision making block and counter, seventh and eighth outputs of the control unit are connected with the same control inputs of the counter, the ninth input of the control unit is connected with synchronator counter and state clock inputs shift registers.

 

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