Digital coherent filter signals with discrete frequency shift keying

 

(57) Abstract:

Usage: in radio engineering. The inventive digital coherent filter signals with discrete frequency shift keying contains frequency recirculator, the first, second, and third switches, the first, second memory blocks, the first, second blocks of keys, the threshold block, the block decoders, N adders drives, block select the maximum number, the first, second, and third blocks formation threshold, the synchronization unit. The first forming unit threshold contains the first, second, and third switches, the block of N/2 numbers, the first, second adders, first and second dividers, the first, second multipliers, the first, second, and third registers, the unit selection minimum number, the divider with a variable division ratio, the memory block, the adder N/2. The unit minimum number comprises N Comparators, the first, second counters, the first, second, third keys, the first, second pulse shapers, the element OR NOT, the element OR the decoder, the trigger. Unit selection minimum number comprises N Comparators, the first, second, third keys, the driver gates, adder, the first, second delay elements, the first, second counters, decoder, fourth and ptor, divider, multiplier, first and second registers. Serially connected threshold block, the block decoders and the second set of keys contain the element OR the element, And the first, second and third Comparators, the first and second keys. The synchronization unit includes a master oscillator, the first, second, and third frequency dividers, the driver gates, the first, second, seventh ...keys, delay element, the shaper is the reference frequency, the pulse shaper. Agreed the filter at the expense of signal analysis in time-frequency plane in the bandwidth of the filter allows the shaper thresholds rejectee that does not depend on the level of the input noise, narrowband and impulsive noise, and to improve the noise immunity filter. 2 C.p. f-crystals, 7 Il.

The invention relates to radio engineering.

The purpose of the invention is the increased robustness.

In Fig. 1 shows a structural diagram of a digital matched filter signals with discrete frequency shift keying; Fig. 2 is a block circuit formation threshold; Fig. 3 is a block diagram of the block of N/2 minimum numbers of Fig. 4 is a structural block circuit diagram of the selection of the minimum numbers of Fig. 5 is a diagram of a third processing unit threshold; Fig. 6 is a diagram sequentially soy is SS="ptx2">

Digital coherent filter signals with discrete frequency shift keying contains frequency recirculator 1, the first comparator 2, the first memory block 3, the first block of keys 4, the second memory block 5, the second switch 6, the threshold block 7, block 8 decoders, the second set of keys 9, the third switch 10, N - adders-drives 11, block 12 select the maximum number, the first, second and third blocks 13-15 formation thresholds, block 16 synchronization.

The first block 13 formation contains the first threshold switch 17, the first adder 18, the first divider 19, the second switch 20, block 21 of the memory, the third switch 22, block 23 N/2 minimum numbers, the second adder 24, a second divider 25, the first multiplier 26, the first register 27, block 28 to select the minimum number, the divider 29 with a variable division ratio, the second multiplier 30, the second register 31, an adder 32, the third register 33.

Block 22 N/2 minimum number comprises N Comparators 34, the first counter 35, the first key 36, the second set of keys 37, the first shaper 38 pulse, third keys 39, scheme OR NOT 40, scheme OR 41, the second counter 42, a decoder 43, the second driver 44 of the pulse, the trigger 45.

Unit 28 to select the minimum number contains N comparatory 52, the first counter 53, the second counter 54, the decoder 55, the second delay element 56, the fourth and fifth keys 57 and 58.

The third block 15 formation threshold contains the block 59 keys, block 60 allocation N/2 minimum numbers, the adder 61, the divider 62, a multiplier 63, the first and second registers 64 and 65.

Serially connected threshold block 7, block 8 and the second set of keys 9 contains the element And 67, the first, second and third Comparators 68-1, 68-2 and 68-3, the first and second keys 69-1, 69-2.

Block 16 synchronization includes a master oscillator 70, the first, second and third frequency dividers 71, 72, 73, shaper 74 gates, the first, second, third, fourth, fifth, sixth, seventh keys 75-81, element 82 delay shaper 83 the reference frequency, the shaper 84 impulses.

The device operates as follows.

The input signal in the form of an additive mixture of the useful signal and noise received at the input frequency of the recirculator 1. The values of the envelope of the output of all N channels of frequency recirculator 1 in digital form at the same time with a frequency Fethe following elements of the signal through the first switch 2 is served in the buffer of the first memory block 3. The number of captured every moment count with frequency recirculate the aqueous recirculator 1, recorded in one continuous line, describing a single frequency signal.

When you have filled in all the N columns of the buffer of the first memory block 3, the first switch 2 pulse sequence Fto= Fe/N will be reset to the original state, and from the first memory block 3 by means of the first unit key 4 all numbers will be overwritten in the second memory block 5 so that the input signal can be processed in real pace of time. For time Tto= 1/Fto= Nethe binary number from the second memory block 5 to be processed and it should be ready for a new load.

From the second memory block 5 binary numbers are used for pre-forming threshold with the aim of rejectio interference for the subsequent formation of the response of the matched filter. At the first stage of processing are formed thresholds rejectee interference. To do this, the outputs of the second memory block 5 binary numbers served simultaneously on the first unit 13 according to the analysis of narrowband interference Pyon the second block 14 - the results of the analysis of impulse noise P and the third block 15 on the results of the analysis of the noise level PW.

Entity formation threshold of Pyaccording to the results of Naletov in one or two adjacent filter frequency recirculator 1 for a sufficiently long time t > >eits influence will manifest at the level of samples in one (or two adjacent) line of the second memory block 5.

Therefore, rejectee interference threshold is generated as follows. Calculates the average value of the samples ASRin each row of the second memory block 5. From all secondary selects the N/2 smallest. It is assumed that the selected line without narrowband interference. These N/2 lowest averages are averaged to N/2, are obtained from factorN1take into account possible excess noise above the signal, and this preliminary threshold of P.CR= 2A/N rejected all average ASRrow - those that exceed the preliminary threshold are discarded, and the average values that are less than the preliminary threshold, taken to formation threshold. To do this, they are summed, averaged, i.e., divided by the number average not exceeding preliminary threshold is taken with weightU2and fed to the input of the adder, the other input of which receives a binary number, characterizing the noise level. Output number from the output of the adder and is a threshold of Py.

All described operations are performed first block 13 in the following order. First commute are summed, averaged first divider 19 to N/2 and through the synchronously operating the second switch 20 average of the i-th row of a is A=Aj/N in the i-th cell of the memory block 21. Upon completion of all rows of the second memory block 5 and the filling of the cell unit 21 of the third switch 22 all average values of ASRat the same time served to the input unit 23. Unit 23 sequentially selects the N/2 lowest averages, which are fed to the input of the second adder 24. The sum of the N/2 smallest medium is applied to a second divider 25, the output of which through the first multiplier 26 weightN1is input to the first register 27, the output of which is connected to the reference input of the block 28. The number from the output of the first register 27 is an intermediate threshold (weighted average N/2 medium), which is used for further processing medium from the block 21.

When the preliminary threshold ends, all medium from the output of the block 21 are connected to the input unit 28. In block 28 is rejection, i.e., the exception processing when forming threshold of Pythose averages calculated across rows, which exceeds the amount of the preliminary threshold. Average values do not exceed it, i.e., characterizing the line, n is La 29, on the installation log which enters the number M equal to the number of averages, not exceeding the preliminary threshold. Private, not-average M value from the output of the divider 29, taken with weightU2the second multiplier 30 is applied to the input of the second register 31, which is memorized and stored until the time when the second block 15 will be formed this threshold. The number value from the output of the second register 31 and the number from the output of the second unit 15 and are summed in the adder 32, and its output as a final threshold value of Pyserved in the third register 33.

Average ASRare fed to the inputs of Comparators 34-1...34-N, at the second input of which is supplied with the output of the first counter 35, remember counting pulses which have passed through the first and second keys 36 and 37. Increasing the number on the counter (in the initial state is equal to 0) on one of the Comparators will exceed this number by the value of ASR. The output of that comparator will change the potential at the outputs, which is the first pulse shaper 38 will turn into a relatively short pulse, which opens the corresponding third key 39 and the aSRsupplied to the signal input key, prerecruit receipt of the pulses and to exclude almost simultaneous activation of two or more of the Comparators 34. These pulses through the circuit OR 41 fill the second counter 42 to determine the number of responding comparator. When this number reaches N/2, the decoder 43 will appear the drop of potential through a second pulse shaper 44 will reset the first counter 35 and the second counter 42, takes the trigger 45 in a state that by means of the second key 37 will cease to receive the pulses and will stop block 23.

Middle row ASRfrom the third comparator 22 serves to first inputs of Comparators 46 (46-1...46-N), to the other input of which is supplied with the output of the first register 27, playing the role of the threshold. Depending on the ratio of the values of the integers ASRand threshold comparator 46 will be established in various States. All the same, the outputs of Comparators 46 is connected to the first control inputs of the first key 47, the signal inputs are connected to inputs of the respective Comparators. On the second control inputs of the first keys 47 are gates with shaper 48, which starts counting the pulses passing through the second key 49. On the control input of the second key 49 is served, allowing for the potential to trigger 45 unit 23 after the end of calculation of prewar the UB> do not exceed the threshold, and the first inputs of the first keys 47 there is an enable potential from the output of the comparator through the opening keys of ASRpass to accumulate to the adder 50. Similarly, through the third keys 51, controlled by two inputs, are counting the pulses delayed by the first delay element 52. Number passed through the third keys 51 counting pulses, determined by the number in the corresponding position of the Comparators 46, is counted by the first counter 53, and the total number of the pulses counted by the second counter 54. When all channels will be scanned and the second counter 54 will accumulate the number of ASR, the output of the decoder 55 manifest difference of potential, which opens the keys 57 and 58 for the issuance of the contents of the adder 50 (dividend) and the contents of the first counter 53 (divisor), which receives the outputs of the block 28. The difference of potential is applied to the recording of the second register 31, the third block 15, the third switch 22 and the trigger 45 unit 23 to install them in their original state. From the output of the second delay element 56 period potential is supplied to the reset of the second counter 54, read from the second register 31 and to control entry to the third register 33.

Tre the second memory block 5 on each block of keys 59-i opened the outputs of the cells of one of the i-th row of the matrix. The composition of each block 59 are N keys in the number of cells in the row. On the control inputs of the block of keys 59-i opened the outputs of the block 60, controlled by the pulses from the outputs of the first imaging unit 38 unit 23. Control is performed so that the first row with the minimum average value of ASRthe pulse from the first shaper 38-i through the block 60, block keys 59-i and outputs of the cells of the I-th row of the second memory block 5 are connected to the inputs of the block 60 is the first choice, which works quite similar to the block 23. When the selected N/2 minimum number of the i-th row of the second memory block 5, terminates the access counting pulses keys 59-i are closed, the minimum number of hosts on the sum in the adder 61. When the unit 23 selects the following minimum average in the string, obviously not affected by narrow-band interference, again transmitted to the control unit 60 of the third unit 15, the following block of keys 59 and another N/2, the minimum number will be accumulated in the adder 61. Thus from each line with a minimum mean, obviously does not contain noise, is selected by N/2 minimum number obviously does not contain the useful signal and characterizing only the almost accurate assessment of the level of noise.

The number of adder 61 is averaged divider 62 and taken with weightWin the multiplier 63 is written in the first register 64 as a threshold of PW. When the first and second blocks 13 and 14 ends with the formation of numbers and write them in the second registers 31 and 31-1, the control inputs reading all of these registers (31, 31-1 and 64) receives the control signal. The number from the output of the second register 64 is supplied to the inputs of the adders 32 and 32-1, the second inputs of which receive respectively the number of the second registers 31 and 31-1. Number from the output of the adders representing the final value threshold of Pnand Pandaccordingly, serves to record and third registers 33 and 33-1. This completes the second stage of operation of the matched filter is the formation of all three thresholds: the threshold on the results of the analysis of narrow-band interferences Pythreshold analysis of impulse noise Pandand the threshold on the results of the analysis of the noise level PW.

In the next phase, the interference rejection and generation of the response of SF. The rapids with the first, second and third blocks 13, 14 and 15 serves on the reference input of the threshold unit 7. The second switch 6 with cells of the second memory block 5 to the input of the threshold b is s signal inputs of the first, the second and third Comparators 68-1, 68-2, 68-3 and signal input key 69-2. On the reference input of the first comparator 68-1 served with the first block 13 a threshold of Pyon second comparator 68-2 - threshold of PWwith the third unit 15, and a third comparator 68-3 - threshold of Pandwith the second unit 14. The outputs of the first and third Comparators (S < N) 68-1 and 68-3 and output (S > P) of the second comparator 68-2 filed on inputs trehochkovoy schemes And 67 in the block 8, the output of which is connected with the control input of the second key 69-2, at the signal input of which is fed an input signal from the second switch 6. If this signal satisfies the above conditions, i.e., exceeds a threshold of PWand, Vice versa, does not exceed the thresholds of Pyand Pandhe passes on the output of the second unit 9 keys. The outputs of the first and third Comparators (S > P) 68-1 and 68-3 and output (S < N) of the second comparator 68-2 connected to inputs of the circuit 66, the output of which is connected with the control input of the first key 69-1, so if the signal at the input of the threshold unit 7 meets at least one of these conditions, the output of the second block of keys 9 passes binary " 0 " supplied to the signal input of the first key 69-1. Thus, for the formation of the response of SF are not used timing noise is Loka key 9 is fed to the input of the third switch 10, the outputs of which are connected to the input of N adders drives 11. The third switch 10 it is N times slower than the second switch 6. The inputs of the second switch 6 are connected with the cells of the second memory block 5 in order diagonals, including cell numbers that correspond to the sequence of frequencies in the signal with the corresponding cyclic shift numbers of cells. So while the second switch 6 to the input of the threshold unit 7 transmits signals from cell one diagonal, the third switch 10 is connected to the input of one of the N adder-accumulator 11. Then, the second switch 6 begins to interrogate cells other diagonal, and the signals from these N cells serves to accumulate in the other of the N adders drives 11. N adders drives 11 to form directly the response of SF. When we surveyed all N x N cells of the second memory block 5, is formed of the sum of all N adders-drives 11, block 12 selects from these amounts is the greatest, which is the response of the matched filter.

All nodes of the matched filter is synchronized with control signals from the output of block 16. Oscillations from oscillator 70 through the frequency divider arrives at the shaper 83, which is designed to genericoviagra sequence, which is received in the second and third frequency dividers 72 and 73. With an output of the third divider 73 pulse sequence is supplied to the driver 74. The gate with its output set timing nodes of the matched filter, determining the time of formation of the medium-ASRthe formation thresholds of PyPandand PWand time rejectee interference and the formation of the response of SF. The gates control the operation of all keys through which a pulse sequence with the output of the second divider 72 are fed to the nodes of the matched filter. The required ratio between the frequency of the pulses in the sequence determined by the second frequency divider 72.

1. DIGITAL COHERENT FILTER SIGNALS WITH DISCRETE FREQUENCY shift KEYING containing serially connected frequency recirculator, the first switch, the first memory block, the first block of keys, the second memory block, the second switch, the threshold block, the block decoders, the second set of switches and the third switch, and N adders drives the outputs are connected to the matching unit select the maximum number whose output is the output of the digital matched filter, and the first and second blocks for the formation of blocks forming rapids, the outputs of which are connected with the control input of the threshold unit, and the second output of the second processing unit threshold is connected to an additional input of the first forming unit threshold, with the first group of outputs of the synchronization unit connected with the control inputs of the frequency of the recirculator, the first engraved which is connected to the first engravida synchronization unit, the second engraved which is connected to the coupled between a second synchronator frequency recirculator and pulsing the input of the first comparator, the installation log which, combined with synchronator the first block of keys, installation of the inputs of the second and third switches, and N adders drives, connected with the eighth engravida synchronization unit, installation input of the first forming unit threshold is connected with the third synchronator synchronization unit, pulsing the input of the second switch to the fourth output of the synchronization unit, and the United synchronicty the first and second blocks forming thresholds connected with the seventh engravida synchronization unit, wherein, to improve noise immunity, it introduced the third block formation threshold, the signal input of which is with the od of the third processing unit threshold combined with the additional input of the first forming unit threshold, the output of the second switch is additionally connected to the second signal input of the second block of keys, the output of the third switch with the signal inputs of the N adders drives, pulsing inputs which are connected with pulsing input of the second switch group pulse output, and the output control entry and exit control reading of the first forming unit threshold connected to respective inputs of the second forming unit threshold setting input of the third processing unit threshold combined with the same input of the first forming unit threshold, United first pulsing inputs of the first and third blocks formation threshold is connected with the fifth engravida synchronization unit, combined second pulsing the first input and the first pulsing the input of the third blocks forming threshold with the ninth engravida synchronization unit, combined counting input of the first and third blocks forming rapids - tenth engravida synchronization unit, the counting input of the second processing unit threshold connected with the eleventh engravida synchronization unit, pulsing the input of the third switch - sixth engravida synchronization unit, with sedimentologist under item 1, characterized in that the first processing unit threshold includes serially connected first switch, an adder, a divider, a second switch, a memory block, the third switch, the block of N/2 minimum numbers, a second adder, a second divider, multiplier, register, the output of which is connected to the reference input of the unit selection minimum number of signal inputs of which are connected with the second group of outputs of the third switch, and outputs - with cascaded divider with a variable division ratio, a second multiplier, a second register, a third adder and a third register, the output of which is the output of the shaping unit threshold, moreover, additional pulsing outputs of the block of N/2 minimum number connected with kreisiraadio inputs of the third switch, the second adder, the first register and the block of N/2 minimum number of additional kreisiraadio the outputs of which are connected with synchronically second and third registers, the third switch and the block of N/2 minimum numbers.

3. The device under item 1, characterized in that the second processing unit threshold contains N blocks of keys, the inputs of which are the inputs of the processing unit threshold, and whele included the adder, divider, multiplier and the first and second registers, and the output of the second register is the first, and the output of the first register, the second output unit formation threshold, N/2 minimum number connected with control inputs of the respective blocks of keys, and their combined pulsing outputs with engravida adders.

 

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