Device for transmitting and receiving digital data

 

(57) Abstract:

The invention relates to telecommunication and can be used in communication systems. The purpose of the invention is improving the noise immunity of the device due to the error correction code groups pseudorandom sequence (SRP). The goal of the invention is provided by introducing into the device on the transmission side of the distributor 13 pulses, the registers 141-14Kforming a parallel group, unit 15 of the switching element And 16, the divider 17 frequency element OR 18, valve 19 pulses at the receiving side elements 32 and 34, block 35 of the write-read register 36, a memory 37, block 38 switching and shaper 39 pulses, and in block 23 forming groups SRP entered the trigger, codebreaker and elements And forming a parallel group, block 15 switching on the transmission side contains K groups of parallel elements And one group of parallel elements OR and the block 38 switching on the receiving side contains two groups of parallel elements And one group of parallel elements OR, the selector 20 SRP contains three pulse shaper, the four elements And two elements OR two triggers, iroutes pulses, four trigger, the three elements, two elements 2-2I-OR two elements AND two of the inverter. The invention consists in the formation of the code groups of the different phases of the SRP of the same length, corresponding to the initial condition of the cells of the shift register generating the SRP, with the possibility of correcting errors of a certain multiplicity arising from the transfer of these code groups of the SRP, as well as in the Union of several groups of different phases of the SRP under one marker signal. 3 C.p. f-crystals, 7 Il.

The invention relates to telecommunication and can be used in systems for the transmission of discrete information.

A device for transmitting and receiving digital information containing on the transmission side block selection signal front, trigger, three elements And summarizing the counter, the pseudo-random sequence generator (SRP), the delay unit, subtractive counter and the member OR, at the receiving side, the two elements, And two triggers, summing counter, generator, SRP, inverter, drive, subtractive counter and decoder [1].

However, the known device has a relatively low data transmission rate, as one binary bit kodiruemogo the information about the duration of this parcel. This device has low noise immunity, since the distortion of any code word SRP leads to the loss of phase values of the SRP.

The closest to the technical nature of the present device is a device for transmitting and receiving digital information containing on a transmitting side of the first element And summarizing the counter element OR the second element And the generator of the SRP, the pulse shaper, the pulse counter, the first additional element OR, modulo two, the second additional element, And first and second additional delay blocks, at the receiving side the selector SRP, block compare, trigger, element, And summing counter, drive, additional trigger generator SRP, the shift register, the first codebreaker, the second shift register, the third codebreaker, the counter pulses [2].

However, the known device also has low noise immunity.

The purpose of the invention is improving the noise immunity of the device due to the error correction code groups of the SRP.

In Fig. 1 presents a functional diagram of a device for transmitting and receiving digital data; Fig. 2 is a functional block diagram of formirovaniia SRP; in Fig. 6 shows timing diagrams illustrating the operation algorithm selector SRP; Fig. 7 is a functional block diagram of the recording-reading.

The device comprises in the transmitting side of the first element 1 And summarizing the counter 2, the second 3 third 4 fourth 5 elements And the imaging unit 6 pulses, subtractive counter 7, the first 8 and second 9 blocks of the delay generator 10 SRP, the adder 11 in module two, the first element OR 12, the first valve 13 pulses, the group of registers 141-14TO(forming a parallel group), the switching unit 15, the fifth element And 16, the divider 17 frequency, the second element 18, the second valve 19 pulses at the receiving side the selector 20 of the SRP, the first 21 and second 22 blocks comparison unit 23 forming groups of the SRP, the counter 24 pulses, the trigger 25, the first element And 26, the first drive 27, the first 28 and second 29 and 30 third registers, codebreaker 31, second 32 and third 33 and 34 fourth elements And the block 35 record is read, the fourth register 36, the second drive 37, block 38 switching the imaging unit 39 pulses. The transmission and reception side device connected via the channel 40 of the connection.

Block 23 forming groups SRP (Fig. 2) contains the generator 41 of the SRP, the trigger 42, codapane contains To groups of parallel elements and 451-45TOand one group of parallel elements OR 46.

Block 38 switching (Fig. 4) at the receiving side contains two groups of parallel elements And 47 and 48 and one group of parallel elements OR 49.

The selector 20 SRP (Fig. 5) contains the first 50, second 51 and third 52 shapers pulses, the first 53 and second 54, 55 third and fourth 56 elements And the first 57 and second 58 elements OR the first 59 and second 60 triggers the first 61 and second 62 the pulse generator, the first 63 and second 64 and third 65 the pulse counter and the first 66 and second 67 registers.

Block 35 of the write-read (Fig. 7) contains the first 68, 69 second and third 70 shapers pulses, the first 71 and second 72, 73 third and fourth 74 triggers, the first 75, 76 second and third 77 elements, And the first 78 and 79 second elements 2-2I-OR, the first 80 and 81 second elements, the first 82 and second inverters 83.

Device for transmitting and receiving digital data works as follows.

The transmitted digital signal is supplied to the information input device (Fig. 1), i.e., the first input of the first element 1. At its second input with the reading of the input device enters a periodic sequence of counting pulses, the period sledd device receives the pulses of the reference sequence, the repetition period of which Tabout. In the time interval between any reference pulses cannot be more than one front of the transmitted digital signal. With the arrival of the reference pulse to the input of the first dispenser 13 pulses, the latter is excited by one of the outputs, resulting in a corresponding register 14 is written information that was in summarizing the counter 2 (in binary code - the duration of a single potential source of a discrete signal in a period between two adjacent reference pulses), then the counter 2 is reset to zero, as each reference pulse arrives at his detainee Abdoulaye entrance. While counting the pulses through the first element 1 And is fed to the counting input of summing counter 2, if an item 1 open a single potential of the transmitted digital signal.

The transmission cycle is the time interval in the reference intervals Taboutand begins with the appearance of a signal at the first output of the distributor 13 pulses, in which information about the duration of a single parcel during the reference interval of duration Taboutof the sum counter 2 is rewritten in the first register 141from a parallel group. One is one, transferring the counter 7 in its ultimate state, which decreases with the arrival of pulses at its inverted counting input. Simultaneously, the divider 17 frequency and the second valve 19 pulses are set to the initial state. The signal from the first output of the distributor 19 pulses commutes initial phase number of outputs of the first register 141 from a parallel group on information outputs of the switching unit 15 and further information on the inputs of the generator 10 of the SRP. The pulse passing from the shaper 6 pulses through the second element OR 18 at the inverse input record generator 10 SRP, the initial phase number is recorded in the cells of a register (not shown) of the generator 10 of the SRP.

A single potential direct output of the counter 7 is supplied through the first element OR 12 in the channel 40 of communications and forth on the receiving side. This impulse is a marker, signaling to the receiving party of the early arrivals To the code groups of the SRP. To clock input device receives the high frequency clock pulses (VTI), the length of which is equal to the half period tabout. The rear front of the second pulse of the sequence VTI, which is supplied to the inverse of the counting input of the counter 7 via the second is estwenno zero and singular potentials. The time delay of the second delay block 9 is selected more time delay of the first delay unit 8 and less than half the period to. A single potential with inverted output of the counter 7 has a third 4 fourth 5 fifth 16 elements I. the clock generator 10 of the SRP and to the input of the divider 17 frequency start coming VTI. Under the action of these VTI is the phase shift of the SRP relative to the initial recorded in the generator 10 of the SRP, the number of gradations corresponding to the length of the code word is selected SRP sufficient for error correction of a certain multiplicity. For example, for a SRP of length M = 7 for the correction of single errors you need minimum code distance between code groups of phases SRPmin= =3, which is provided by the choice of the length of the code group l = 6. For example: if the SRP is generated based on the generating polynomial P(x) = x3+ x + 1 and has the form 1011100, the code for the initial phase 010 combination SRP n-1 = 6 characters looks 010111, and to code the initial phase 111 corresponding to the combination of SRP - 110010. In the adder 11 in module two and the fourth element 5 is formed code group SRP iimpulse code, through which the first element OR 12 is thrown into the channel 40 due immediately for marker C is UB> from a parallel group during the second calibration interval through pulse recording with the incoming second output of the distributor 13 pulses, then during the interval of the excitation of the second output of the distributor 19 pulses (after calculation of the divider 17 cha - frequency l pulses) occur the formation of the second code-group of SRP and issuing it in the channel 40 due immediately after the first group according to the algorithm described above. In the role of signals that writes code initial phase in the generator 10 of the SRP and the changing conditions of the distributor 19 pulses are the pulses generated at the output of the divider 17 frequency. This happens until then, until you interviewed last K-th register. 14TOfrom a parallel group, after which the forming cycle To code groups of the SRP under one marker signal will be repeated.

Taken from the output of the channel 40 communication sequence is supplied to the selector 20 of the SRP, where are consistently the character code groups SRP formed on the information outputs of the selector 20 of the SRP. After defining the characters of each group of the SRP with the additional output of the selector 20 of the SRP signal sets the counter 24 pulses in the initial state, and the trigger 25 is the th clock input devices on the inverse of the counting input of the counter 24 pulses, clock generator 41 SRP and trigger block 42 23 forming groups SRP begin to enter the pulse repetition period whichoproducing a shift adopted by the (previous) combination of SRP's recollection. The shift is performed to match the specified sequence respectively with the information outputs of the selector 20 SRP and block 23 forming groups SRP) in the first block 21 comparison or to the number of mismatched characters combinations specified, not exceeding the threshold (min- 1)/2. Up to this match, the trigger 42 of the block 23 is in a single state, the opening elements 441-44n-1parallel groups, resulting in their outputs is formed by the combination of the repeating that is formed on the information outputs of the generator 41 of the SRP. With the arrival of the M-th pulse at the first output of the counter 24 pulses is formed of a single signal that sets the trigger 42 of the block 23 in the zero state, so that the elements 441-44n-1closed and on the information output unit 23 is formed of a zero combination in addition to the M combinations of the previously generated by generator 41 of the SRP. With the arrival of (M+1)-th pulse at the second output of the counter 24 formiruete (min- 1)/2 symbols matching with the one which was adopted from the channel 40 due selector 20 of the SRP.

If in block 21 comparison comes the moment of coincidence of the combinations or the number of mismatched characters does not exceed the value (min- 1)/2, at its output, a signal is generated that sets the trigger device 25 in the zero state. As a result, the imaging unit 39 generates signal pulses, write the initial code, the received code group of the SRP from the block 23 in the fourth register 36, where this information is then overwritten in the first 27 or 37 second drive, and this overwrites the block controls 35 write-read. The information in the register 36 is a binary code combination entered on the transmission side in summarizing the counter 2 at the time of the reference interval. The presence of two drives due to the fact that the time of transmission of the code group of the SRP, is equal to the value of ltaboutthat is less than the reference interval Tabout. Therefore, when the continuous analysis of the code groups of the SRP are the time periods of the reference intervals Taboutduring which is necessary to form simultaneously two adjacent initial code corresponding to the adjacent code groups of the SRP.

When the transmitting side receives the pulses of the reference sequence with the same period of Tabout. Each such pulse is passed to the block 35 of the write-read, which generates at its first or second additional output signal resolution reading information from the first 27 or 37 second drive through block 38 switching depending on which drives the register 36 recorded before. Information from the block 38 switching is overwritten in the first register 28, which is the next reference pulse corresponds to the second register 29, and then in the register 28, the information is updated in the second code group.

For decoding the received binary combinations and deciding the polarity of the proposed signal is analyzed according to two successive code groups, recorded respectively in the registers 28 and 29. The second block 22 comparison summarizes the number recorded in the registers 28 and 29, and the specified amount compares with the number n-1. If the specified amount exceeds or equal to the number n-1, it means that on the transmission side has been coded unit sending a discrete signal of duration TPOSduring the reference time interval, and (n-1) TPOSand it was located in the middle part of the analyzed time interval EWMA does not exceed the number n-1, it is located in the middle part of the analyzed interval of duration 2Taboutwas coded zero signal with a duration of TPOSand (n-1) < TPozo. At the output of the second unit 22 comparison produces a zero signal. Codebreaker 31 performs the function of the inverse transform of the binary code stored in the register 29, a corresponding code number of "units" on their outputs, distributed depending on the additional signal from block 22 comparison at the start or end rooms outputs codeprivate 31. Information from codeprivate 31 in parallel code is written to the register 30 by the reference pulses received at its input records in the first (n-1) bits of the register 30, and reads the information from the last n-th digit of the register 30 in the sequential code on the information output device through the read pulse period , coming to the shift input of register 30 with additional reading of input devices.

In Fig. 6 shows timing diagrams illustrating the operation algorithms of the device in General, and the selector 20 SRP in particular for the case when the basic premise of the original disks theabout+ = 7, where Taboutthe repetition period of the reference pulses ( Fig. 6 (a). When the repetition period VTI to= (6 )/ 7 (Fig. 6). While the first reference interval of the original signal (Fig. 6g) strobiles one Gating pulse, which corresponds to the binary code (001). During the next second reference interval of the reference signal strobiles six Gating pulses, which corresponds to the binary code (110). In Fig. 6D shows diagrams iimpulse code, transmitted through the channel 40 of the connection. Thus in Fig. 6D shows the case when the marker signal M is transmitted two (K = 2) code SRP group a and b corresponding to the original binary codes, i.e., (001) ->> A(101110) and (110)->> ->> (110010).

Taken from the output of the channel 40 communication sequence (Fig. 6D) is supplied to the selector 20 of the SRP, which is determined by the phase of the SRP as follows. Taken from the channel 40 communication sequence (Fig. 6D) is supplied to the input shapers 50 and 51 of the pulses and the element 55. At the output of the shaper 50 pulses are distinguished front the fronts of the pulses of the received sequence (Fig. 6E), and the output of the shaper 51 pulses are allocated back wavefronts accept who I formed a zero signal, the opening element And 55. Thus, at the counting input of the counter 63 pulses begin to flow from the generator 61 pulses, whereby after a period of time lying in the range of taboutup to 1.25 toat the exit of the overflow of the counter 63 is formed pulse (Fig. S) up until the counter 63 will not drop to zero rear front marker signal at its inverted Abdoulaye entrance. The rear edge of the pulse from the output of the counter 63, the trigger 60 is translated in one state (Fig. 6I), which together with the zero output of counter overflow 64 pulses opens the item And 56 and runs the generator 62 pulses. The trigger 60 is in a single state during the entire period of analysis To groups of the SRP. From the output of the generator 61 pulses through the open element And 56 at the counting input of the counter 64 pulses begin to enter the pulses and the interval of time lying in the range of 0.5 toto 0.75 toat the exit of the overflow of the counter 64 receive a single signal (Fig. 6L), the opening elements 53 and 54 and the locking element And 56. As a consequence, on a unit and a zero trigger inputs 59 receives signals (respectively Fig. 6m and 6N), which moves it accordingly in the unit and zero E on the trigger inputs 59, unite in element 57 (Fig. 6P) and then arrive at the inverse input register entries 66, whereby the reproduced information groups SRP of trigger 59 in sequential code is overwritten in the register 66 (Fig. 6R). Pulses from generator 62 pulses occur rewriting in parallel code information from the register 66 in register 67, which acts as an intermediate carrier of information, and the counter 64 to prepare it for analysis of the following character groups of the SRP. The pulses generated by the generator 62 pulses form the end of the analysis interval of the next group of SRP. After counting the pulses from generator 62 counter 65 pulses at the output of the latter is formed of a single signal, after separation of the leading edge which driver 52 pulse occurs prohibition pulse shaping generator of the SRP, prepared for analysis next To the code group of the SRP.

The operation unit 35 of the write-read (Fig. 7) is as follows. Suppose that triggers 71-74 block 35 are in the zero state. Upon receipt of the signal from the inverted output of the trigger 71 is translated in one state. Then, through the shaper 69 pulses and the elements of the provided information from the fourth register 36 of the device. Simultaneously, in one state means the trigger 72 unit 35, i.e., zero potential with direct outputs trigger 73 and 74 are formed on the output element AND IS NOT 81 single potential, opening the first circuit And element 2-2I-OR 78, through which also passes the output signal from the shaper 68 pulses to an inverse input of the trigger 72. If then again in block 35 receives the signal recording, in one state means the trigger 73 signal from the output of the shaper 68 pulses through the open element And 75. The element 75 is opened by a single signal from the direct output of the trigger 71. Further, similar to the recording signal through the shaper 70 pulses and the element And device 34 is fed to the input of the recording of their second drive device 37, which is overwritten with the information from the fourth register 36 of the device. The trigger 74 remains in the zero state. At the output of inverter 82 is a single potential, and the output of inverter 82 is zero.

Upon receipt of the signal read from the auxiliary input reference pulse device information through the public members And 47 is overwritten in the register 28 of the device from the first memory 27. The signal read through the outdoor element of the second state of the trigger 74. If after this comes another signal recording, the information is again written in the first memory 27, the trigger 71 is in a single state, and the trigger 72 is zero, because the first schema And element 2-2I-OR 78 is closed zero output signal from the element AND NOT 81. At the output of inverter 82 is zero potential, and the output of inverter 83 - unit. In this situation, upon receipt of the next signal readout information already in the public members And 48 is overwritten in the register 28 of the device with a second drive 37, and from the register 28 of the previous information is overwritten in the register 29.

Feasibility advantage of the inventive device in comparison with the device of the prototype lies in the ability to combine multiple code groups of the SRP, which carry information about the duration of a single parcel under one marker signal defining the beginning of the analysis of these code groups, and the ability to increase the noise immunity of the transmitted information by correcting errors of a certain multiplicity, resulting in transmitted over the communication channel code groups. Consequently, the gain for a consolidated value of a specific error in the proposed unitary can be obtained from the use of the proposed device, is that possible to transmit information in less time with high reliability.

1. DEVICE FOR TRANSMITTING AND RECEIVING digital INFORMATION containing on a transmitting side of the first - fourth elements And summarizing the counter, a pulse shaper, subtractive counter, the first and second delay blocks, the pseudo-random sequence generator (SRP), modulo two, the first element OR, with informational reading and support the device inputs are, respectively, the first and second inputs of the first element And boleushim input sum counter, a counting input connected to the output of the first element And the clock input to the device through the second delay unit is connected to a second input of the third element And the first input of the second element And whose output is connected to the inverse of the counting input of subtractive counter, and the second input through the first delay unit with direct access subtractive counter, set input of which is connected to the output of the pulse shaper, and the inverted output to the first inputs of the third and fourth elements And the output of the third element And is connected to the second input of the modulo two Summator modulo two, the output of which is connected to the second input of the fourth element And whose output is connected to the first input of the first element OR the output of which is connected to the communication channel at the receiving side is the selector pseudo-random sequence, the first and second blocks of the comparison, the first element And the first input of which is complementary clock input of the block forming groups of pseudo-random sequence, the clock input of which is connected with the output of the first element And the pulse counter, the trigger, the first drive, the first through third registers and codebreaker, information input selector pseudo-random sequence is connected to the communication channel, an additional output connected to boleushim input of the pulse counter and with a single input trigger, and the outlet of which is connected to the second input of the first element, And a zero input - output of the first block of comparison, the first and second group of inputs of which are connected to data outputs, respectively, of the selector pseudo-random sequence and block the formation of groups of pseudo-random sequences, information outputs of the first and second registers are connected respectively with the first and second groups is s which is connected to the information output of the second register, and outputs - information input of the third register, the shift input of which is more reader input devices, and output information output device, wherein, to improve the noise immunity of the device due to the error correction code groups pseudorandom sequence entered on the transmission side of the first and second valves pulses, the group of registers, switching unit, the fifth element, And the frequency divider and the element OR Abdoulaye input sum counter is connected to the first input of the pulse distributor, the respective outputs of which are connected to the input record corresponding register group, the outputs are connected to the appropriate inputs of the switching unit, the information outputs of which are connected to information inputs of a pseudorandom sequence generator, an inverse input record which is connected to the output of the second element OR the input of the first register group through the pulse shaper is connected with the installation of the inputs of the frequency divider and the second pulse distributor and the second input of the second element OR the first input of which is connected to the output of the frequency divider and to and the input of the second delay unit is connected to a second input of the fifth element And whose output is connected to the input of the frequency divider, the first input of the fifth element And connected to the first input of the fourth element And the second input of the first element OR is connected to the input of the first delay unit, the bit outputs of the sum counter is connected to information inputs of the registers of the group, at the receiving side entered the second to fourth elements And the write block-read, a pulse shaper, a fourth register, a second drive and switching unit, a code output unit for forming groups of pseudo-random sequence is connected with the information input of the fourth register, the outputs of which are connected to information inputs of the first and second drives the outputs are connected respectively to the first and second groups of inputs of the switching unit, the outputs of which are connected to information inputs of the first register, the input record which combined with the inputs of the recording of the second and third registers, with additional support by the input device and with the reading log block write-read log records which is connected to the inverse output of the trigger directly and through the pulse shaper is connected to inputs of record, respectively, the first and second drives, the output of the first element And is connected to the direct input of the second element And whose output is connected to the inverse of the counting input of the counter pulses, the first output of which is connected with the mounting unit forming groups of pseudo-random sequence, the second output of the pulse counter is the output "Error" device and is connected to the inverted input of the second element And the second inputs of the third and fourth elements And connected respectively to first and second outputs of the write block-read, first and second complementary outputs of which are connected respectively with the first and second inputs of the switching unit, the information inputs of the second register connected to respective outputs of the first register.

2. The device according to p. 1, wherein the unit for forming groups of pseudo-random sequences, the inverse clock input is a clock input unit for forming groups of pseudo-random sequence, the trigger, the group of items and codebreaker, and an installation unit for forming groups of pseudo-random sequence is the zero input of the trigger, a single input connected to the inverse of t is that the inputs of the respective elements And groups outputs information output unit for forming groups of pseudo-random sequence code outputs which are the outputs of codeprivate, the inputs of which are informational outputs of the pseudorandom sequence generator, direct trigger is connected with the first inputs of elements And groups.

3. The device under item 1, characterized in that the selector SRP contains the first-fourth elements And the first through third pulse shapers, the first and second pulse generators, the first and second elements OR the first and second triggers, the first and second registers and the first through third pulse counters, information input selector cap is the first input of the third element And the inputs of the first and second pulse shapers and boleushim negative input of the first counter pulse output overflow which is connected with the inverse of the single input of the second trigger and the entrance to the third element, And the output of the first pulse generator is connected to the second inputs of the third and fourth elements And the outputs are connected to the counting inputs respectively of the first and second pulse counters, the outputs of the first and second pulse shapers is responsible with unit and zero inputs of the first flip-flop and to the input of the first element OR the output of which is connected to the negative input of the first register and the first input of the second element OR the direct output of the first flip-flop is connected to the serial input of the first register, the information outputs of which are connected to the same inputs of the second register, the outputs of which are the outputs of the selector SRP, and an inverse input record combined with the additional output of the selector SRP, with the second input of the second element OR, with the output of the second pulse generator and a counter input of the third pulse counter, the output of the second element OR is connected with boleushim input of the second pulse counter, output overflow which is connected to the negative input of the fourth element And with the second inputs of the first and second elements And direct the output of the second trigger connected to the first input of the fourth element And with the triggering input of the second pulse generator, the inverted output of the second trigger is connected with boleushim input of the third pulse counter whose output through the third pulse shaper is connected with the inverse of the zero input of the second trigger and prohibiting input of the second pulse generator.

4. The device under item 1, characterized in that the recording unit with the options And the first and second elements 2 - 2I - OR, the first and second elements and the first and second inverters, the input of the recording unit of the recording-reading is the input of the first pulse shaper, the output of which is connected with the inverse of the single input of the first trigger and the first inputs of the first circuit And the first element 2 - 2I - OR and of the first element And the input of the read block write-read is the third inputs of the second and third elements And the outputs of which are connected with the inverse of zero inputs respectively of the first, second and third, the fourth trigger and with the first inputs of the second circuits And respectively the second and first elements 2 - 2I - OR, the outputs of which are connected with inverse isolated inputs, respectively, the fourth and second triggers, direct the first flip-flop through a second pulse shaper is connected to the first output of the write block-read and is directly connected to the second inputs of the first and second elements And the first element AND - NOT and the second circuit And the first element 2 - 2I - OR, the output of the first element And is connected to a second input of the first circuit And the second element 2 - 2I - OR with a single inverse input of the third trigger, direct access through third formirovanii third element, And the second element AND - NOT and the second circuit And the second element 2 - 2I - OR direct outputs of the second and fourth trigger is connected with the first inputs respectively of the second and third elements And respectively the first and second elements AND IS NOT, the outputs of which respectively through first and second inverters are connected respectively with the first and second additional outputs of the write block-read and directly connected respectively with the first and second inputs of the first circuits And respectively the second and first elements 2 - 2I - OR.

 

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4 cl, 16 dwg, 6 tbl

FIELD: communications engineering; simulating digital communication channels with separate and grouping errors.

SUBSTANCE: proposed method includes evaluation of set of communication channel states S0,S1, ..., Sm - 1 and calculation of conditional error probabilities P(e/s) in each state s" i = 0, ..., m - 1 of communication channel, and error acquisition in communication channel in compliance with conditional error probability for current state of communication channel; in the process probability of error-free interval p(0i) of i bits is found, and conditional probabilities p(0i1/11), p(0i1/01) of error-free intervals of i bits are calculated with respect to them basing on probabilities p(0i) and using recurrent rules during each current time interval and preceding one on condition that for error generation use is made of two states of communication channel corresponding to combination of errors 11 or 01; random number p uniformly distributed within interval between 0 and 1 is generated; conditional probabilities p(0i1/11), p(0i1/01) are summed up starting from i = 0 resulting in sequence 0k1 that constitutes bit-by-bit stream of communication channel errors.

EFFECT: enhanced speed.

1 cl, 1 tbl

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: coding in communication systems.

SUBSTANCE: proposed partial reverse bit-order interleaver (P-RBO) functions to sequentially column-by-column configure input data stream of size N in matrix that has 2m lines and (J - 1) columns, as well as R lines in J column, to interleave configured data, and to read out interleaved data from lines.

EFFECT: optimized interleaving parameters complying with interleaver size.

4 cl, 7 dwg, 3 tbl

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