Device for multi-channel decoding

 

(57) Abstract:

The device relates to telecommunications, and in particular to systems transmit-receive data, and can be used to group devices protection against errors, group devices receive discrete data. The invention solves the problem of improving the performance of the decoding information. The device contains three counters 1, 8, 17, a decoder 3, three decoder 2, 4, 19, the five elements And 5, 10, 11, 13, 15, the trigger 9, the two elements, OR 12, 14, two block 7, 18 RAM and two multiplexer 6, 16. 3 Il.

The device relates to telecommunications, and more specifically to systems transmit-receive data, and can be used to group devices protection against errors, group devices receive discrete data.

Known multi-channel device for transmitting and receiving digital data containing the matching blocks, switch gear, control unit, switcher, analyzer, rebound, block mates with the line receiver code, a distributor, a codec colonizability channels, codec code sensitive channels, random access memory unit, the imaging unit address buffer unit, the selector of the call, the memory block with random sampling, the op is headed the remainder of this device are the complexity - large hardware cost, low performance - the impossibility of decoding received data at high speeds in communication channels.

The closest to the technical nature of the claimed is a multi-channel decoder, comprising a generator of clock pulses, the iteration count of decoding, the distributor channels (counter), input switch, a decoding unit, a decoder pulse recording, the adder, random access memory and the switch address-of-record [2].

The disadvantages of this decoder are low speed decoding information received simultaneously over N channels, large equipment costs (RAM per channel) and the impossibility of decoding information when applying for the nonmultiple speeds from independent sources.

The aim of the invention is to improve the performance of your device.

In Fig. 1 shows an electrical functional diagram of the device for multi-channel decoding, Fig. 2 - electrical functional diagram of the third counter (sequence length), Fig. 3 is a timing diagram of the operation of the device.

The device comprises a first counter 1 (the time interval for the CRRF 6, RAM 7, the second counter 8 (address), IK-trigger 9, the first and fourth elements And 10 and 11, the second element OR 12, the second And gate 13, the first element OR 14, the fifth element And 15, the second multiplexer 16, the third counter 17 (length sequence), block 18 RAM and the third decoder 19.

The decoder 3 is a set of individual D-flip-flops and adders modulo two (Polyommatus), which are connected by the known rules for the creation of digital decoders, communications (connections) which are formed in accordance with the form of cyclic polynomial (polynomial), the degree of which corresponds to the number of bits of the shift register is made on the D-triggers.

The counter 17 (Fig. 2) is implemented in a separate IK-triggers to the interconnected inputs reset which element is NOT connected. The inputs and outputs of the triggers poluchautsa using a multiplexer 16.

The device operates as follows.

At first (clock) input device continuously receives a sequence of clock pulses T 1 with a frequency of 2048 kHz (Fig. 3).

After the reset of the counters 1 and 8 pulse cycle frequencies (8 kHz) supplied to the second input of the reset device, the counter 1 uscity is at its counting input of every sixteenth pulse from the output of counter 1 generates the address (in binary code) temporary channel (VC), the number of which corresponds to the N-number (odd or even) group timeslots tract.

For the duration of each VC on the outputs of the decoder 2 cyclically formed corresponding signals on the first output of the first (zero) on account of the time interval, the second output - eighth, and the third output - ninth (Fig. 3).

On the third (information) input device receives information of the sequence group tract containing data bits is odd (or even) channel intervals. It is associated (synchronized) by a sequence of clock pulses T2, coming in fourth (clock) input of the device. The clock pulse frequency T2 (2048 kHz) is identical to T1 in duration, but are shifted in time and not alternate between one and the other sequences.

The information sequence from the third input device is supplied to the information input of the decoder 3 and the I-input of the trigger 9. When I input trigger 9 "checkbox", which is always a bit of logical "1", the trigger 9 is switched on the trailing edge of the pulse T2 in one state. As a result, after the element 11 And the element OR 12 is allowed to pass to them the coming of the recording portion of the information in the register (or triggers) of the decoder 3, that goes for the "box" in the serial code, and the counter 17 counts kolichestvo bits (or length) of this pieces of information.

The value of bits in the information sequence VK correspond to the values of bits in the corresponding time interval in discrete communication channel, and the distribution and the number of bits in this VK depends on the speed of receiving information. For example, if one value of speed (2400 bps) information is received in a portion of one of the VC, see "the box" and one bit of information, and at another speed value (48000 bits/c) - "the box" and seven bits of information.

Until receipt of the information in the decoder 3 it is overwritten piece of information (for the same VK) stored in the RAM 7, and the counter 17 is overwritten status (binary code) that is stored in the block 18. This operation is performed under the action of the signal generated at the first output of the decoder 2. The signal at the control inputs of the multiplexers 6 and 16 (for Priklyucheniya information from the RAM 7 and the block 18 respectively) and through the element OR 14 to the input of the chip select RAM 7 and the block 18. When matching on the item And 10 of this signal and the clock pulse T 2 (on its edge) portion of the information Zap is done using a counter 8.

Thus, the information is rewritten from the RAM 7 in the decoder 3, is added to a portion of the information received on the third input device, and the counter 17 is recorded state (binary number) is identical to the counter state in the previous cycle of reception of the information for the same VC.

Limitation of pieces of information received at the input of the decoder 3, is produced by the trigger 9 feeding it To the input signal generated from the second output of the decoder 2. The coincidence of this signal in time of the clock pulse T 2 (trailing edge) trigger 9 is switched to the zero state and the write data in the decoder 3 is terminated.

The information is then recorded in the decoder 3 for a given VC, is overwritten in the RAM 7, and the counter 17 in block 18. This is done by the signal generated at the third output of the decoder 2 via the OR element 14 to the input of the chip select RAM 7 and the block 18, and the signal received simultaneously at the input of the write mode RAM 7 and the block 18 with the output element, And 13, which turned out to be the coincidence of the clock pulse T 2 with the signal on the third output of the decoder 2 (Fig. 3). The signal processing procedure for a single VC begins and ends with the formation of sledujushih the

After storing portions of the data RAM 7 and the block 18 for all N VK and busting the counter 8 of the addresses of all the VC begins a new cycle of operation. The duration of such a cycle is equal to the repetition period of the pulse cycle frequency 8 kHz. The result in the RAM 7 accumulates the information sequence, which is based on redundant coding using cyclic code, for example, 19, 10. The decoder 3 is used to detect errors in received data.

The counter 17 through the block 18 and the multiplexer 16 generates a binary number indicating the length of information sequence. This number identifies the decoder 19, and outputs a signal on one input element And 5, the other input of which in the absence of errors (i.e., the equality of the balance to zero after decoding unit information sequence in the decoder 3) is formed by a pulse from the output of the decoder 4. As a result, the output element 5, and thus, at the output device, a signal is generated to confirm the correct reception of an information block of a given VC, the number of which is determined by the address code generated by the counter 8 to the address outputs of the device.

The counter 17 before receiving each information block is roan information block (sequence), with a clock pulse T 1. The reset signal (token) is input to 5 devices at the beginning of each information block (sequence).

Thus, the proposed device allows to detect errors (decode) the received information independently and simultaneously in real time on N discrete communication channels at speeds of 2400, 4800, 9600, 32000 and 48000 bits/s

DEVICE FOR MULTI-channel DECODING, containing blocks of memory, the first counter, the first decoder and the decoder, wherein, to improve the performance of your device, enter the second and third counters, multiplexers, the second and third decoders, trigger, elements, elements, OR, the first outputs of the first counter connected to respective inputs of the first decoder, the first output of which is connected with the first inputs of the first element OR the first element And control inputs of multiplexers, the outputs of the first multiplexer are connected with the corresponding first information input of the decoder, the first and second outputs of which are connected with the corresponding first information input of the first multiplexer, the inputs of the second decoder and the information is rmazioni inputs of the multiplexer, the second and third outputs of the first decoder connected respectively with K-input trigger, the first input of the second element And the second input of the first element OR the output of which is connected to the inputs of the chip select of the first and second blocks of memory, the second output of the first counter is connected to the counting input of the second counter whose outputs are connected to respective address inputs of the first and second blocks of memory and are address outputs, the outputs of the second multiplexer is connected to the first information input of the third counter, the outputs of which are connected with the first information input of the second multiplexer, corresponding inputs of the third decoder and data inputs of the second memory block, the outputs of which are connected with the second information inputs of the second multiplexer, the outputs of the second and third decoders are connected respectively with the first and second inputs of the third element And whose output is an information output device, direct the trigger output is connected to the first input of the fourth element And whose output and the output of the first element And connected with the first and second inputs of the second element is n with inputs write blocks of memory, the output of the fifth element And to the input of reset the third counter, the second output of the third decoder is connected to the second information input of the third counter, the counting input of the first counter and the first input of the fifth element And the joint and are the first input device, the input reset of the first and second counters are the second input device, the second information input of the decoder and the J-input of the trigger are combined and the third input of the C-input of the trigger and the second inputs of the first, second and fourth elements And are combined and the fourth input of the second input of the fifth element - the fifth input device.

 

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