Device for correcting errors in a character code

 

(57) Abstract:

The invention relates to data transmission and can be used for gradual correction of errors. The purpose of the invention is the increased robustness. This goal is achieved by the introduction of the D-flip-flops 1,1 - 1,5 elements OR 5, 6, item, And 7 in the device containing the counter 2, the delay element 3 and element OR 4. The device corrects all the offsets to ](T-1)/2[ bits during reception of serial code. 1 Il.

The invention relates to data transmission and can be used for serial bug fixes.

Known devices for controlling the code minimal form [1], the optimal form [2], in batch form [3].

The disadvantage of these devices is the inability to correct errors of the displacement type units in the neighboring discharge (left or right).

Closest to the invention to the technical essence and the achieved result is a device for control of Fibonacci p-codes (p t) containing the element OR the shift register, the information input which is the input of the trigger element is NOT, the delay block and counter, the output of the register is output, clock the WHA merged with the first input of the OR element and is connected to the control bus, the second input element OR is connected to the output of the counter overflow and the output with the input set to "0" trigger, the output of which is connected to the inputs of the installation in the "0" of the register and the delay block and a reference output device, the counting input of the trigger is connected to the output of the delay unit, the input of which is combined with the input set to "0" of the counter and the input of the register element, the output of which is connected to the counting input of the counter [4].

The disadvantage of the prototype low immunity, as this device does not allow you to correct errors.

In the receiving device of the data transmission system the decision on admission to 0 or 1 is taken at the time of receipt of the sync pulse. Under different interference and influence of parameters of the communication channel errors offset (left or right). To correct such errors are prompted for the source code

a(0)a(1)a(2)...a(m-1) Converter in the character type code

a(0) a(1)...a(m-1)

where between code bits is placed at T zero defensive category, and T/2 protective discharge at the borders. Thus, a code sequence corresponding to the source, will have a length of n = (T+1)m.

For example, if the source code to use l ustoichivosti notation of the form (1) is given by the polynomial

A = A(S)f (S-T/2)/(T+1))

where

a(S) =

Here f(S) - basic function; for the classical notation

F(S) = f(S-1)+f(S-1) for p-notation for p=1

F(S) = f(S-1)+f(S-2) for t-base with t=1

F(S) = F(S-2)+F(S-3).

The signal E(S) error-correcting type level-shift left-right that is generated by the rule

E(S) = a(S-T/2)v...va(S-2)va(S-1)v

va(S+1)va(S+2)v...va(S+T/2) (2)

(S = (T+1)i - T/2, i = 1,2,..., n/(T+1)).

The purpose of the invention is improving the noise immunity of the device.

The drawing shows a structural diagram of an apparatus for error correction in the error correcting notation of the form (1) at T=4, which contains the D-flip-1.1-1.5, counter 2, item 3 of the delay elements 4,5,6 OR, the And gate 7, the information input 8, engraved 9 reset input 10 output 11.

D-flip-1.1-1.5 are designed to remember the next five digit portions, the average discharge of which is information, and the remaining excess

00a(0)0000a(1)0000...a(m-1)00. (3) These triggers form shift registers.

Counter 2 (the conversion factor is equal to T+1, consider the case when T=4, the conversion factor is equal to 5) specifies the mode of the device after the recording of the next portion of code it sends a signal NAII code in D-triggers 11-15 after T+1 (5) sync.

The device operates as follows.

Let the input of 8 received code combination 00100, which was recorded in the D-flip-11-15 five pulses at the output of the counter overflow 2 unit, the actuation element OR 6 does not occur (because the combination has not been corrupted) and upon receipt of the sync pulse from the delay element 3 element And 7 does not issue a signal to the correction code. In the case of distortion combinations

1.1 - 0 0 0 1

1.2 - 0 0 1 0

1.3 - 0 0 0 0< / BR>
1.4 - 0 1 0 0

1.5 - 1 0 0 0

_________________

1 2 3 4

Element 6 OR throws an error signal, and after the fifth pulse, the overflowing counter 2 (unit output counter overflow 2), and upon receipt of the sync pulse from the delay element 3 element And 7 is triggered, setting the D-flip-1.1, 1.2, 1.4, 1.5 in the zero state, and the D-flip-flop 1.3 in one state, the output signal of the overflow counter is set to the initial zero state.

Thus, the proposed device corrects all errors offset left or right according to the formula (2) in the code combinations of the form (3), thereby increasing the noise immunity of the data reception due to the complicated structure of the code combinations.

DEVICE FOR CORRECTING the spruce improve noise immunity of the device, it introduced D-triggers, second and third elements OR element, And an information input of the first D-flip-flop is an information input device, the output of the first D-flip-flop connected to the first input of the second item OR the information input of the second D-flip-flop, the output of which is connected to a second input of the second OR element and the first input of the first element OR the output of which is connected to the information input of the third trigger, the output of which is connected to the information input of the fourth flip-flop, the output of the fourth flip-flop is connected to the third input of the second element OR the information input of the fifth D-flip-flop, the output of which is connected to the fourth input of the second element OR an output device, the output of the second element OR connected to the first input element And the output of which is connected to the reset inputs of the first, second, fourth and fifth D-flip-flops, the second input of the first element OR the first input of the third element OR the output of which is connected to synchronator third trigger, the state clock inputs of the first, second, fourth and fifth D-flip-flops merged with the input of the delay element and a counter input of the counter and are synchronator device, the output of the delay element is connected is of ketchika is the reset input of the device.

 

Same patents:

The invention relates to computing

The invention relates to systems for the transmission of information via communication channels and can be used in devices for decoding by the Viterbi algorithm

The invention relates to computer technology and can be used in communication systems and information processing, operating with modular codes (codes in the system of residual classes - JUICE)

The decoding device // 2007866
The invention relates to communication technology, and in particular to devices for decoding information encoded block correction code, and can be used in communication systems with replay code words

The invention relates to a multi-valued error-correcting coding for the protection of the transmitted channel information from failures caused by interference

The invention relates to telecommunication and computer engineering and can be used to enhance noise immunity in the transmission and processing of digital information, in particular in digital audio

The invention relates to telecommunication and computer engineering and can be used to enhance noise immunity in the transmission and processing of digital information, in particular in digital video recording

The invention relates to computer technology, telecommunication and can be used at the receiving side communication systems for encoding binary

FIELD: Witterby algorithm applications.

SUBSTANCE: system has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.

EFFECT: higher efficiency.

2 cl, 9 dwg

FIELD: communications engineering.

SUBSTANCE: proposed device and method for mobile code-division multiple access communication system including device for transferring channel of backward-link transmission speed indicator afford generation of optimal code words ensuring optimal coding for all types of coding procedures from optimal type (24.1) up to optimal coding procedure 24.7 and supporting all optimal-coding devices.

EFFECT: optimized capacity.

74 cl, 21 dwg, 44 tbl

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communications engineering; network remote measuring and control systems.

SUBSTANCE: proposed noise-immune cyclic code codec designed for data transfer without pre-phasing has on sending end code-word information section shaper incorporating shift-register memory elements, units for computing verifying parts of noise-immune code of code-word information section, and modulo two adder of code-word information section shaper; code-word synchronizing section shaper and modulo two adder of code-word synchronizing section; on receiving end it has binary filter incorporating binary-filter shift register memory elements, computing units for verifying parts of binary-filter noise-immune code, and binary-filter modulo two adder; shift register of code word information section; decoder; accumulator; error correction unit; unit for shaping synchronizing section of code word; and modulo two adder units.

EFFECT: enhanced speed of device.

1 cl, 1 dwg

FIELD: communication systems.

SUBSTANCE: method includes generating sets of sub-codes of quasi-additional turbo-codes with given encoding speeds, and given sub-codes are reorganized as a set of sub-codes with another encoding speed for use in next transfer of sub-code with given encoding speed.

EFFECT: higher efficiency.

9 cl, 13 dwg

FIELD: data transfer technologies.

SUBSTANCE: method includes segmentation of length N of quasi-complementary turbo-codes on preset amount of sections, determining identifiers of sub-code packets appropriate for segmented portions, setting of said packets separated for initial transfer of sub-code, calculation of number of remaining symbols in form N-Fs, where N - length of quasi-complementary turbo-codes, and Fs - position of start symbol of sub-code of quasi-complementary turbo-codes, determining position of symbol of remaining symbols in amount equal to sub-codes amount, which have to be sent and serial transfer of sub-code symbols from position of starting symbol Fs to position of last symbol Ls.

EFFECT: higher efficiency.

5 cl, 17 dwg

FIELD: communications engineering.

SUBSTANCE: method includes selecting one combination among given combinations, appropriate for several or every generated symbols of code word to transmit generated symbols of code word with length of sub-packet, determined in accordance to data transfer speed, information, appropriate for data transfer speed, is read, also based on length of sub-packet and chosen combination, from a table, wherein identification information, pointing at data transfer speed, sub-packet length and selected combination, is, is previously displayed for given information, and generated code word symbols are transmitted in accordance to read information and in accordance to selected combination.

EFFECT: possible check transmission of information by means of hybrid automatic repeat query for increasing carrying capacity during high-speed information transfer.

4 cl, 16 dwg, 6 tbl

FIELD: communications engineering; simulating digital communication channels with separate and grouping errors.

SUBSTANCE: proposed method includes evaluation of set of communication channel states S0,S1, ..., Sm - 1 and calculation of conditional error probabilities P(e/s) in each state s" i = 0, ..., m - 1 of communication channel, and error acquisition in communication channel in compliance with conditional error probability for current state of communication channel; in the process probability of error-free interval p(0i) of i bits is found, and conditional probabilities p(0i1/11), p(0i1/01) of error-free intervals of i bits are calculated with respect to them basing on probabilities p(0i) and using recurrent rules during each current time interval and preceding one on condition that for error generation use is made of two states of communication channel corresponding to combination of errors 11 or 01; random number p uniformly distributed within interval between 0 and 1 is generated; conditional probabilities p(0i1/11), p(0i1/01) are summed up starting from i = 0 resulting in sequence 0k1 that constitutes bit-by-bit stream of communication channel errors.

EFFECT: enhanced speed.

1 cl, 1 tbl

FIELD: communications engineering; data transfer, telemetering, and telecontrol systems.

SUBSTANCE: proposed codec has on sending end code-word data part shaper whose output and that of code-word synchronizing part shaper are connected to modulo two adder input; on receiving end it has binary filter whose code-word data part shaper output is connected to accumulator connected to synchronizing sequence decoder and to error connection unit whose outputs are connected to respective inverting inputs of code-word data part shaper; output of the latter functions as data output of device; output of binary-filter code-word synchronizing part is connected through switching unit to input of code-word data part shaping unit; synchronizing sequence decoder output is connected to control input of switching unit and to error correction unit input; on receiving end accumulator outputs are connected to inputs of code-word data part shift decoder whose output is connected to input of delay circuit whose output functions as second control input of switching unit and as synchronizing output of device.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: coding in communication systems.

SUBSTANCE: proposed partial reverse bit-order interleaver (P-RBO) functions to sequentially column-by-column configure input data stream of size N in matrix that has 2m lines and (J - 1) columns, as well as R lines in J column, to interleave configured data, and to read out interleaved data from lines.

EFFECT: optimized interleaving parameters complying with interleaver size.

4 cl, 7 dwg, 3 tbl

Up!