Failover device for multiplying

 

(57) Abstract:

The invention relates to computing and can be used in the development of high-speed devices multiplication of high reliability, easy to manufacture using the technology of LSI and VLSI. The aim of the invention is to improve the reliability of the device due to the continuation of the work on a smaller number of major operating units, with a corresponding reduction performance of the device. The device includes a register mnimogo, n operating units (n is the bit width mnimogo), n switches of the first and second groups, the switch mnimogo, the control unit reconfiguration and new switch shift, two shifter and switch. 8 Il.

The invention relates to computing and can be used in the development of high-speed devices multiplication of high reliability, easy to manufacture using the technology of LSI and VLSI.

A device for multiplying containing the register mnimogo and n operating units (n is the bit width mnimogo).

With its high performance, this device has a low reliability, which is ecoutotheque device for multiplication, containing n main operating units (n is the bit width mnimogo), m operating reserve blocks (m= 1,2,3,...), two groups of n+m switches, each switch mnimogo and the control unit reconfiguration, and the input of the multiplier of the i-th main operating unit (i=1,...n) is connected to the input of the multiplier of the i-th backup of the operational unit (j= 1,...,m) and the input of the multiplier device, the input mnimogo which is connected with the information input switch mnimogo, n+m outputs of which are connected with inputs mnimogo corresponding to the top n and m operating reserve units, control inputs from the first to n-th switches the first and second groups are connected with the first output control unit reconfiguration and first managing the switch input mnimogo, the second control input of which is connected to control inputs with (n+1) th to (n+m)-th switches the first and second groups and a second output control unit reconfiguration, third and fourth outputs of which are connected respectively to the outputs of failure and interruption device, the input control and the first control input of which is connected respectively to the input control and managing the input of the control unit reconfiguration, the input element of the i-th osnovnoj what about the operating unit connected to the first information input of the i-th switch of the first group, the input element of the j-th backup operating unit connected to the first output (j+n)-th switch of the second group, the output of the j-th backup operating unit connected to the first information input of the (j+n)-th switch of the first group, the second output of the k-th switch of the second group (k=1,.. .,n+m) is connected with the second information input of the k-th switch of the first group, the output of which, except the first switch of the first group connected to the information input of the (k-1)-th switch of the second group, the output of the first switch of the first group is connected to the output of the device, the input correction which is connected with the information input (n+m)-th switch of the second group.

This device has the ability to continue functioning after the failure of its main operating units due to their replacement reserve operating units.

The disadvantage of this device is its low reliability with a small amount of operating reserve blocks, and when they increase sharply increase hardware costs.

The aim of the invention is to improve the reliability of the device due to the continuation of the work on a smaller number of major operating units with boosterist for multiplication, containing n operating units (n is the bit width mnimogo), two groups of n switches, each switch mnimogo and the control unit reconfiguration, and the input of the multiplier of the i-th operational unit (i=1,...,n) is connected to the input of the multiplier device, the input mnimogo which is connected with the first information input of the switch mnimogo control inputs of the switches of the first and second groups are connected with the first output control unit reconfiguration, second and third outputs of which are connected respectively to the outputs of failure and interruption device, the input control and the first control input of which is connected respectively to the input control and managing the input of the control unit reconfiguration, the input element of the i-th operating unit is connected to the first output of the i-th switch of the second group, the second output of which is connected to the first information input of the i-th switch of the first group, the output of the i-th operating unit connected with the second information input of the i-th switch of the first group, the output of which, in addition to the output of the first switch, is connected with the information input (i-1)-th switch of the second group, the output of the first switch of the first group is connected to the output of the result is utter, moreover, the output switch mnimogo connected with the information input register mnimogo, the output of which is connected to the information input of the second shifter and the second information input of the switch mnimogo, managing shift, the output of which is connected with the control input of the first shifter and the second information input to the fourth output control unit reconfiguration, the fifth output of which is connected with the control input of the delay unit, an information input connected to the output of the first switch of the first join group, and the output from the first information input of the switch, the output of which is connected to the information input of the n-th switch of the second group, the first output control unit reconfiguration is connected with the control input of the second shifter, the i-th output of which is connected to the input mnimogo the i-th transaction unit, the third control input and the second input of the correction device are connected respectively with the control input and the second information input of the switch.

In Fig. 1 shows the structural diagram of the proposed fault-tolerant device for multiplication of Fig.2 - structural diagram of the operational unit of Fig.3 is a functional diagram of the switch perks when n=8; in Fig.6 is a structural diagram of the first shifter; Fig. 7 is a structural diagram of the second shifter; Fig.8 is a block diagram of the control unit reconfiguration.

We offer a failover device for multiplication register 1 contains mnimogo, n operating units 2 (n - bit width mnimogo), n switch 3 of the first group, n switches 4 of the second group, unit 5 delays the switch 6 mnimogo, the switch 7 of the shift switch 8, the first 9 and second 10 shifters, block 11 control reconfiguration, the inputs 12, 13 and 14 mnimogo, the multiplier and the control device, respectively, the first 15 and second 16 inputs the correction device, the first 18, second 17 and third 19 control inputs of the device, the outputs 20, 21 and 22 of the refusal and interrupting devices, respectively. The input of the multiplier of the i-th unit 2 is connected to the input device 13, input mnimogo - with the i-th output 23 of the shifter 10, the input element with the first output 24 of the i-th switch 4, the output 25 of the - with the first information input of the first switch 3, the second information input of which is connected to a second output 26 of the i-th switch 4, an information input connected to the output 27 (i+1)-th switch 3, the information input of the n-th switch 4 is connected to the output 28 which is connected to the output of the first switch 3 and the output 20 of the device, the input 12 mnimogo which is connected with the first information input of the switch 6, the second information input of which is connected to the information input of the second shifter 10 and the output 30 of the register 1 mnimogo, an information input connected to the output 31 of the first shifter 9, the information input connected to the output 32 of the switch 6, the control input of which is connected to the controlling input of the switch 7 and the second managing input device 17, the first input 15 of the correction of which is connected to the first information input of the switch 7, the output 33 which is connected with the control input of the first shifter 9, the control input unit 5 is connected to the output 34 of the block 11, the output 35 which is connected with the second information input of the switch 7, the control inputs of the i-th switches 3 and 4 are United and connected with the control input of the second shifter 10 and the first output 36 of sbloca 11, second and third outputs of which are connected respectively to the outputs 21 and 22 of the device, the inputs 14, 16, 18 and 19 which are connected respectively to the input control unit 11, the second information input of the switch 8, the controlling unit 11 and control input of the switch 8.

Consider the functionality and implementation is made by an n-bit register, which can be implemented in a synchronous push-pull D-triggers.

Operating units 2 are used to calculate the bit values of the work and generate on their outputs 25 values:

[HU+a+b] ml,

where [ ] ml indicates the low-order digit of the result;

X,Y is the corresponding digit of factors, arriving at the inputs mnimogo and multiplier blocks 2;

A - single-digit addends, arriving at the inputs of the components of block 2;

In - internal single-digit addends stored in the buffer registers 38 2 blocks.

The implementation of the block 2 shown in Fig.2. In this case, each block 2 contains the node 37 calculate bit values works and buffer registers 38 and 39. Node 37 generates at its outputs digit value of a function

F=HU+A+B,

senior and low-order bits which are recorded respectively in the registers 38 and 39. Implementation of node 37 depends on the requirements of regularity of structure and performance, and can be implemented, for example, in the form of a homogeneous cellular structure. The registers 38 and 39 can be implemented in a synchronous push-pull D-flip-flops with inputs installation in the zero state.

Commuter 3 is designed for pereth signals. Implementation of switch 3 elements 40, 41 and 42 shown in Fig.3.

Switch 4 is used for delivery of information from your informatsioonogo log on to the first 24 and second 25 its output depending on the signal at the control input. In Fig.4 shows an implementation of the switch 4 on the elements 43, 44.

Unit 5 delays designed for storing bits of the sums of the partial products generated when the device is low speed after the bounce blocks 2 and reconfigure the device. Depending on the signals at the control input unit 5, it can be configured for different delay the passage of information from its data input to its output 29. Latency when the number of blocks 2 n=2m(m=1,2,3,...) is equal to n/2andwhere l=1,2,...,m is the degree of degradation, which determines the state of the device with a certain level of performance. In the case of n=8, the device may operate using 8 operating blocks 2 - initial state, 4 operating units 2 - first degree of degradation (l=1), 2 operating units 2 - the second degree of degradation (l=2) and one operational unit 2 - third degree of degradation (l=3). The implementation of the block 5 may be different. In Fig. 5 shows realier 45 - n/2-bit (in this case, 4-bit), the second register 45 - n/4-bit (in this case, 2-bit) and the third case 45 - n/8-bit (in this case, single-digit). Feeding on the switches 46 control signals, it is possible to form the circuit registers the bit width n/2 or n/2+n/4=3n/4 or n/2+n/4+n/8=7n/8. Registers 45 unit 5 can be implemented in a synchronous push-pull D-triggers. The switches 46 for transmitting information to the inputs of respective registers or the second information inputs can be implemented on the elements of And and OR similarly shown in Fig.3 switch 3.

The switch 6 is designed to transmit information on its output 32 (information input shifter 9) with their first or second information inputs depending on the control input 17 of the device. It can be implemented similarly shown in Fig.3 switch 3.

The switch 7 is designed to transfer the code of the shift control input of the shifter 9 (exit 33 of the switch 7) with the first input 15 of the correction device, or from the output 35 of the block 11 according to the control signal at the input 17 of the device. It can be implemented similarly shown in Fig.3 commute 4) information from the first or second information inputs depending on the control signal at the input 16 of the device. It can be implemented similarly shown in Fig.3 switch 3.

The shifter 9 is designed to shift information on the value defined by the code on its control input. It performs a cyclic shift to the left of the information received at its data input, and can be implemented similar to that shown in Fig.6. In this case, it has m switches 47, implemented similarly shown in Fig.3 switch 3, and the first (Junior) category code shift at the control input of the shifter 9 configures the first switch 47 to shift to 0 or 1 digit, the second digit of code shift configures the second switch 47 to shift to 0 or 2 digits, and the m-th bit of code shift - m-th switch 47 to shift to 0 or 2m-1discharges. Thus, the shifter 9 under the control code supplied to its control input, can be configured to shift mnimogo on any number of digits.

The shifter 10 is designed to redistribute the bits mnimogo from the information input from the output 30 of the register 1 mnimogo between inputs mnimogo block 2 so that the information can be shifted to the left, starting from any discharge, keeping his right side. About the logical shown in Fig.3 switch 3 the first (primary) category code shift at the control input of the shifter 10 configures the first switch 48 to shift all the information (n bits) to the left by 0 or 1 digit, the second digit of code shift configures the second switch 48 to shift (n-1) bits of information left at 0 or 1 digit, the third digit of code shift - the third switch 48 to shift (n-2) bits of information left at 0 or 1 digit, and so on

Unit 11 control reconfiguration is designed to generate control signals for interrupting the operation of the device at the failure of unit 2, the choice of functional unit blocks 2 and its connection with the block 5 delay and register 1, select the desired delay amount in units of 5, code shift mnimogo when overwriting in case 1 after each cycle of operation of the device, and for issuing a signal about the failure after n failures 2 blocks. One of the possible implementations of block 11 for device number 2 blocks n=8 (m=3) is shown in Fig.8. Block 11 contains two groups of n triggers 49 and 50, the group of m triggers 51, n-input elements OR 52 PII OR 53, m-input accumulating element OR 54, three counter 55-57, two decoder 58, 59, n elements And 60 m elements And 61, elements, And 62 and 63 and NOT a group of (m-1) elements of the SLUDGE is vlivaetsa to "0". The signal about the refusal of any block 2 through the element OR 52 is supplied to the counting input of the counter 55, which together with the decoder 58 determines the number of failed blocks 2 in the device. In addition, the signal from the failure of any unit 2 resets to zero state counters 56 and 57 and the second trigger group 50, and arrives at the output 22 of the device causing the interrupt his work. The outputs of the decoder 58 is combined with an element OR 64 into groups, each of which corresponds to a degree of degradation of the device performance, for example, the first element OR 64 combines the outputs of the decoder 58 from the first to the n/2-th, i.e., up to n/2 failures 2 blocks the device operates with a first degree of degradation of performance (using n/2 operable unit 2), the second element OR 64 combines the outputs of the decoder 58 (n/2+1)-th to (n/2+n/4)-th, and indicates that the second degree of degradation of performance (using n/4 operable unit 2). The signals from the outputs of the elements OR 64 and (n-1)-th output of the decoder 58 receives the output 34 of the block 11 (set the corresponding delay unit 5) and set to "1" corresponding triggers 51, the outputs of which are formed from shift code for shifter 9, which determines the value of sopralene, what blocks 2 will continue functioning, as well as to generate signals settings of switches 3, 4 and shifter 10, the connection information inputs and outputs of the respective blocks 2 in the working configuration, the second control input 18 of the device (control input unit 11) are the clock pulses through the element And 62 at the counting input of the counter 56. From the output of the counter 56 through the decoder 59, the signals received at the first inputs of elements And 60, starting from the first element And 60, the outputs of which appear to "1" if the corresponding operable unit 2 (corresponding to the trigger 49 is "1"). The number "1" at the outputs of the elements And 60, and therefore, the number of defective blocks 2 are counted by a counter 57. When the number counted by the counter 57 is operable units 2 is equal to the desired quantity, which is determined by the degree of degradation of the performance of the device and translates information from the outputs of the decoder 58 and elements OR 64, the output of the corresponding element And 61 appears "1", through which the elements OR 54 and NOT 63 is supplied to the second input element And 62, preventing further passage of clock pulses to the counting input of the counter 56. The counter 56 remains with the Ohm meter 57 working 2 blocks signals from the outputs of the elements And 60 being set to "1" triggers 50, the respective working units 2, plug in a working configuration. The output 36 of the block 11 is formed as the control code for the settings of switches 3, 4 and shifter 10.

After the n-th failure 2 blocks from the n-th output of the decoder 58 to the second output unit 11 (exit 21 of the device) receive a signal about the failure and the inability to reconfigure the device.

Structural and functional schemes to simplify conventionally not shown installation chain in the zero state registers 38, 39 2 blocks, triggers, 50, 51 and counters 55-57 unit 11, a circuit installed in one state triggers 59 unit 11, and chain synchronization register 1, register 38, 39 blocks 2 and registers 45 unit 5. However, it can be noted that there is a common chain synchronization registers 38, 39 blocks 2 and registers 45 unit 5 (the signals are at the end of each cycle of the device), chain synchronization register 1 (signal before the operation and at the end of each cycle), the total circuit installed in the zero state registers 38, 39 block 2 (the signal before any of the operating modes of the device) and a common circuit installed in the zero state triggers 59, 51 and counters 55-57 block 11, connected to the chain at the ri of all operable units 2).

The operation of the device is considered for the three modes:

1) operating mode;

2) the mode reconfiguration;

3) operating mode with reduced speed.

In the initial state of the registers 38, 39 2 blocks, triggers, 50, 51, and counters 55-57 unit 11 is set to zero, the trigger 49 is set to "1", the inputs 17 and 19 device filed the control signals that configure accordingly, the switches 6 and 7 on the transfer of information from the first information inputs (inputs 12 and 15 of the device), and the switch 8 on the transfer of information from the second information input (input device 16). In the case 1 through the shifter 9, the control input which is set to zero, the code that is present on the input device 15, is written without a shift n-bit value mnimogo received at the input 12 of the device. Running code of zero at the output 36 of the block 11 at the i-th output of the shifter 10 is the i-th bit of mnimogo, switches 4 of the same signal are configured to transfer information from their information inputs to their outputs 24 and the switches 3 with their first informational inputs (outputs 25 of the respective blocks 2) on their outputs 27.

The operating mode.

The device calculates the 2n-bit product of n-bit single discharge, starting with the youngest, the multiplier. In the i-th operating unit 2 is the multiplication of the i-th digit mnimogo, arriving at its input mnimogo with the i-th output 23 of the shifter 10, a discharge factor, arriving at its input multiplier input device 13, and the addition to the low order resulting when this digit works LSB works (i+1)-th block 2, arriving at its input term output 24 of the i-th switch 4 and older category of works of the i-th block 2 stored in the register 38, senior and Junior categories formed the i-th block 2 pieces at the end of each stroke is recorded in its registers 38 and 39.

After execution of n first clock cycles of operation to the input device 13 receives zero information, and then performed another n cycles during which of the devices is displayed with the corresponding transformation information stored in the registers 38, 39 block 2.

It should be noted that the output of the 2n-bit product in the device through its output 20 one bit in each step.

In the considered case, during the entire operation of the device at its input 16 there is zero information. If you want to receive the divided information (for example, for rounding the 2n-bit product of factors, represented in binary-coded number system, it is necessary to input 16 in the first cycle of the device file is binary 1000). This allows rounding of the result in no time. In addition, the input device 16 may be used for introducing the resulting correction of the signs when multiplying numbers in two's complement.

Mode reconfiguration.

During the operation of the blocks 2 can refuse. It is assumed that each unit has 2 detection of failure in the form of means of internal control, which can be arranged by any known means, for example, duplication or control in module two. The status information of the blocks 2 is fed to the input 14 of the device at the time of survey control means 2 blocks. Due to the low probability of simultaneous failure of two or more blocks 2 this situation will not be considered.

The signal from the denial of the i-th block 2 from input device 14 enters the block 11, which sets the i-th trigger 49 to "0", and also through the OR element 52 is supplied to the output 22 of the device causing the interrupt his work, and at the counting input of the counter 55, octanitrate enters the mode reconfiguration, which can be divided into two phases. In the first stage unit 11 produces the signals for adjustment unit 5 delays and shifter 9, which is determined by the number of failed blocks 2. In the second phase unit 11 produces control signals for the switches 3 and 4 and the shifter 10, which of the 2 blocks will continue functioning.

After the installation of the meter 55 in the first state at the first output of the decoder 58 appears "1", through which the first element OR 64 is supplied to the first output 34 of the block 11 and further to the control input unit 5, configuring the first switch 46 to the transmission of information from the information input unit 5 to the input of the first register 45. In addition, this signal sets to "1" the first trigger 51, thus determining the output 35 of the block 11 size code shift for shifter 9, is equal to n/2 bits, and is supplied to the first input of the first element And 61, preparing it to work in the second phase reconfiguration.

In the second phase reconfiguration input device 18 serves heartbeats, which through the element And 62 unit 11 receives at the counting input of the counter 56. At the inputs of the decoder 59 successively appear "1", allowing the passage of information through sootlike i-th trigger 49 is set to "0" signal on the refusal of the i-th block 2), therefore, the "1" outputs of the decoder 59 pass through the respective elements And 60 to the inputs OR 53 and then arrive at the counting input of counter 57, which carries the reference functional block 2. When the number of counted operable unit 2 (the signal on the corresponding output of the counter 57) is required of them to continue working (in this case requires n/2 blocks of 2, which is determined by the signal at the output of the first element OR 64), the output of the corresponding element And 61 (in this case the first element And 61) of poyavlyaeza "1", through which the elements OR 54 and NOT 63 prevents further flow of clock pulses to the counting input of the counter 56 through the element And 62.

Simultaneously with the counting of functional blocks 2 to configure the trigger group 50, which first mode reconfiguration unit output element OR 52 were set to "0". In the presence of a "1" output elements And 60 corresponding to the trigger 50 is set to "1". In this case, "1" will be installed n/2 trigger 50, the rest will remain in the zero state.

Thus, at the end of the mode reconfiguration on the outputs of the block 11 will contain the following information: output 34 is in the first places); at the output 35 is in the first position is 1, and the other is "0" (this set of signals is determined by the shift code for shifter 9, is equal to n/2 bits); output 36 - n/2 digits, starting with the first and excluding the i-th (if 1i n/2) are "1", and the other is "0" (this set of signals is determined by the shift code for shifter 10 and configured the switches 3 and 4 thus, n/2 of the respective functional blocks 2 are included in the working configuration, and the remaining n/2 blocks 2 are excluded from work). Steam is zeroing registers 38, 39 block 2, and the input device 17 serves a control signal that configures the switches 6 and 7 on the transfer of information from their second information inputs. The device enters a mode of operation with reduced performance.

The mode of operation with reduced performance.

In this mode, the calculation of the 2n-bit product of the n-bit factors is made for a greater number of cycles than using all available operating units 2. So, in the case where the total number of operating units 2 device n=2m(m=1,2,3,...) the product of n-bit cofactors can be efficiently computed by m+1 algorithms, distinguished bistroy device, and m algorithms with reduced performance, each of which is determined by the degree of degradation 1 performance of the device. When the l-th degree of degradation (l=1,... , m) the product of n-bit factors calculated for the 2lcycles, each of which consists of (n+n/2l) cycles using n/2loperating units 2 (when the first degradation degree l=1 are n/2 blocks of 2, when the second n/4 blocks 2 and so on). In each cycle is the calculation of the partial product of the n-bit multiplier n/2ldischarges mnimogo and potamiaena to him of the sum of the partial products generated in the previous cycle and stored in the registers 45 unit 5 (most significant bit) and the registers 39 block 2 (low-order bits). The result is a new sum of the partial products. Unit 5 is configured to delay in the (n-n/2l) cycles.

After the first failure of the unit 2 and reconfigure the device operation continues using n/2 blocks of 2, starting with the first and excluding the failed unit 2, i.e. set the first degree of degradation (l=1). Multiplication of n-bit cofactors in the device is a two-cycle (n+n/2l) cycles each.

In the first cycle is calculated partial about is that at the end of each beat from the output 25 of the first unit 2 in the first register 45 unit 5 is written to the next digit of the partial product (record of the first partial discharge works produced in the second step of the first cycle, as in the first step of this bit is written to the register 39 of the first block 2). In the (n/2+2)-th stage of the first cycle of the first partial discharge works with exit 29 unit 5 is supplied to the first information input of the switch 8, however, the input summand n/2-th block 2 (if the number of the failed unit 2 i>n/2 or (n/2+1)-th block 2 (if 1 i n/2) fails, and the following (n/2-1) bits of the partial product (which is achieved by applying an appropriate signal to the input 19 of the device)because younger n/2 bits of the partial product are the digits of the final result and in subsequent calculations do not participate.

At the end of (n+1)-th stroke of the first cycle to the input 19 of the device is a signal that permits the passage of information from the output 29 of the block 5 to the input summand n/2-th unit of work 2 and simultaneously with the entry in the next (n/2-1) cycles first cycle in the first register 45 unit 5 senior n/2 bits of the partial work is recorded in the registers 39 blocks 2 least significant bits of this work.

In the last step of the first cycle the contents of register 1 switch 6 and the shifter 9 is rotated to the left by n/2 bits of the running code at the output 35 of the block 11, so steam cycle of operation of the device is calculated partial product of n-bit multiplier n/2 high-order bits mnimogo and potamiaena to him n high-order bits of the partial works, formed in the first cycle (n/2 bits of the partial pieces of the first cycle are stored in the registers 39 units 2 and n/2 bits are received in each of the n/2 first bars of the second cycle of unit 5).

As in the first and second cycles during their first n clock cycles to the input device 13 is supplied by a single digit, starting with the youngest, the multiplier, and in the last n/2 cycles cycles - zero information.

It should be noted that the output of the 2n-bit product of factors is carried out through the output device 20 in the first n/2 cycles of the first cycle (Jr n/2 bits of the work) and in each step of the second cycle (upper n+n/2 bits of the work).

Upon the occurrence of the second failure among blocks 2 device again enters the mode reconfiguration signal at the output 22 of the interrupting device. Simultaneously with the issuance of this signal is reset triggers 50 and counters 56, 57 unit 11, the counter 55 has a status of "2" and the second output of the decoder 58, you receive a "1". Since the first n/2 outputs of the decoder 58 are used as inputs of the same element OR 64, the outputs 34 and 35 unit 11 remains unchanged information to configure the block 5 and shifter 9, respectively. In the to learn are set to "1" n/2 triggers 50, starting with the first and excluding those triggers 50, whose numbers correspond to the numbers of failed blocks 2, other triggers 50 remain in the zero state. Thus, in the continuation of the calculations are n/2 operable units 2, starting with the first. Through the rest of the blocks 2 through respective switches 3 and 4 there is a workaround information.

The first degree of degradation of the performance of your device (use when multiplying n/2 operable units 2) is maintained until n/2 failures 2 blocks. After the occurrence of (n/2+1)-th failure 2 blocks from the corresponding output of the decoder 58 "1" through the second element OR 64 output 34 unit 11 (unit 5 is configured to delay (n/2+n/4) clock cycles), and sets to "1" the second trigger 51, defining shift code for shifter 9 at the output 35 of the block 11 is equal to n/4 bits. In the second phase reconfiguration required to continue the number of blocks 2 is n/4 blocks of 2 (in this example implementation of block 11 in Fig.4 requires n/4=2 block 2), which is determined by the "1" on the output of the second element OR 64. After the counter 57 counts n/4 operable units 2, prohibits the supply of the clock signals through the element And 62 at the counting input of sketchily performance of the device, which is stored in the subsequent (n/4-1) the failure of unit 2, after which the speed is reduced to the third degree of degradation, etc.

Technical appraisal and economic benefits the proposed fault-tolerant device for multiplying lie in its higher reliability due to the continuation of the work on a smaller number of major operating units.

FAILOVER DEVICE FOR MULTIPLYING containing n operating units (n is the bit width mnimogo), two groups of n switches, each switch mnimogo and the control unit reconfiguration, and the input of the multiplier of the i-th operational unit (i = 1, ... , n) is connected to the input of the multiplier device, the input mnimogo which is connected with the first information input of the switch mnimogo control inputs of the switches of the first and second groups are connected with the first output control unit reconfiguration, second and third outputs of which are connected respectively to the outputs of failure and interruption device, the input control and the first control input of which is connected respectively to the input control and managing the input of the control unit reconfiguration, the input element of the i-th operating unit is connected to the first output of the i-th Ki-th switch of the first group, the output of which, in addition to the output of the first switch, is connected with the information input (i-1)-th switch of the second group, the output of the first switch of the first group is connected to the output of the device, characterized in that, to improve device reliability, it entered the switch of the shift register mnimogo, two shifter, the delay unit and the switch, the output switch mnimogo connected to the information input of the first shifter, the output of which is connected to the information input of the register mnimogo, the output of which is connected to the information input of the second shifter and the second information input of the switch mnimogo, the control input of which is connected with the control input of the switch position and the second managing input device, the first input of the correction of which is connected to the first information input of the switch of the shift, the output of which is connected with the control input of the first shifter and the second information input to the fourth output control unit reconfiguration, the fifth output of which is connected with the control input of the delay unit, an information input connected to the output of the first switch of the first group and the output from the first information input commutator second group is connected with the second information input of the i-th switch of the first group, the first output control unit reconfiguration is connected with the control input of the second shifter, the i-th output of which is connected to the input mnimogo the i-th transaction unit, the third control input and the second input of the correction device are connected respectively with the control input and the second information input of the switch.

 

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Pyramidal decoder // 2017208
The invention relates to computing

The invention relates to computing and allows high accuracy to control the combinational logic (CCL)

Redundant device // 2015544
The invention relates to automation and computer engineering and can be used in highly reliable control systems, working in hard real-time

The invention relates to automatic control and computer engineering and is intended for use in high-reliability redundant devices

The invention relates to automatic control and computer engineering and can be used for designing fault-tolerant computing systems, real-time

FIELD: computers.

SUBSTANCE: device has commutation block, checked microcontroller, block of read-only memory devices of checked microcontroller, block of operative memory devices, PC, controlling microcontroller, block 7 of serial interface, indication block, commutation block of serial interface, block for forming a signal of starting setting of block for forming ROM addresses, block for forming addresses of Rom of checked microcontroller, block for decoding control signals, data-reading block, RAM recording block, block of memory access constants for checked microcontroller, block for forming addresses of checked microcontroller, block for forming start setting signal for controlling microcontroller, RAM reading block, block for forming RAM addresses and power buses.

EFFECT: higher efficiency.

3 dwg

FIELD: computers.

SUBSTANCE: method includes, on basis of contents of central processor registers, received after processor performs some sort of command, by means of mathematical logical operation, forming certain finite control sum and storing it in memory, and on basis of contents of registers, received before start of execution by said processor of directly next command, certain starting checksum is formed, while if starting checksum mismatches finite checksum, error message is generated, which can be followed by halting of processor operation or blocking of chip board with its removal from circulation.

EFFECT: higher reliability.

2 cl, 2 dwg

FIELD: computer science.

SUBSTANCE: signals from each two bits of code of inputted data are converted to 1 of 4 code, calculations in said code are performed in accordance to operation code, result signals in said code are recorded, recorded signals are inputted into code control device and in case of mismatch error signal is generated and processing result output is blocked.

EFFECT: higher trustworthiness.

1 dwg

FIELD: computer science.

SUBSTANCE: method includes protective mathematical conversion of service data of network frame prior to transfer to environment for transfer of a LAN. To said protective conversion the data is subjected, which is contained in headers of network frames of channel level, and also in headers of all encapsulated network packets and segments. As a result the very possibility of interception is prevented.

EFFECT: higher efficiency.

7 cl, 2 dwg

FIELD: computer science.

SUBSTANCE: in the method, called program prior to execution checks data, sent from calling program directly or indirectly.

EFFECT: higher efficiency.

2 cl, 3 dwg

FIELD: measuring equipment.

SUBSTANCE: in turns, on each device, included in diagnosed block, feeding voltage amplitude is decreased in steps from nominal value Enom to threshold value Ethri with step ΔEn, while on each step of decreasing of amplitude of feeding voltage of device pseudo-random multi-digit code sets are sent to inputs of diagnosed block, consisting of logical zeroes and ones with even possibility of appearance of logical zero or logical one in each digit, received logic levels are recorded on outputs of diagnosed digital block and compared to standard levels, and when error frequency Fc appears, voltage value Ethri is recorded (functioning threshold) for each device and its functioning area is calculated on basis of feeding voltage ΔEpi. Defective (potentially malfunctioning) device is detected on basis of lowest value in functioning area ΔEpi, which is selected on basis of comparison of functioning areas of all devices, included in diagnosed digital block.

EFFECT: higher precision, higher efficiency.

1 dwg

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