A method of manufacturing a mos transistor

 

(57) Abstract:

Usage: a method of manufacturing a MOS transistor used in electronic engineering and is used in the manufacture of MOS VLSI. The inventive MOS transistor is generated by the formation on the surface of the semiconductor silicon wafer of the first conductivity type shutter with vertical walls, the introduction of ion implantation in the plate on both sides of the gate slowly diffusing impurities of the second conductivity type, the creation of low-alloy source-drain regions annealings embedded impurities, drawing on the surface with a stepped topography of the dielectric layer, creating anisotropic plasma etching caused parietal layer of dielectric regions, the introduction of ion implantation in the plate on both sides of the parietal areas slowly diffusing impurities of the second conductivity type, introduction ion implantation bystrozagruzhaemaya impurities of the same conductivity type and the simultaneous creation of annealing signalisierung Istok - stock areas and intermediate areas, the degree of alloying of which more low-alloy, at least signalisierung, whereby the gain relates to electronic devices and can be used in the manufacture of field-effect transistors and integrated circuits high degree of integration on the basis of them.

A known method of manufacturing a MOS transistor [1], which comprises forming on the surface of a semiconductor silicon wafer of the first conductivity type shutter with vertical walls, coating the surface with a stepped topography of the dielectric layer doped with phosphorus, the creation of anisotropic plasma etching of the deposited layer parietal areas, the introduction of ion implantation in the plate on both sides of the parietal areas slowly diffusing impurities of the second conductivity type, creating signalisierung Istok-stock areas annealing embedded impurities and the simultaneous creation of a low-alloy regions by diffusion of phosphorus from parietal areas.

In a known way to create signalisierung Istok-stock areas annealing slowly diffusing impurities and simultaneously low-alloy Istok-stock areas by diffusion of phosphorus from parietal regions leads to the formation of sub-optimal (sharp) profile Istok-stock areas.

As a consequence, produces large parasitic capacitance of the source-drain-substrate, increased edge effects, performance is decreased and the percentage of yield TRANS is for drinking, preparing MIS transistor [2] , including the formation on the surface of the semiconductor silicon wafer of the first conductivity type shutter with vertical walls, the introduction of ion implantation in the plate on both sides of the gate slowly diffusing impurities of the second conductivity type, the creation of low-alloy regions by annealing embedded impurities, coating the surface with a stepped topography of the dielectric layer, creating anisotropic plasma etching caused parietal layer of dielectric regions, the introduction of ion implantation in the plate on both sides of the parietal areas slowly diffusing impurities of the second conductivity type, creating signalisierung Istok-stock areas annealing embedded impurities.

The known method does not allow to obtain a high percentage of the output transistors and integrated circuits. If korotkokanal (scaled) transistors this is due to edge effects, in case dlinnorazmernyh transistors decrease in performance due to the increasing contribution of the stray capacitance.

The aim of the invention is to increase the yield by reducing korotkokanal effects by smoothing the trim is of nsistor, including the formation on the surface of the semiconductor silicon wafer of the first conductivity type shutter with vertical walls, the introduction of ion implantation in the plate on both sides of the gate slowly diffusing impurities of the second conductivity type, the creation of low-alloy regions by annealing embedded impurities, coating the surface with a stepped topography of the dielectric layer, creating anisotropic plasma etching caused parietal layer of dielectric regions, the introduction of ion implantation in the plate on both sides of the parietal areas slowly diffusing impurities of the second conductivity type, a highly doped source-stock areas annealing embedded impurities, after the introduction of the plate on both sides of the parietal areas slowly diffusing impurities of the second conductivity type, the plate in the same areas implement rapidly diffusing impurity of the same conductivity type, and at the same time with the creation of signalisierung Istok-stock areas by diffusion of fast diffusing impurities from signalisierung Istok-stock areas forming region, the degree of alloying of which more low-alloy, but worrisome slowly diffusing impurities simultaneously with the creation of annealing embedded impurities signalisierung Istok-stock areas to form the field, the degree of alloying of which more low-alloy, but less signalisierung areas. Thus, there is a smooth p-n junction decreases the field strength in the marginal areas of the source-drain, attenuated korotkokanal effects and this increases the yield of field-effect transistors and MOS IC.

The diffusion rate is additionally embedded in signalground Istok-stock impurity region must be higher than the diffusion rate of the main impurities. Otherwise there will not be forming regions with the degree of alloying of more low-alloy, but less signalisierung areas will not be smoothed diffusion profile.

In Fig.1 shows a semiconductor silicon wafer 1 of the first conductivity type after forming on the surface of the shutter with vertical walls 2, introduction ion implantation into the wafer on both sides of the gate slowly diffusing impurities of the second conductivity type and create low-alloy Istok-stock areas 3 annealing embedded impurities, drawing on the surface with a stepped topography of the dielectric layer, creating anisotropic plasma etching of the deposited layer near-wall dielectric region is an impurity of the second conductivity type, introduction to the plate in the same field of fast diffusing impurities.

In Fig. 2 shows the plate 1 after annealing embedded impurities signalisierung Istok-stock areas and regions 6, the degree of alloying of which more low-alloy, but less signalisierung areas.

P R I m m e R. On the surface of the semiconductor silicon wafer KDB-12 (Fig.1) the first type of conductivity (p) formed by thermal oxidation mask Si3N4region local oxide thickness of 0.5 - 0.8 μm with the subsequent removal of the mask Si3N4and the creation of ion doping boron (E= 30 Kev, D = 0.1 to 0.3 µc/cm2during the entire surface area of ponteginori channel transistors. Then the projection photolithography on the installation EM A from the printed plate layers gate thermal oxide thickness of 150 doped with phosphorus polysilicon with a thickness of 0.4 μm, and the low-temperature oxide thickness of 0.3 μm formed region of the shutter with vertical walls. The channel length L = 1.2 m, width W = 1.6 ám.

Low-alloy Istok-stock region formed by an ion doping antimony at the "Vesuvius-6" (E = 30 Kev, D = 0,4 - 1,0 µc/cm2) is ATiM relief LPCVD method caused a layer of silicon dioxide with a thickness of 0.8 μm and anisotropic plasma etching of the deposited layer on the installation 08 PHO-100T-004 created a wall surface of the dielectric region. After that, the plate on both sides of the parietal regions by ion implantation at the "Vesuvius-6" introduced slowly diffusing impurity (antimony), E=30 Kev, D = 0,4 - 1,6 µc/cm2then rapidly diffusing impurity (phosphorus), E = 30 Kev, D = 1.5 to 5.5 µc/cm2. Annealing embedded impurities within 30 min at 950aboutWith created signalground Istok-stock field and the degree of alloying of which more low-alloy, but less signalisierung areas.

The effectiveness of the method was evaluated by yield and by measuring two parameters of the test transistor with L = 1.2 µm and W = 1.6 ám, determine its korotkozernisty: voltage clamping Ucmand coefficient korotkokanal TOtothat represents a difference between the threshold voltage of the transistor when the two voltages on the drain relative to the source (Ucm1= 0.5 V, Ucm2= 5 V). MOS transistor is clinically, if Ucm2EPete.(EPete. = 5 V) and Kto0,2 Century, moreover, the estimated slope and the maximum drain current of the transistor, as well as its long-term reliability. The results of the measurements are shown in the table.

As Vij fast diffusing impurities (phosphorus) in addition to introduced in the same region slowly diffusing impurities (antimony), followed by the creation, simultaneously with the creation of signalisierung Istok-stock areas, regions, the degree of alloying of which more low-alloy, but less signalisierung areas, allows comparison with the prototype to weaken korotkokanal effects and at 1.03 - 1.2 times to increase the voltage clamping. As a consequence, the percentage of yield increases of 6.9 - 39,2%.

This is due to the decrease in field strength in the marginal areas of the source-drain by creating a smooth p-n junction.

A method of MANUFACTURING a MOS TRANSISTOR, comprising forming on the surface of a semiconductor silicon wafer of the first conductivity type shutter with vertical walls, the introduction of ion implantation in the plate on both sides of the shutter melanocephala impurities of the second type of provodimosti, creating low-alloy Istok-stock areas annealing embedded impurities, coating the surface with a stepped topography of the dielectric layer, creating anisotropic plasma etching caused parietal layer of dielectric regions, the introduction of ion implantation in the plate on both sides of the parietal areas melanocephala impurities of the second type provodimo aimed at weakening korotkokanal effects by smoothing of the diffusion profile Istok-stock areas, after the introduction of the plate on both sides of the parietal areas melanocephala impurities of the second conductivity type in the plate in the same areas implement bystrodeystvuschy impurity of the same conductivity type, the ratio of the speeds of diffusion melanocephala and bystrozagruzhaemaya impurities chosen from the condition of education in the subsequent annealing diffusion of signalisierung areas intermediate areas with a degree of doping of less than signalisierung, and greater than for low-alloy regions.

 

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