Signature analyzer

 

(57) Abstract:

The invention relates to computing and allows you to extend the functionality of the analyzer by identifying non distorted portion of the input sequence and the nature of the distortion: technocrate, nechernosemya, errors of the transition to the third state, and determining the occurrence of distortion directly in the process of forming the signature. The analyzer contains shaper 1 time signals, two comparator 2, 3, two shaper 4, 5, two NOT gates 6, 7, the three elements 8, 9, 10, element OR 11. It introduced the shift register 16, two blocks 17, 18 parity, block 19 controls, three blocks 20, 21, 22 of the memory unit 23 detecting a third condition, two trigger 24, 25, the element OR NOT 26. 2 C. p. F.-ly, 2 tab., 9 Il.

The invention relates to computer technology and can be used for monitoring and diagnosis of digital nodes having outputs tristate.

Known signature analyzer [1], containing two blocks down the block data distribution, the counter, the EXCLUSIVE OR element, data input, two output groups non distorted plot, engraved, the input shift Uch the formation of consistency in his uniqueness.

The disadvantages of this analyzer is the inability to determine whether errors before the end of the period of forming the signature, the inability to determine the location of several distorted areas, as well as the nature of the incident distortion - jednokratna error, error associated with transitions to the third state.

Closest to the proposed technical essence is a signature analyzer [2] , containing the shaper time signals, two driver signatures, two comparator element and two elements And, moreover, the trigger output of the shaper time signal is a control input "Start-stop" analyzer, the inputs of the first and second Comparators are combined and connected to the information input of the analyzer, the output of the first comparator is connected to the input element and the first input of the first element And the output of the second comparator is connected to the second input of the first element And the first input of the second element, And the output element is NOT connected to the second input of the second element, And outputs shapers signatures are the outputs of the signature analyzer. The analyzer also contains the second element is NOT, the third element And the element OR, and VA information connected to the input of the second element and NOT the information input of the second driver signature the output of the second element is NOT connected to the first input of the third element And a second input connected to the output of the first element, third and fourth inputs of the first through third elements And are connected to each other and connected respectively to synchronou analyzer and the output driver transient signals, the outputs of the first and third elements And is connected to the output element OR the state clock inputs of the first and second shapers signature connected respectively to the outputs of the OR element and the second element And. Known signature analyzer provides generation of signatures separately for the levels "0" and "1" and the level of Z (the third state).

However, this analyzer is not possible to determine the location and nature of arising distortion (technocrate and nechernosemya), as well as the fact distortion may occur before the end of the period of the formation of structures.

The aim of the invention is to enhance the functionality of the analyzer by identifying non distorted area in the code sequence, as well as the nature of the distortion: technocrate or nechernosemya errors, errors when moving in the Z-state, and determining the occurrence of a travesty is the overall driver of temporal signals two Comparators, two driver signatures, two element, three-element, And the element OR to the start of the shaper time signal is a control input "Start-stop" analyzer, the inputs of the first and second Comparators are combined and connected to the information input of the analyzer, the output of the first comparator is connected to the input of the first element and the first input of the first element And the output of the second comparator is connected to the second input of the first element And the first input of the second element And the first element is NOT connected to the second input of the second element, And the information input of the first driver signature connected to the information input of the analyzer, the output of the second comparator is connected to the input of the second element and NOT the information input of the second driver signatures, the output of the second element is NOT connected to the first input of the third element And a second input connected to the output of the first element, third and fourth inputs of the first through third elements And interconnected and connected to synchronou analyzer and the output driver transient signals, the outputs of the first and third elements And connected to inputs of the OR element, the state clock inputs of the first and second forms the setting of the analyzer is connected to the corresponding inputs of the first and second shapers signature put the shift register, two parity block, control block, three block of memory, the detection unit of the third state, the first and second triggers, the element OR NOT, when it inputs the initial setup of the shaper time signals, a shift register, a control unit, the detection unit of the third state, the first and second triggers are combined and connected to the input of the initial setup of the analyzer, the information input shift register is connected to the information input of the analyzer, the outputs of the shift register and the first driver signature connected respectively with the groups of inputs of the first and second block of parity, the state clock inputs shift register, and a control unit connected to the output element OR the control input of the control unit is the input of the analyzer Read-write, group address and control outputs of the control unit are connected to the address bus and bus control signals with respective groups of inputs of the first, second and third memory blocks, the information outputs of which are connected respectively with individual inputs of the first and second block of parity information input detection unit of the third state, the input control and the second triggers are combined and connected with engravida control unit, the information inputs of the first and second triggers are connected respectively to the outputs of the first and second block of parity, the outputs of the first and second triggers, and an information output unit detecting a third condition respectively connected to information inputs of the first, second and third memory blocks and the inputs of the element OR NOT, the output of which is connected to the first Manager of the input of the shaper time signals, the second control input connected to the second input of the Read-write analyzer.

The control unit contains two counters, decoder and pulse shaper, and the United inputs the initial installation of the first and second counters pulse shaper form input the initial setup of the control unit connected to the input of the initial setup of the analyzer, engraved first counter is synchronator control unit that is connected to the output element OR the outputs of the first counter connected to the inputs of the decoder, the input selection mode which is a control input of the control unit, and connected to the control input "Read-write analyzer, the first and second outputs of the decoder are the control outputs of the unit, t the outputs of the block, the input of the start pulse shaper connected to the output end of the account of the first counter, the output of the pulse shaper, which synchronator control unit, connected to the state clock inputs of both triggers and detection unit of the third state.

The detection unit of the third state contains two triggers, the comparison circuit element And the pulse shaper, and engraved first trigger is input to the control unit detecting a third state and is connected to the output element And the output of the first flip-flop connected to the first input of the comparison circuit, the second input of which is an information input unit and is connected to the output of the third memory block, the output of the comparison circuit is connected to the information input of the second trigger, the output of which is an information output analyzer input the initial installation of the first flip-flop coupled to the output element, And the first input is combined with the inputs of the initial installation of the second trigger and pulse shaper is input the initial setup of the unit and connected to the input of the initial setup of the analyzer, the second input element And is connected to the output of the pulse shaper, engraved which combined with synchronator verratene is the following. The input information stream is divided into segments of length 16 bits, which are recorded in the shift register. Any decemnotata error for 16 clock synchronization, changes the parity segment information sequence and the first parity block produces an error signal. Thus, all nechernosemya errors are detected directly in the process of forming the signature. The parity of the contents of the first shaper signatures can detect half technocratic distortion of the input sequence. As the driver signature - linear device, it is fair superposition principle is true of the input sequence and sequence errors. Thus the signature distorted sequence is the sum modulo two of the signatures of the true sequence and sequence errors. The current signature changes the parity, if true to the signature sequence added the signature sequence error, which is odd.

Consider this situation.

In table. 1 shows signatures of a single error occurring in one of the 16 clock synchronization.

As conatact, the signature sequence of errors is odd, is calculated by the formula

P(K) = M(K)/N(K), where K is the number of multiple-error;

M is the number of combinations leading to nechetnoi signature;

N is the total number of combinations of errors K-th order.

Calculate the probability for the sequence consisting of two errors:

N(2)= = = = 120,, where Cmn= the number of combinations of n by m;

M(2) = 6.10 = 60 as the number of even signature sequences consisting of one error, is equal to six, and even equal to ten. The signature sequences consisting of two errors, odd, if you group a single error so that one of the sequences gave even the signature, and the other is odd. Other combinations lead to an even signature.

Thus P(2) = = 0,5..

Probabilities for other sequences of error can be calculated similarly:

R(14) = R(2) = 0,5;

R(12) = P(4) = 0,5055;

R(10) = P(6) = 0,496;

R(8) = 0,5035.

Therefore , if 16 bars is 2, 4, 6, 8, 10, 12, 14 errors in half of the cases it is detected by the second parity block.

In Fig. 1 shows a functional diagram of the analyzer of the village of the Whigs register; in Fig. 5 is a diagram of the parity block, and Fig. 6 is a diagram of the control unit of Fig. 7 is a diagram of the memory block of Fig. 8 is a block circuit diagram of the detection of the third state of Fig. 9 is a timing diagram illustrating detection technocrates errors.

Signature analyzer (Fig. 1) contains shaper 1 time signals, the first 2 and second 3 Comparators, shapers 4, 5 signature, elements, NOT 6, 7, items 8, 9, 10, element OR 11, entry 12 "Start-stop" information input 13 input 14 sync input 15 initial setup, the shift register 16, the blocks 17, 18 parity, unit 19 of the control units 20, 21, 22 of the memory unit 23 detecting a third state, the first 24 and second 25 triggers, the element OR NOT 26, entry 27 "Read-write".

The inputs of the first 2 and second 3 Comparators combined and connected to the information input 14 of the analyzer, the input of the start of the shaper 1 time signal is a control input 12 "Start-stop". The output of the first comparator 2 is connected to the input of the first element 6 and the first input of the first element And 8, the output of the second comparator 3 is connected to the second input of the first element And 8 and the first input of the second element And 9. The output of the first element 6 is connected to a second input of the second cell battery (included) is. The output of the second comparator 3 is connected to the input of the second element 7 and an information input of the second imaging unit 5 signatures, the output of the second element 7 connected to the first input of the third element And 10, a second input connected to the output of the first element 6. The third and fourth inputs of the first through third elements 8, 9, 10 connected together and connected to synchronou analyzer 14 and the output of the shaper 1 time signals, respectively. The outputs of the first 8 and the third 10 elements And connected to inputs of the OR element 11, the state clock inputs of the first 4 and second 5 shapers signature connected respectively to the outputs of the OR element 11 and the second element 9. Inputs the initial setup of the imaging unit 1 temporary signals, shapers 4, 5 signature, shift register 16, block 19, the control unit 23 detecting a third state, the first 24 and second 25 triggers the joint and is connected to the input 15 the initial setup of the analyzer. Information input shift register 16 is connected to informationin input analyzer 13, the outputs of the shift register 16 and the first imaging unit 4 signatures are connected respectively with the groups of inputs of the first 17 and second 18 blocks of parity, and the state clock inputs shifts the is a log analyzer 27 "Read-write", group address and control output unit 19 controls are connected to the address bus and bus control signals with respective groups of inputs of the first 20, second 21, 22 third memory blocks, information inputs which are connected respectively with individual inputs of the first 17 and second 18 blocks of parity information input unit 23 detecting a third state, the control input of which is connected to the output of the second element And 9. The state clock inputs of the block 23, the first 24 and second 25 triggers combined and connected with synchronator unit 19 controls. The information inputs of the first 24 and second 25 triggers are connected respectively to the outputs of the first 17 and second 18 blocks of parity, the outputs of the trigger 24, 25, and an information output unit 23 detecting a third condition respectively connected to information inputs of the first 20, second 21 and third 22 blocks of memory and the inputs of the element OR NOT 26, the output of which is connected to the first Manager of the input shaper 1 time signals, the second control input connected to the input 27 of the Read-write analyzer.

Unit 19 controls (Fig. 6) contains two counters 28, 29, the decoder 30 and the imaging unit 31 of the pulse. Inputs initial installation of the unit 19, which is connected to the input 15 the initial setup of the analyzer. Engraved first counter 28 is synchronator unit 19 of the control that is connected to the output element OR 11. The outputs of the first counter 28 are connected to the inputs of the decoder 30, the input selection mode which is a control input unit 19 and is connected to the input 27 of the Read-write analyzer. The output of the decoder 30 forms a bus control signals analyzer, engraved decoder 30 is connected to synchronator second counter 29, the outputs of which form the address bus analyzer. The starting shaper 31 pulse is connected to the output end of the account of the counter 28. The output of the shaper 31 pulse is engravida unit 19 connected to the state clock inputs of the trigger 24, 25 and the block 23.

Unit 23 detecting a third state (Fig. 8) contains triggers 32, 34, scheme 33 comparison, the And gate 35 and the shaper 36 pulse. Engraved the first flip-flop 32 is input to the control unit and connected to the output of the second element And 9, the trigger output 32 connected to the first input circuit 33 of the comparison, the second input of which is an information input unit and coupled to the output unit 22 of the memory. The output of the circuit 33 comparison connected with the information input vtoroy. Input the initial installation of the trigger 32 is connected to the output element And 35, the first input of which is combined with the inputs of the initial installation of the second trigger 34 and shaper 36 pulse is input initial installation of the unit 23 and podcacher to the input 15 the initial setup of the analyzer. The second input element And 35 is connected to the output of the shaper 36 pulse, engraved which combined with synchronator the second trigger 34 is synchronator block and connected to engravidou unit 19 of the control.

Shaper 1 time signals (Fig. 2) is designed to control a loop formation signatures and performed on circuits DD1 - CRM, DD2 - CRL, DD3 - CRL.

The comparator 2 is designed for quantization of the input signal on two levels: logic "1" and the third state and which is made on the chip CRS (Digital and analog integrated circuits. Directory./Edited by S. C. Jakubowski. - M.: Radio and communication, 1989 (1)). The comparator 3 is designed for quantization of the input signal on two levels: logic "0" and the third state and which is made on the chip CRS.

Conditioners 4 and 5 signatures (Fig. 3) are designed to compress the input sequence in the signature and executed on the mikros is, The .180).

Elements 6 and 7 are used for the inversion of the signals from the Comparators 1 and 2, and represent the inverted outputs of the Comparators CRS. Items 8, 9, 10 are used for separating a sync signal in three ways depending on the logical state of the input information and is performed on the chip CLI (1). Element OR 11 is designed to combine signals coming from the outputs of the elements And 8 and 10, and is made on the chip CRL (1).

The shift register 16 (Fig. 4) is intended for accumulation sixteen bits of the input sequence and performed on circuits DD1, DD2 - KIR (1),

The blocks 17 and 18 parity (Fig. 5) are used to determine the parity of the input information and is performed on circuits DD1, DD2 - CRIP (awl Century Popular HP digital chip. The Handbook. - M.: Radio and communication, 1987 (2)).

Unit 19 controls (Fig. 6) is designed to generate cycles of read and write blocks 20, 21, 22 memory and outputting the strobe for latching output signals from the blocks 17, 18 parity and circuit 33 comparison in block 23. It contains two counters 28, 29, the decoder 30 and the imaging unit 31 of imulse. The first counter 28 of the block 19 is glaie. The second counter 29 unit 19 is designed to generate the addresses of the blocks 20, 21, 22 memory and executed on the chip DD4, DD5, DD6 - KIE (2). The decoder 30 unit 19 controls is designed to generate control signals of the blocks 20, 21, 22 memory and clocking the second counter 29 and executed on the chip DD3 - CRE (Lebedev O. N. Memory chips and their applications. - M.: Radio and communication, 1990 (3)). Shaper 31 pulse unit 19 is designed to generate gate on the block 23 and the trigger 24, 25 of the analyzer and executed on the chip DD2 - KAG (1).

Blocks 20, 21 memory (Fig. 7) are intended for storage of parity information of the controlled sequence. Unit 22 of the memory is for storing information about the transitions to the third state. In this case they are made on the circuits DD1 - KRUA (3).

Unit 23 detecting a third state (Fig. 8) is intended for fixation of the signal transition of the input sequence in Z state. It contains triggers 32, 34, scheme 33 comparison, the And gate 35 and the shaper 36 pulse. The first trigger 32 unit 23 serves to remember the fact of occurrence of a third state and which is made on the chip DD1.1 - KR531TM2 (1). Scheme 33 comparison unit 23 is designed for generating the error signal p IC DD4 - CLP (1). The second trigger 34 unit 23 is designed to commit the error signal at the output of the circuit 33 comparison strobe signal from block 19 of control and performed on the chip DD1.2 - KR531TM2 (1). Element And 35 of the block 23 is designed to combine the signals from the input initial setup of the analyzer and the output of the pulse shaper unit 23 and executed on the chip DD2 - CRL (1). Shaper 36 pulse unit 23 is designed to generate a signal initial setup for the first flip-flop 32 and executed on the chip DD3 - KAG (1).

The first 24 and second 25 triggers analyzer intended to commit the error signals at the output of the first 17 and second 18 blocks of parity, respectively, and performed on the chip KR531TM2 (1). The element OR NOT 26 is designed to combine the error signals from outputs of the first 24 and second 25 trigger and the second trigger block 23 and executed on the chip KR531LE7 (1).

The analyzer works as follows.

Before the start of the working cycle to the input 15 initial setup signal that causes the analyzer to its original state. Under the influence of this signal at the output of the shaper 1 temporary signal level is set to a logical "0", blocking responsive the register 16, the counters 28 and 29 of the block 19 controls. Shaper 31 pulse unit 19 of the control is set to one state. Set in the zero state of the trigger 32 and 34 of the block 23 detection of a third state, and the shaper 36 pulse of this unit is installed in one state. Set in the zero state, the first 24 and second 25 triggers.

Input 27 "Read-write" is a logical "0" which means the installation mode "read". This signal allows the shaper 1 time signals responsive to the condition it first control input, and switches the decoder 30 unit 19 controls on the formation of the loop "read" blocks 20, 21, 22 memory. When applying to the control input 12 of the Start signal shaper 1 time signals permit the passage of synchronization signals from input 14 through the elements 8, 9, 10, which together with the Comparators 2 and 3, items 6, 7 OR 11 and share information flow information to the input 13 of the analyzer into two parts.

The first component, formed by the signal levels logic "0" and "1", folded in signature in the imaging unit 4 in synchronization with the output element OR 11. The second component is ignal with the output of the second element And 9. Synchronously with the imaging unit 4 signatures is entering input information in the shift register 16. In this case, the bit shift register is chosen equal to 16. Current information in the first imaging unit 4 signatures and shift register 16 is subjected to a parity respectively in blocks 18 and 17, a single input which receives the parity bit of the blocks 21 and 20 of the memory. If the number of units in the content of units 4 and 16 together with a bit coming from blocks 21 and 20 memory is odd, then the blocks 18 and 17 produce error signals supplied respectively to the information inputs of the second 25 and the first 24 triggers. Fixing errors in triggers 25 and 24 occurs on strobe pulse from engravida unit 19 of the control.

Consider the detection technocrates errors, i.e. the situation when 16 cycles synchronization is two distortion of the input information sequence (Fig. 9). This type of error is detected by a chain consisting of blocks 4, 18, 21 and 25 (Fig. 1). The first counter 28 unit 19 controls (Fig. 6) counts 16 pulses coming from the output of the OR element 11 (Fig. 19a) and starts the shaper 31 pulse unit 19 of the control, which produces a strobe pulse which indicates the input information, containing two distortions (Fig. 19b). In the 16th step of synchronizing the second block 18 controla parity generates at its output an error signal (Fig. 19c), which is fixed in the second trigger 25 on the front strobe with engravida unit 19 (Fig. 19g).

The output of the second trigger 25 is set to the logical state "1" (Fig. 19D), leading to the setting of the output element OR NOT 26 stop signal analyzer. This signal acts on the first control input of the shaper 1 time signal that causes at its output a logical "0" (Fig. 19th), which prohibits the passage of signals from the input 14 of the analyzer through the elements 8, 9, 10. The process of forming the signature is interrupted. Chain consisting of blocks 16, 17, 20, 24, works in a similar way when it detects an odd number of distortions in the input information sequence.

In parallel with parity unit 23 detecting a third condition captures the presence of transitions in the state within 16 clock cycles from the output element OR 11. The first trigger 32 unit 23 (Fig. 8) fixes the sync pulse coming from the output element And 9 to the input of the control unit 23. The third block memory 22 outputs the information input is x clock output element OR 11, comparing circuit 33 of the block 23 with the output information of the trigger 32. In the presence of the error signal at the output of the circuit 33 comparison block 23 it is latched in the second trigger 34 unit 23 strobe pulse from engravida unit 19 controls. At the same time run the shaper 36 pulse unit 23 that generates a signal that causes the first trigger 32 unit 23 through the element And 35 of the block 23 in the initial state. The error signal from the information output unit 23 through the element OR NOT 26 acts on the first control input of the shaper 1 time signals, which leads to the stop of the analyzer. If the blocks 17, 18 parity and unit 23 detecting a third state not reveal the presence of errors, the process of formation signatures in blocks 4 and 5 continues to feed the input of the analyzer 12 "Stop"signal.

The decoder 30 unit 19 of the control generates the control signals necessary for the operation units 20, 21, 22 memory in read-only mode", and generates the synchronization signal for increasing the content of the second counter 29 of the block 19, which forms the address for blocks 20, 21, 22 memory. Bit counter 29 is determined based on the length of the output information sequence. In this case, if the length of the sequence is s formers 4 and 5 signatures removed signature of the input sequence for comparison with the original. When you stop the analyzer according to the error signal from the output of the element OR NOT 26 outputs a second counter 29 block 19 management includes the number of the distorted segment of the input sequence and outputs of shift register 16 is itself distorted segment. The state of the outputs of the triggers 24 and 25 and an information output unit 23 determines the nature of error that occurred (see table. 2).

To remove the source signature of parity information and the transitions in the Z-state at the control input 27 of the analyzer signal of logical "1" setting for the unit 19 controls the mode "write" and for prohibiting shaper 1 interrupt synchronization input 14 when receiving the error signal from the output of the element OR NOT 26. Data outputs of the trigger 24, 25 and the block 23 are recorded in the blocks 20, 21, 22 memory management unit 19. The work of the other blocks analyzer similar modes of detection technocratic errors and bugs on the third condition.

1. SIGNATURE ANALYZER containing shaper temporary signals, two Comparators, two driver signatures, two element, three-element, And the element OR to the start of the shaper time signals is whodo the ode analyzer, the output of the first comparator is connected to the input of the first element and the first input of the first element And the output of the second comparator with a second input of the first element And the first input of the second element And the first element is NOT connected to the second input of the second element, And an information input of the first driver signature connected to the information input of the analyzer, the output of the second comparator is connected to the input of the second element and NOT the information input of the second driver signatures, the output of the second element with the first input of the third element And a second input connected to the output of the first element, the third and fourth inputs of the first through third elements And the joint and connected to synchronou analyzer and the output driver transient signals, respectively, the outputs of the first and third elements And are connected with the inputs of the element OR the state clock inputs of the first and second shapers signature connected respectively to the outputs of the element OR the second element And the input of the initial setup of the analyzer is connected to the inputs of the initial installation of the first and second shapers signature, characterized in that, to increase functionality by defining R is CI, error when moving in the Z-state, as well as determining distortion may occur directly in the process of forming the signature analyzer contains a shift register, two parity block, control block, three block of memory, the detection unit of the third state, the first and second triggers, the element OR NOT, and inputs the initial setup of the shaper time signals a shift register, a control unit, the detection unit of the third state, the first and second triggers are combined and connected to the input of the initial setup of the analyzer, the information input shift register is connected to the information input of the analyzer, the output of the shift register and the first driver signature - information inputs respectively of the first and second block of parity, the state clock inputs shift register, and a control unit connected to the output element OR the input of the Read-write control unit is input Read-write analyzer, group address and control outputs of the control unit connected to respective groups of inputs of the first, second and third memory blocks, the information outputs of which are connected respectively with individual inputs of the first and what hodom second element, And the state clock inputs of the detection unit of the third state, the first and second triggers are combined and connected to the output of the synchronization control unit, the information inputs of the first and second triggers are connected respectively to the outputs of the first and second block of parity, the outputs of the first and second triggers, and an information output unit detecting a third state, respectively with information inputs of the first, second and third memory blocks and the inputs of the element OR NOT, the output of which is connected to the first input of the start of the shaper time signals, the second input of the start of which is connected to the input of the Read-write analyzer.

2. The analyzer under item 1, characterized in that the control unit contains two counters, decoder and pulse shaper, and the United inputs the initial installation of the first and second counters and pulse shaper to enter the initial setup of the unit, engraved first counter - synchronator block, the outputs of the first counter connected to the inputs of the decoder, the control input which is the input of the Read-write unit, the first and second outputs of the decoder are a group of control outputs of the unit, a third output of the decoder with the AC pulse shaper connected to the output end of the account of the first counter, the output of the pulse shaper is output synchronization unit.

3. The analyzer under item 1, characterized in that the detection unit of the third state contains two triggers, the comparison circuit element And the pulse shaper, and engraved first trigger is input to the control unit, the output of the first flip-flop connected to the first input of the comparison circuit, the second input of which is an information input unit, and the output is connected to the information input of the second trigger, the output of which is an information output unit, the output of the initial installation of the first flip-flop coupled to the output element And the first input of which is combined with the inputs of the initial installation of the second trigger and pulse shaper and an entry initial setup of the unit, the second input element And is connected to the output of the pulse shaper, engraved which combined with synchronator the second trigger is synchronator block.

 

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4 cl, 1 dwg

FIELD: information technologies.

SUBSTANCE: device to compare data in computer system comprises at least two actuator units and comparator, besides, data comparison is carried out in comparator, and each actuator unit processes input data and generates output data, at the same time actuator unit is arranged with the possibility to communicate to the comparator that it is not necessary to compare subsequent element of output data with element of output data, at least of the second actuator unit, afterwards, comparison of these at least two elements of output data takes place.

EFFECT: increased safety of computer system operation, using various actuator units and software.

11 cl, 3 dwg

FIELD: information technology.

SUBSTANCE: system of gathering and processing information for integrated security systems of facilities has control computers, automated workstation computers and servers connected over an Ethernet. Control computers have multi-port devices whose like ports are connected in pairs through interface converters to groups of transceivers which are connected to interface converters. The transceivers are connected by communication lines to peripheral devices.

EFFECT: single failure of a server, an automated workstation computer, a computer network component, a control computer, a multi-port device or interface converter does not affect operation of a system when a transceiving device fails or when a line of communication with a peripheral device breaks, there is loss of communication with only one peripheral device.

9 cl, 2 dwg

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