A device for decoding a convolutional code


H03M13/12 -

 

(57) Abstract:

The invention relates to systems for the transmission of information via communication channels and can be used in devices for decoding by the Viterbi algorithm. The purpose of the invention is improving the noise immunity of the device by providing the automatic gatweway and block synchronization when working on real communication channels for code speeds of 1/2 and 3/4 (perforated) code. The aim is achieved in that in a device for decoding a convolutional code is entered three counters 5, 6, 7, three elements OR 8, 9, 10, the EXCLUSIVE OR element 11, a decoder 12, a switch 13, four K = bit multiplexer 14 - 17, k elements are NOT 181-18ktwo k= bit register 19, 20, valve 21 pulses, block 22 computing metrics of the branches. 1 C.p. f-crystals, 4 Il.

The invention relates to systems for the transmission of information via communication channels and can be used in devices for decoding by the Viterbi algorithm.

The closest in technical essence to the claimed is a device consisting of correlators, n-Vodolaga comparator, n memory registers, the n blocks of the addition-comparison-selection, each of which contains two adder and comparator, bambuterol, reversible shift register solution, 2 n shift registers decisions, 2 n triggers, 2 n items, 4 n elements And, 2 n elements OR.

A disadvantage of the known device is the low immunity due to the fact that the device does not automatically provide gatweway synchronization with real communication channels for different code speed code.

The aim of the invention is to increase the noise immunity of the device by providing the automatic gatweway and block synchronization when working on real communication channels for code speeds of 1/2 and 3/4 (perforated code).

In Fig. 1 shows a functional diagram of the device of Fig. 2 is a functional diagram of the unit for computing the metrics of the branches of Fig. 3 is a functional block diagram of a decision; Fig. 4 is a block diagram of the memory block solutions.

A device for decoding a convolutional code (Fig. 1) consists of n blocks (11-1nchoice solutions, a group of registers 21-2nn+1-Vodolaga comparator 3, block 4 memory solutions, counters 5, 6, 7, items, OR 8, 9, 10, EXCLUSIVE OR element 11, a decoder 12, a switch 13, a k-bit multiplexers 14-17, k elements are NOT 1822 calculate the metrics of the branches (Fig. 2) contains a k-bit multiplexers 23, 24, items, OR 251-25k, 261-26kthe adders 27-30.

Unit 1 selection decisions (Fig. 3) consists of item 31 of the comparison, the switch 32, adders 33, 34.

Unit 4 memory solutions (Fig. 4) consists of n channels 351-35nprocessing, each of which corresponds to one node of the trellis diagram, item, OR 36, of the two shift registers 37, 38. Each channel processing consists of five switches 39-43, reversible shift register 44, the two shift registers 45, 46, trigger, 47, item 48, item BAN 49, item, OR 50, the trigger 51 item 52 item PROHIBITION 53, item, OR 54.

A device for decoding a convolutional code is as follows.

The device has two possible States gatweway synchronization with R = 1/2 because of the ambiguity in determining the exact matching of the phases of the received signals and values coded signals always have a place in a decoding apparatus, and the four possible States of synchronization with R = 3/4 (two of them are similar to the conditions at R = 1/2 and two more are due to the ambiguity of the definition of the beginning of the block of symbols over which was held n the torus ensures correct operation of the device.

When R = 1/2 for the first state, the counter 6 is in state 00, i.e., on its first and second outputs set the potential logical "0". In this case the coded signal 1 and the encoded signal 2 from the inputs of the first channels of the multiplexers 14 and 15, respectively, under control of a signal from the first output of the counter 6 are held on the outputs of these multiplexers. From the outputs of the multiplexers 14, 15 coded signals received at the inputs of the first channels of the multiplexers 16, 17, respectively, where the control signal with the second output of the counter 6 are part of the output of these multiplexers and further to the first and second information input unit 22 to calculate the metrics of the branches. For R = 1/2 dispenser 21 pulses under the control of the signal speed control devices do not produce signals of the ban on their second and third outputs. In the result of joint work blocks 22, 1 and 4 at the output of block 4 memory solutions produces decoded information. For unit 4 memory solutions comparator 3 compares all metrics of the States, arriving on the first to n-th inputs of the comparator 3 outputs of registers 21-2nmetrics of States, with each other with a certain threshold value, arriving at the (n+1) th input is STS. The comparator 3 generates a check box on the output that matches the input with the minimum metric of the state, which is also less than the threshold value. This option is fed to the control inputs of block 4 memory solutions and is used to start a preliminary search. If there is no metric of the state, exceed the threshold value, which may occur either when a significant random distortion of the encoded signal, or when the incorrect synchronization of the device, the box on the outputs of the comparator 13 is not produced. Then the process starts preliminary search pulse from the first output of the distributor 21 pulses passing through the EXCLUSIVE OR element 11, the first input of which at this time is set to zero potential from the output of the OR element 8, and the element OR 9 on the n-th control input unit 4 memory solutions. The process starts preliminary search for a particular (n-th) of the host lattice diagram purposefully correcting ability of the device, but excludes breakdown processes of preliminary and final search and, therefore, ensures the normal decoding information in conditions of significant distortion of codiovan is 5 ka. When incorrect synchronization device is characterized by increased growth rate values of the metrics of the States, the frequency of the signals at the output of the EXCLUSIVE OR element 11 is increased, the filling time counter 7 counter 5, reset by the pulse from the output of the transfer counter 7 through the OR element 10, time to change your status to this value when the output of the decoder 12 a signal indicating incorrect synchronization device. This signal resets the counters 5, 7, and changes the state of the LSB of the counter 6 to 01, the value of the signal at its first output changes. Under the effect of this signal on the control inputs of the multiplexers 14, 15, the outputs of these multiplexers are signals from inputs of the second channel, i.e. there is a change of locations of the first and second coded signals of the device and the inversion of the first encoded signal, which is the condition for the transition to the second state when R = 1/2, which should be sustainable.

When R = 3/4, the operation of the device in the first and second States and the transition from the first to the second occur similarly to the operation of the device at R = 1/2. The difference lies in the work of Bloka at its second and third outputs, and the threshold value at the (n+1)-th input of the comparator 3 is supplied with the second input of the threshold device through the switch 13 controlled by the signal of the speed control device. If the second condition for R = 3/4, there is increased growth rate metrics of the States, again the signal at the output of the decoder 12, changes the state of the counter 6 to 10, then at its second output is a single potential, and on the ground - zero. While the multiplexers 14, 15 are similar to the first condition, and the multiplexers 16, 17 commute on the outputs delayed coded signals from outputs of the registers 19, 20, thus changing the location of the block of the perforation relative to the pulses of the ban applied to the block 22 calculate the metrics of the branches. When R = 3/4 the fourth condition, when the new position of the block perforation is happening again, the switching of the first and second coded signals to the multiplexers 14, 15. The state of the counter 6 in this condition 11.

The values of the first and second threshold devices are supplied to corresponding inputs of a switch 13, and the state of the counter 5 is set to the decoder 12 are determined experimentally or Mathematica is t R = 1/2 pulses to the first and second control inputs of the block 22 (prohibition 1, ban 2) not being received k-bit coded signals (soft decision) (C1, C2) with the first and second information inputs directly pass on the outputs of the multiplexers 23, 24 in inverted form at the outputs of the elements OR 251-25k. Adders 27-30 calculate four values of the metrics of the branches of the P00, R01, R10, R11corresponding to the four possible combinations of pairs of coded signals 00, 01, 10, 11. The values of the metrics of the branches correspond to the linear method of calculating the metrics of the branches (see j. Clark, J. Jr.. Kane. Encoding with error correction in digital communication systems. M. : Radio and communication, S. 239-240). If the code combination R = 3/4 for perforated code metrics calculation branches adders 27-30 is similar, however, in accordance with the method of perforation (matrix perforation) is periodic ban (equating to zero) of any of the coded signals (C1 or C2). For this purpose, the control unit 22 to calculate the metrics of the branches receives the appropriate signals. For example, when a signal at the first control input (ban 1) unit 22 from the outputs of the multiplexer 23 and the outputs of the elements OR 251-25k sets the potential logical "0" and pearl, prohibited by the signal from the second control input unit 22 to calculate the metrics of the branches.

Work unit 1 is as follows. Block 1 on each step produces at first outputs the new value of the metric condition for the corresponding node of the trellis diagram, and generates the second output information about the transitions on the trellis diagram of the code (solution). To calculate the new value of the metric condition on the outputs of the switch 32 (the first exit block 1) use the old values of the state metrics for the two nodes of the trellis diagram supplied with first and second inputs of the block 1 to the first inputs of adders 33, 34, the second input of which receives the values of the metrics of the branches of the third input unit 1. The output of the switch 32 is held to the minimum of the metric values at the outputs of the adders 33, 34, the control switch 32 is a signal of the comparison with the element 31 comparison. The signal of the comparing metrics of the States from the output of the comparison element corresponds to the solution and is supplied to the second output of block 1.

Unit 4 memory solutions operates as follows. In unit 4 memory solutions fail recovery path through trellis diagram of the code and the development of Dacapo trellis diagram, it can be argued that the oldest bits of information lies on the true path and matches correctly decoded information. Search this bit is called the pre-search. Storing in a memory of the solutions on the interval length In the preceding segment, where he carried out a preliminary search, you can restore the optimal way to determine the decoded information by reverse movement on the lattice diagram.

The process of preliminary search is performed using each channel 351-35nthe reverse processing of the register 44, the group of logic elements 47-50. The process begins after the introduction of the reversing register 44 decisions on the path segment length, and the switches 39 to 41 are in position A. For the next cut length switches 39-40 switch to position B and the direction of entry of the decision in reversing the register 44 is changed to the opposite. The process starts preliminary search is carried out by a single signal (flag) from outside through one of the n control inputs of the block 4 memory solutions, and the corresponding node with the minimum metric of the state. All the switches 42 on one tact switch in the floor of thenprocessing, by setting one of them is in state "1". In this channel, depending on what information came from the reversing register 44, a signal of logical "1" (selected) appears either on the output element 48 or the output element PROHIBITION 49 and, hence, the output of one (selected) items OR 50 in accordance with relationships between the elements 48, 49 and 50 different channels of processing. In the next cycle all switches 42 are switched to position B and the box with the output of the selected item OR 50 is moved into the corresponding trigger. This is repeated In cycles. Simultaneously with the process of the preliminary search for the cut, when the switches 39 to 41 are in position B, the information of the reversible register 44 is moved into the shift registers 46. This information is later used in the process of final search.

The final search is performed using each channel register 45 or 46, the logical elements 51-54 as follows. In the preliminary search in one of the triggers 47 recorded the check box corresponding to the end of the segment preliminary search. This option in the next cycle starts the process of final search. This will remain one of the trigger 51. At the same time the direction of movement information in the reversible registers 44 changing. Switches 39-41 switch in position and remain in this position In the following cycles. Information from reverse register 44 is moved into the shift registers 45, and the information coming from these shift registers, through the switch 41 is supplied to logic elements 52, 53 of the same channel processing. Later during the cycles In the process of final search is similar to the process of the preliminary search.

Decoded identity information is removed from the outputs of the elements OR 54 channels 352iprocessing (i = 1,...,i/2), are connected with inputs of the OR element 36. Information from the output of the OR element 36 is written in the shift register 37, at the end of reception of bits of information, it is rewritten in parallel in the shift register 38 where it comes from, starting with the oldest bits at the output of block 43 memory solutions.

Thus, the proposed device provides a stable work on real communication channels in conditions of significant accidental distortion of the transmitted encoded signal, which is provided by automatically find the correct variant of vetovo and block synchronization.

2. The device under item 1, characterized in that the computing unit metrics of the branches contains multiplexers, groups of items OR NOT, the adders and the bus logic zero, the outputs of the first multiplexer is connected to the first inputs of the first and second adders, the outputs of the second multiplexer is connected to a second input of the first and the first input of the third adder, the outputs of the elements OR NOT the first group is connected to the second inputs of the second adder and the first input of the fourth adder, the outputs of the element OR NOT the second group are connected to second inputs of the third and fourth adders, the outputs of the adders are output block, the first inputs of the multiplexers connected to the bus logic zero, the second input of the first multiplexer and the first input element OR NOT the second group are combined and the first Manager of the entrance block, the second input of the second multipl the third input of the first multiplexer and a second input elements OR NOT the first group are United and are the first infomration input unit, the third input of the second multiplexer and a second input elements OR NOT the second group are combined and the second information input unit.

 

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