The way of converting the information in the design and trace the basic matrix crystals and basic materity crystal (and its variants)

 

(57) Abstract:

Usage: the invention relates to microelectronics and is intended for use in the design and trace the basic matrix crystals (BMC) for analog and analog-to-digital semiconductor integrated circuits (IC). Essence: irregular grid, which most closely to each other are the contacts to the elements of the original BMC irregular matrix is converted into a rectangular grid of lines on which the trace in-circuit connections in accordance with the implemented scheme, and then the coordinates of the lines trace the rectangular grid are transformed to the original irregular matrix. The options presented are designed this way, analog BMC. 3 S. and 2 C. p. F.-ly. 14 Il.

The invention relates to microelectronics and is intended for use in the design and trace the basic matrix crystals (BMC) with a single-level system of connecting metallization, as well as analog and analog-to-digital semiconductor integrated circuits (IC) on their basis with increased requirements for size, the percentage yield of the chips and their selectivity how to convert information in the design and trace the basic matrix crystals with single system connecting metallization, consisting in the fact that in the field of basic matrix crystal place of the basic cell for trace lines in-circuit connections within and between them, in these zones the place and diffusion resistors jumper with

contacts to them, and these contacts and the contacts to the active regions of the cell elements of the matrix are placed in the nodes of a uniform grid, with a trace lines connecting metallization carried out along the lines of this grid.

Known for BMC, the conversion information in the design and trace, which is implemented in this way (see article: C. Bray, P. Irisson "A new gridded bipolar semicustom linear array family with CAD support"//J. of Semicustom ICs; 1986, v. 3, N 4, p. p. 13-20; H. L. Van Eeden : An Uncommited Linear Array Designed for Implementation on a Cate Workstation Array"//J. of Semicustom ICs; 1986, v. 4, N 1, p. p. 18-24).

The disadvantages of this method and BMC, designed on its basis, is the low density of the layout elements of the BMC and, as a consequence, large chip area, a large cost and low yield of the IC; low functionality BMC due to the uniformity of the used components: the length of the tire interconnects; optimal electrical parameters of transistors and other elements, the size of the active on the="ptx2">

Known method and the corresponding BMC closest to the technical essence and adopted as a prototype BMC is designed to transform the way information on a rectangular grid and described in the article N. L. Van Eeden "An Uncommited Linear Array Designed for Implementation on a Gate Array Workstation"//J. of Semicustom ICs; 1986, v. 4, N 1, p. p. 18-24.

BMC prototype consists of a substrate on which the formed elements of the BMC, and its periphery evenly placed isolated back biased p-n junction region has a square shape, designed to accommodate metallized pads for the pins of the crystal, which is placed between the elements of the BMC increased geometric dimensions, while the BMC contains duplicate symmetrically located cells, consisting of the set of elements of the BMC (resistors, capacitors, p-n-p and n-p-n transistors) and passive areas for laying metallic tracks interconnects, located between the cells and the periphery of the crystal with pads. Dimensions BMC-prototype 3,2x3,2 mm2; its elements are grouped in cells containing 206 diffusion resistors with a total resistivity 340 kω, capacitor 4, 116 n-p-n and 48 p-n-p of all three types, VK is nirov") is 374. The density of the composition BMC prototype is 37 elements per square millimeter square. Contacts to the active regions of all elements of the BMC are located in the nodes of a uniform rectangular grid, which is produced by the trace circuit connections.

The disadvantages of the prototype are small, the total number of components of the BMC with a significant chip area, low density layout elements, the low yield of IC and correspondingly high cost; long tyre interconnects; optimal parameters of transistors and other elements; limited functionality BMC due to the small number of types available transistors and other elements. This prevents the application of BMC in radio and television equipment, where necessary elements with different areas, the active elements with low noise and a wide range of operating currents, a large number of resistors of different part types with a resistivity and capacitors. These drawbacks with a one-tier system metallization is the price for convenience trace tires interconnects BMC way of converting information on a uniform rectangular selvadego deterioration of their electrical parameters.

The aim of the invention is to reduce the cost, increase the percentage of yield IC, increasing the density of the layout elements of the BMC and optimization elements required parameters while facilitating conflict-free trace and the possibility of using automated methods, as well as increased functionality of the BMC and the scope of application of the proposed method.

The aim is achieved in that first create the original irregular matrix by approximating elements and nodes of all valid runs of the metallization on the minimum allowable technological distance, or spend a couple of lines of tracks metallization violates the regulations on the gaps between them, then by increasing the size of the random matrix due to the flatness of all valid lines trace and establish between them the same distance form a regular matrix with the transformed relative to the source image elements (such a matrix is called a "tablet"), and the nodes of regular and irregular matrices correspond to each other, spend on a regular matrix, the nodes are connected according to the implemented circuit, and then transformiruyushchim with single trace line circuit connections for analog IC according to the first embodiment in addition enter the second cell, the third and fourth types, the first three types of cells have symmetrically relative to the Central horizontal and vertical axes of the crystal successively along the horizontal axis, cell of the fourth type have around cells of the second type, separating cells from each other, and the contact pads along the edge of the crystal uniformly placed elongated contacts to the substrate and epitaxial pinch resistors are n-type, and the cell of the first type is of the five pairs of coordinated n-p-n transistors of the first type and one of a pair of matched p-n-p transistors of the first type along the vertical axis of the crystal, the cell of the second type is of the three pairs of coordinated n-p-n transistors of the first type and two pairs of coordinated p-n-p transistors of the first type, spaced from the periphery to the center of the crystal along the vertical axis successively two pairs of n-p-n, a pair of p-n-p pair n-p-n and a pair of p-n-p transistors, the cell of the third type is of the three p-n-p transistors of the first type, two diodes, two diffusion jumpers and four n-p-n transistors of the first type, located respectively in two rows along the vertical axis of the cell, the cell of the fourth type is of the diffusion reeal cell and two n-p-n transistors of the first type, the collector region which is structurally integrated with resistive pocket, while between the contact sites of the crystal through each site, starting from the corner of the site along the short sides of the crystal are sequentially p-n-p transistors high power of the second type, MOS capacitors, and along the long sides of the crystal are arranged consecutively one through the space of n-p-n transistors high power of the second type and a region of n-type with different diffusion resistors are p-type and contacts to this area: in the base matrix with single crystal tracing lines in-circuit connections for analog and mixed IC according to the second variant impose additional cell of the second, third, fourth, fifth, sixth, seventh and eighth types, and in one part have a first rectangular area containing four identical cells of the first type, the mutual position which is symmetrical about the horizontal and vertical axes of the first rectangular region, and the cells of the first type along the horizontal axis in pairs shared by two symmetrical relative to the vertical axis of the first rectangular region of cells utoro is relatively horizontal and vertical axes of the first rectangular region of cells of the third type, moreover, the left and right outer sides of the area occupied by the cells of the first type have four pairs symmetric with respect to the horizontal and vertical axes of the first rectangular region of the fourth cell type, and each pair of upper and lower cells of the first type surrounding cells of the fifth type, in another part of the inner region of the crystal have a second rectangular area containing four identical cells of the sixth type, whitnee location which is symmetrical about the horizontal and vertical axes of the second rectangular region, and the upper and lower pairs of cells of the sixth type share a cell of the seventh type, elongated along the horizontal axis, and above the upper and below the lower pairs of cells of the sixth type have along the horizontal axis in the same cell of the seventh and two cells of the eighth type, symmetrical about horizontal and vertical axes of the second rectangular region, and the first and second rectangular areas are separated from the peripheral region of the crystal with the pads of the passive area of the p-type conducting tracks connecting metallization, which are regularly diffusione of the bridge, and along the edge of the Christ is the cell of the first type is composed of two identical, symmetrical about the horizontal axis of the cell subfragments containing each U-shaped area occupied by a chain of six n-p-n transistors of the first type, in the inner part of the recess which houses the differential pair of p-n-p transistors of the first type, and is parallel to the horizontal axis between subfragments cell is a resistive pocket of n-type with Catarina diffusion resistors of equal value p-type and contact him in the center, and two pairs of diffusion bridges along the edges of the pocket, the second cell type is located along the horizontal axis of the three differential pairs of n-p-n transistors of the first type, two capacitors on p-n junction and one of the diffusion resistor p-type large value in the form of a meander, the cell of the third type is composed of a pair of n-p-n transistors of the first type, three p-n-p transistors of the first type and the diffusion jumpers arranged in a row along the horizontal axis, the cell of the fourth type consists of two pairs of p-n-p transistors of the first type and a diffusion resistor p-type large value in the form of a meander along the vertical axis of the cell, the cell of the fifth type is composed of two condivi pocket of n-type contacts to the pockets, and four diffusion jumpers, the sixth cell of the type composed of two diffusion jumpers, resistive pocket in the form of a U-shaped isolated region of n-type resistors p-type different part types and contacts to it, in which in the area of bends symmetrically about the horizontal axis there are two n-p-n transistor of the second type, the collector of which is structurally integrated with isolated area, and inside the recess isolated area with resistors placed two pairs of n-p-n transistors high power of the third type, above and below these pairs of transistors directly near the ends of the isolated pockets with resistors symmetrically about the horizontal axis of the cell are placed one p-n-p transistor of the first type, and on the other side of the resistive pocket is a differential pair of such transistors, the cell of the seventh type is located symmetrically in a row along the horizontal axis, two pairs of n-p-n transistors of the first type and three pairs of n-p-n transistors of the second type, cell eighth type is located in a row along the horizontal axis resistive pocket of the n-type diffusion resistors p-type two type is ContactName the grounds of the crystal through each site, starting from the corner of the platform along one short side of the crystal, are consistently of a pair of matched p-n-p transistors high power of the second type, and along the other short side of the crystal are a pair of matched n-p-n transistors high power of the third type, while along the long sides of the crystal between the contact pads through each site are n-p-n transistors high power of the fourth type, a pair of p-n-p transistors high power of the second type and couples consisting of n-p-n transistor of the third type and p-n-p transistor of the second type.

In Fig. 1 shows a partial analog BMC for designing IC television and electronic measuring equipment with the indicated combination allowed for the passage of tyres connecting metallization lines representing the irregular grid of intersecting indirect lines of Fig. 2 presents the transformed fragment analog BMC Fig. 1; Fig. 3 presents a fragment of the edge region of the joining of two types of cells (section a-a) analog BMC for the design of the IC radio electronic equipment to designated collection allowed for the passage of the tire saalhausen each other); in Fig. 4 presents the transformed fragment BMC Fig. 3 marked in a special way segments of parallel lines of uniform grid (bold line), and Fig. 5 is presented for comparison of the transformed fragment BMC Fig. 3, no matter how he looked in the case, if it was designed so that the contact elements housed in the rectangular nodes, but irregular grid; Fig. 6 presents a General view of the BMC in the first embodiment for the design of IMS television and electronic measuring apparatus, and Fig. 7 presents the BMC cell of Fig. 6; Fig. 8, 9, 10 presents the structure of the n-p-n and p-n-p transistors BMC Fig. 6 with the specified options in the passing tire connecting metallization (shown by strizavka); Fig. 11 presents a General view of the BMC according to the second variant for the design of the IC radio electronic equipment of Fig. 12 presents the BMC cell of Fig. 11; Fig. 13 and 14 shows the structure of n-p-n and p-n-p transistors, and capacitor BMC Fig. 11 with these possible routs tire connecting metallization (shown by shading).

A fragment of a cell analog BMC for designing IC television and electronic measuring apparatuse different denominations of 3, the resistors on the basis of the separation diffusion 4, arranged in an irregular grid of intersecting indirect lines 5. In Fig. 2 in conventional scale presents the transformed fragment BMC Fig. 1 (hereinafter the converted image irregular matrix in the regular will be called "tablet"), the corresponding conditional image 6 on the tablet n-p-n transistors of the first type 1, the conventional image 7 on the tablet p-n-p transistor of the first type 2 conditional image diffusion resistors on the base layer 8 and the resistors on the layer separation 9, applied on a uniform rectangular grid of the tablet 10. A fragment of the edge region of the joining of two types of cells (section a-a) analog BMC for the design of the IC radio electronic equipment (Fig. 3) contains n-p-n transistors of the first 11, second 12 and third 13 types: p-n-p transistor of the first type 14, various diffusion resistors 15 and diffusion jumper (ponyri") 16. All of these elements are located on an irregular grid of intersecting indirect lines 5, which includes a conditional line segments 17 violates the regulations on the gaps between them (in particular, overlapping each other). In Fig. 4 in conventional scale presents the tablet fragment is LEGO 13 types - 18, 19, 20; cosmetic 21 p-n-p transistor of the first type 14; cosmetic diffusion resistors 22 and jumper 23. All these cosmetic applied on a uniform rectangular grid of the tablet 10, which includes marked in a special way segments of parallel lines 24 (bold line). In Fig. 5 in the same scale as in Fig. 3, irregular, but a rectangular grid 25 are deformed elements BMC 26 - 29, components of the same fragment, as in Fig. 3, but enlarged area. For ease of comparison areas undeformed (Fig. 3) and deformed (Fig. 5) fragments on the same sheet as Fig. 5, repeated image of Fig. 3. BMC for designing IC television and electronic measuring instruments (Fig. 6) contains cells (Fig. 7) of the first 30, 31 of the second, third 32 and fourth 33 types; control pad 34 (Fig. 6), p-n-p transistors high power of the second type 35, epitaxial pinch-effect transistors n-type 36, MOS capacitors 37, service marks 38, the contacts to the substrate 39, n-p-n transistors high power of the second type 40, diode 41 (Fig. 7), the diffusion jumper 42 and contacts to the resistive pockets 43. In Fig. 8, 9, 10 presents n-p-n and p-n-p transistors included in the BMC Phi the bars to the emitter and the base 47, 48; the area of the collector contact n+type 49; contacts to the collector 50; bus metallization 51; concentric region of the reservoir p+type 52; a base region of n-type 53, the emitter of the p-type 54; n+-area contact to the n-type 55. BMC for the design of the IC radio electronic equipment (Fig. 11) contains cells (Fig. 12) of the first 56, 57 second, third, 58, 59 fourth, fifth, 60, 61 sixth, seventh 62 and eighth 63 types; n-p-n transistors high power (Fig. 11) the fourth type 64; p-n-p transistors high power of the second type 65, the test transistors 66. In Fig. 13 and 14 exhibit n-p-n, p-n-p transistors and capacitor 67 to p-n junction, forming part of BMC Fig. 11, containing, in addition to named regions with different conductivity type, another upper division p+type 52, which is the upper capacitor plate 67, and contacts to this area 68. From the above set of cells, transistors, resistors, capacitors you can design other BMC (for example larger or smaller area), which in some cases can be useful. Such form BMC family of irregular matrices of the type described.

Conversion information when proektirovaniya schemes with single system connecting the metallization is carried out as follows. The resulting dense large number of heterogeneous elements of the BMC, such as BMC for designing IC television and electronic measuring instruments (Fig. 6-10), irregular grid indirect lines 5 (Fig. 1) passing through the possible routes of holding tire connecting metallization standard width, in which the nodes are the contact window to the active areas of the elements BMC 47, 48, 50 (areas of the emitter 46, 54; base 45, 53, 55. collector 44, 49, 52; the body of the resistor 3, 4, 36, etc.,), is converted to a regular rectangular grid of the tablet 10 (Fig. 2), which subsequently is the trace interconnects. When this pin the Toolbox BMC 47, 48, 50 in its original form (Fig. 1) are arranged to each other as closely as allow tehnologicheskie standards for minimum clearances between these areas in this process, either on the basis of the optimum electrical characteristics of each individual element 1, 2, 3, 4, 14, 35, 36, 37, 40, 41, 42, or for ease of passage through the elements end-to-end tires metallization 51. In any case, the arrangement of the elements of the criterion is their diversity and minimum sizes, increasing the density of whom shall agenie elements of the BMC on the tablet 6, 7, 8, 9 Pets in a distorted form, retaining only the relative position of the elements of the BMC and allowed lines for tire connecting metallization. Tracing mezhshemnyh compounds is carried out on the tablet BMC on a uniform rectangular grid 10. Further, as between the coordinates on the tablet 10 and the original irregular matrix 5 there is a match, any of the known methods (manually or automatically) the route from the tablet 10 is transferred to the original irregular matrix 5. Thus, despite the high density of the layout elements of the BMC, through the use of the tablet is achieved simplicity trace interconnects. Describe one of the possible methods of transformation of the coordinates of tyres connecting metallization with tablet coordinates of the lines of the original BMC. Allowed for the passage of the tire metallization horizontal and vertical broken lines on the original BMC 5 are numbered in order from left to right and top to bottom. Then information separately about the vertical and separately the horizontal line 5 is fixed (for example in the form of a table), and the description line contains the line number and coordinates of feature points, for example the coordinates of the start line, end and points isomeros m to line n, parallel to the axis Y, is written as: l, m, n[(xm, yl), (xh, y1), (xn-1, yk), (xn, yk)] , where l is the number of the horizontal lines of the non-uniform grid; m, n is the number of vertical lines irregular grid; (xm, yl), (Xh, yl), (xn-1, yk), (xn, yk) - coordinates of the characteristic points of this line on the original BMC. Thus is formed an array of data (description of source BMC) in the coordinates of allowed lines for passage of a tire metallization. Given the frequency of occurrence of fragments BMC may be formed descriptions BMC not entirely, but ofragment. The relevant lines of uniform grid 10 tablet BMC Fig. 2 are assigned the same number as line 5 of Fig. 1, thereby providing them one-to-one correspondence. The description mentioned a dedicated segment on the tablet in this case will be presented in the form: l, m, n, [(m, l), (n, l)] , where l, m, n is the appropriate number of grid lines of the tablet. When converting the coordinate information of the characteristic points of this segment (on a uniform grid they coincide with the start and end nodes) in the source view BMC operator node numbers of the tablet (m, l); (n, l) will cause the source BMC appropriate e is>, (xn-l, yk, (xn, yk). Thus, the length of the bus metallization with tablet can be uniquely real transformed into a segment of the original BMC. The described process can be automated.

In those cases, when the BMC, such as BMC for designing IP radio electronic equipment of Fig. 11-14, contains several different types of cells (fragments), on the border of their dock can be a situation when in one section (a-a) (Fig. 3) in different cells 61, 62 will be unequal number of lines allowed to hold tire connecting metallization 5. In this case, to preserve the continuity and uniformity of the tablet 10 (Fig. 4) in some areas of the original BMC (Fig. 3) provides for multiple line segments 17 (in particular, two, Fig. 3) under the bus misordering violates the regulations on the gaps between them (in particular, superposed on each other, Fig. 3). Each of these segments is converted to the corresponding on the tablet 10 (Fig. 4) cut parallel lines of uniform grid 24 (in particular, two, Fig. 4) is marked on the tablet 10 in a special way (in particular, in bold lines, Fig. 4). When the trace on the Board is 10 Fig. 4, which when converted back to the original view in Fig. 3 will move in the corresponding period of 17 a single line, when conducting along which the standard bus metallization standards for clearances with the adjacent tires will not be violated, because other segments of lines 17 on the original BMC 5 Fig. 3 in this case, under the conduct of tyres interconnects are unused. This rule complements rule transformations of coordinates tire metallization with tablet coordinates of the original BMC and significantly extends the application of the proposed method, in particular for analog and analog-to-digital labs, which use a wide range of different types of cells (fragments) and items. In the rest of the layout rules elements BMC (Fig. 11-14) 11, 12, 13, 14, 15, 16, 36, 64, 65, 67, as well as the location of the contact Windows to the active areas of the elements of the BMC (47, 48, 50) (areas of the emitter 46, 54, base 45, 53, 55, collector 44, 49, 52, of the body of the resistor 15, 16, 36 and so on ) remain the same as for BMC Fig. 6-10. Also Pets distorted elements of the BMC on the tablet 18, 19, 20, 21, 22, 23 (Fig. 4), which maintains only the relative position of the elements of the BMC and allowed lines for tire connecting metallization.

The quality is now BMC and extend its functionality in Fig. 5 shows a fragment of MBP (Fig. 11-14), the same as that shown in Fig. 3, but with deformed elements 26, 27, 28, 29, whatever they were supposed to be, if BMC design on a rectangular grid. The elements are deformed so that their contact window located at the nodes although uneven, but a rectangular grid of straight lines 25. For comparison next repeated the pattern of the original fragment of Fig. 3. The gain in area occupied by the elements in the original BMC case (Fig. 3), even when an uneven grid 25 is compared with the deformed fragment of Fig. 5 to 25% . If to prevent further deformation of the considered fragment, so that the grid was uniform, as is done for BMC-prototype (at the same time as the grid step you must take the greatest step non-uniform grid 25), the gain in area would increase by up to 50-80% . Thus, if the location of the contact Windows of the elements of the BMC on the nodes of a uniform rectangular grid increase the linear dimensions of these elements, they occupy the area of the crystal, grow their parasitic capacitance, etc. , i.e. worsen without having electrical characteristics of the elements of the BMC. In the numerical expression for BMC Fig. 6-10 and Fig. 11-14 this viagrastarter has an area of 2,3x3,0 mm2contains 24 pads, 4 types of cells, 272 diffusion resistor with a total resistivity 514 ohms, capacitor 4, 100 n-p-n and 40 p-n-p transistors 5 types, including 8 n-p-n transistors high power, and the total number of items BMC (without podnyav") 440. The density of the composition BMC is 65 elements per square millimeter square. Thus, BMC Fig. 6-10 exceeds BMC-the prototype of a number of types of cells and transistors into 3 types, contains 66 items more is 33% smaller area, and the density of the layout exceeds the prototype is almost two times. BMC Fig. 11-14 for the design of IP radio electronic equipment has an area of 2.3 x 3.0 mm2contains 24 pads, 8 types of cells 410 diffusion resistors with a total resistivity of 1.8 MW, 8 capacitors, 138 n-p-n and 84 p-n-p transistor 6 types, including 24 n-p-n and 16 p-n-p transistors high power and 4 power n-p-n transistor, and the total number of items BMC (without podnyav") is 664. The density of the composition BMC is 96 elements per square millimeter square. Thus, BMC Fig. 11-14 exceeds BMC prototype by the number of types of cells and transistors 10 types, contains 290 items more is on isawanya a new way and new BMC distinguishes them from the prototype, because it allows to increase the percentage of yield IC, lower their costs, increase 2-3 times the density of the layout elements of the BMC, to optimize their required parameters and at the same time to ensure conflict-free trace interconnects, primenenii automated tracing methods and to extend the functionality of BMC.

1. The way of converting the information in the design and trace the basic matrix crystals for analog and analog-digital integrated circuits (IC) with a single-level tracing lines in-circuit connections, including the placing of base cells in the field of basic matrix crystal for tracing lines in-circuit connections within and between them, the creation of a regular grid matrix, accommodation zones to trace in-circuit connections, resistors and diffusion jumper contacts to them and the location of the contacts to the active regions of the cell elements of the base matrix crystal in the grid with the ability to conduct between the grid lines integer trails connecting metallization given width at a fixed width of the gap between them, characterized in that before the creation of the PE the implementation on the minimum allowable technological distance or spend a couple of lines of tracks metallization violates the regulations on the gap between them, and regular matrix form by increasing the size of the random matrix by straightening all valid lines trace and establish between them the same distance, while the nodes of regular and irregular matrices correspond to each other, is performed at regular matrix, the nodes are connected according to the implemented circuit, and then transform the coordinates of the lines trace with a regular matrix on an irregular matrix.

2. Basic matrix crystal with single trace line circuit connections for analog IC containing the substrate, the region of n-type for placement metallized pads for pins with crystal, spaced evenly around the periphery of the crystal and isolated from each other back-biased p - n junction, the elements increased geometrical dimensions, located between the pads, the repeating cell of the same type, located symmetrically with respect to the horizontal and vertical axes of the crystal, resistors, capacitors, n - p - n and p - n - p transistors made with several contacts for switching, and the passive zone of the p-type strip of metallized tracks of messoudi the contact pads of the crystal have been added to the second cell, the third and fourth types, the first three types of cells are located symmetrically relative to the Central horizontal and vertical axes of the crystal successively along the horizontal axis, cell of the fourth type are located around the cells of the second type, separating the cells from one another, and contact pads along the edge of the crystal uniformly placed elongated contacts to the substrate and epitaxial pinch resistors are n-type.

3. The crystal under item 2, characterized in that the cell of the first type is made of five pairs of coordinated n - p - n transistors of the first type and one of a pair of matched p - n - p transistors of the first type along the vertical axis of the crystal, and a pair of p - n - p transistor is located closer to the center of the crystal, the cell of the second type is made of three pairs of coordinated n - p - n transistors of the first type and two pairs of coordinated p - n - p transistors of the first type, spaced from the periphery to the center of the crystal along the vertical axis successively two pairs of n - p - n; a pair of p - n - p pair n - p - n and a pair of p - n - p transistors, the cell of the third type is made of three p - n - p transistors of the first type, two diodes, two diffusion jumpers and four n - p - n transistors of the first the and of the diffusion resistors are p-type in a range of denominations, United in one resistive pocket of the n-type contact to the pocket along the edges of the cell and two n - p - n transistors of the first type, the collector region which is structurally integrated with resistive pocket, while between the contact sites of the crystal through each site, starting from the corner of the site along the short sides of the crystal are sequentially p - n - p transistors high power of the second type, Mont capacitors, and along the long sides of the crystal are arranged successively one by one through the space of n - p - n transistors high power of the second type and a region of n-type with different diffusion resistors are p-type and contacts to this area.

4. Basic matrix crystal with single trace line circuit connections for analog and analog-digital ICS containing substrate, the region of n-type for placement metallized pads for pins with crystal, spaced evenly around the periphery of the crystal and isolated from each other back-biased p - n junction, the elements of the BMC increased geometrical dimensions, located between the pads, the repeating cell of the same type, placed symmetrically otnoshenie with several contacts for switching, and the passive zone of the p-type strip of metallized tracks interconnects located between the cells and the periphery of the crystal, characterized in that the internal contact pads region of the crystal is additionally entered the cell of the second, third, fourth, fifth, sixth, seventh and eighth types, and in one of its parts is the first rectangular area containing four identical cells of the first type, the mutual position which is symmetrical about the horizontal and vertical axes of the first rectangular region, moreover, the cells of the first type along the horizontal axis in pairs separated by two symmetrical relative to the vertical axis of the first rectangular region of cells of the second type, the two lower and two upper cells of the first type are four pairs symmetric with respect to the horizontal and vertical axes of the first rectangular region of cells of the third type, and the left and right outer sides of the area occupied by the cells of the first type, there are four pairs symmetric with respect to the horizontal and vertical axes of the first rectangular region of the fourth cell type, and each pair of upper and Nigeria rectangular area, containing four identical cells of the sixth type, the mutual position which is symmetrical about the horizontal and vertical axes of the second rectangular region, and the upper and lower pairs of cells of the sixth type are separated by a cell of the seventh type, elongated along the horizontal axis, and above the upper and below the lower pairs of cells of the sixth type are located along the horizontal axis in the same cell of the seventh and two cells of the eighth type, symmetrical about horizontal and vertical axes of the second rectangular region, and the first and second rectangular region is separated from the peripheral region of the crystal with the pads of the passive area of the p-type conducting tracks connecting metallization, which are regularly diffusion of the bridge, and along the edge of the crystal for the pads evenly placed elongated contacts to the substrate and pinch resistors are n-type.

5. Crystal on p. 4, characterized in that the cell of the first type consists of two identical, symmetrical about the horizontal axis of the cell subfragments containing each U-shaped area occupied by a chain of six n - p - n transistors of the first type, the internal chorizontal axis between subfragments cell is a resistive pocket of n-type with four diffusion resistors of equal value p-type and contact him in the heart, and two pairs of diffusion bridges along the edges of the pocket, a cell of the second type contains along the horizontal axis of the three differential pair of n - p - n transistors of the first type, two capacitor on a p - n junction and one of the diffusion resistor p-type large value in the form of a meander, the cell of the third type comprises a pair of n - p - n transistors of the first type, three p - n - p transistor of the first type and the diffusion jumper, located in a row along the horizontal axis, the cell of the fourth type consists of two pairs of p - n - p transistors of the first type and a diffusion resistor p-type large value in the form of a meander along the vertical axis of the cell, the cell of the fifth type contains two capacitor on a p - n junction, a set of diffusion resistors p-type different denominations United in two resistive pocket of n-type contacts to the pockets and four diffusion jumper, the sixth cell type contains two diffusion jumpers resistive pocket in the form of a U-shaped isolated region of n-type resistors p-type different part types and contacts to it, in which in the area of bends symmetrically about the horizontal axis, there are two n - p - n transistor of the second type, the reservoirs to the mi has two pairs of n - p - n transistors high power of the third type, and above and below these pairs of transistors directly near the ends of the isolated pockets with resistors symmetrically about the horizontal axis of the cell placed one p - n - p transistor of the first type, and on the other side of the resistive pocket is a differential pair of such transistors, the cell of the seventh type contains symmetrically arranged in a row along the horizontal axis, two pairs of n - p - n transistors of the first type and three pairs of n - p - n transistors of the second type, cell eighth type contains arranged in a row along the horizontal axis resistive pocket of the n-type diffusion resistors p-type two part types, a couple agreed p - n - p transistors of the first type and the diffusion jumper between pads of the crystal through each site, starting from the corner of the platform along one short side of the crystal, are consistently of a pair of matched p - n - p transistors high power of the second type, and along the other short side of the crystal are a pair of matched n - p - n transistors high power of the third type, while along the long sides of the crystal between the crust p - n - p transistors high power of the second type and a pair consisting of an n - p - n transistor of the third type and p - n - p transistor of the second type.

 

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The invention relates to computing and integrated electronics, and more specifically to integrated logic elements ENCORE

FIELD: computer engineering and integrated electronics; integrated logic gates of very large-scale integrated circuits.

SUBSTANCE: newly introduced in integrated logic gate that has semi-insulating GaAs substrate, first input metal bus, first AlGaAs region of second polarity of conductivity disposed under the latter to form common Schottky barrier junction, first inherent-conductivity AlGaAs spacer region disposed under the latter, first GaAs region of inherent-conductivity channel disposed under the latter, second AlGaAs region of second polarity of conductivity, second AlGaAs spacer region of inherent conductivity, second input metal bus, output region of second polarity of conductivity, output metal bus, power metal bus, zero-potential metal bus, and isolating dielectric regions are inherent-conductivity AlGaAs tunnel-barrier region, InGaAs region of inherent-conductivity channel, AlGaAs region of second inherent-conductivity barrier, L-section power region of second polarity of conductivity, and Г-section zero-potential region of second polarity of conductivity; first GaAs region of inherent-conductivity channel and InGaAs region of inherent-conductivity channel are disposed in relatively vertical position and separated by AlGaAs region of inherent-conductivity tunnel barrier; output region of second polarity of conductivity is ┘-shaped and ┘-section region.

EFFECT: enhanced efficiency of using chip area, enhanced speed and reduced power requirement for integrated logic gate switching.

1 cl, 3 dwg

FIELD: computer science and integral electronics, in particular - engineering of VLSI integral logical elements.

SUBSTANCE: integral logical element contains semi-insulated GaAs substrate, first input metallic bus, first AlGaAs area of second conductivity type, positioned above aforementioned bus and forming Schottky transition together with it, below it first AlGaAs area of native conductivity spacer is positioned, below it, first GaAs area of native conductivity channel is positioned, second AlGaAs area of second conductivity type, second AlGaAs area of native conductivity spacer, second input metallic bus, output area of second conductivity type, output metallic bus, zero potential metallic bus, metallic power bus, areas of separating dielectric. Integral logical element additionally contains AlGaAs area of native conductivity tunnel barrier, InGaAs area of native conductivity channel, AlGaAs area of second conductivity barrier, zero potential area of second conductivity type with transverse cross-section in form of symbol L, while first GaAs area of native conductivity channel and InGaAs area of native conductivity channel have vertical mutual position and are divided by AlGaAs area of native conductivity tunnel barrier, output area of second conductivity type is L-shaped and has L-shaped cross-section.

EFFECT: decreased efficiency of crystal area usage, increased speed of operation and decreased energy consumed by switching integral logical element.

3 dwg

FIELD: power semiconductor microelectronics.

SUBSTANCE: newly introduced in central part of semiconductor structure that has substrate, semiconductor material with depleted area in its central part enclosed by depleted area in peripheral part of structure, and relevant current-conducting contacts are recessed components of reverse polarity of conductivity with spherical depleted area whose electric field strength is higher than that of depleted areas in gap between recessed components and in peripheral part of structure.

EFFECT: improved power characteristics, enhanced resistance to pulse overcurrents.

7 cl, 1 dwg

FIELD: physics.

SUBSTANCE: invention relates to design and technology of manufacturing semiconductor integrated circuits (IC) and can be used in digital, analogue and memory units in microelectronics. The semiconductor IC has a high-resistance monocrystalline silicon layer grown in form of a hollow cylinder in which there are regions with different conduction type, which form bipolar transistors, resistors and capacitors. On the outer surface of the high-resistance monocrystalline silicon layer there are emitter and base contacts adjacent to corresponding regions of corresponding transistors connected to resistors and capacitors by conductive paths formed on the surface of a dielectric placed on the outer surface of the high-resistance monocrystalline silicon layer, and on the inner surface of the high-resistance monocrystalline silicon layer there is a collector contact in form of a hollow cylinder adjacent to the collector regions of the transistors or the adjacent silicon layer.

EFFECT: higher degree of integration of the IC, reduced feature size of the element, lower level of inter-electrode connections, reduction of power consumption by one switching, increased reliability.

3 cl, 1 dwg

FIELD: electricity.

SUBSTANCE: semiconductor structure of the logical element AND-NOT comprising the first and second logical transistors, the first and second injecting transistors and a substrate is made as nanosized with a stepped profile and comprises four collectors, four bases and at least four emitters on the substrate of the first type of conductivity.

EFFECT: reduced consumed power and increased efficiency.

13 dwg

FIELD: electricity.

SUBSTANCE: in the integral logical AND-NOT element based on a layered three dimensional nanostructure (the element containing the first and the second logical transistors, the first and the second injecting transistors and a substrate) the logical structure is designed to be nanosized with a stepped profile.

EFFECT: increased response speed and reduced power consumption.

18 dwg

FIELD: electricity.

SUBSTANCE: multifunctional microwave monolithic integrated circuit board based on a multilayer semiconductor structure combines functions of several monolithic integrated circuit boards and comprises field-effect Schottky transistors and quasivertical Schottky barrier diodes with high values of boundary frequencies, which are integrated at the same chip and used as active and non-linear elements. Active areas of the field-effect transistors and basic areas of the quasivertical diodes are placed in different epitaxial layers with a low-ohmic contact layer placed between them and ohmic source and drain contacts of the transistors and ohmic cathodic contacts of the diodes are attached to it.

EFFECT: increased degree of integration for the microwave multifunctional integrated circuit board, reduced weight and dimensions for receiving and transmitting modules of antenna arrays, reduced losses related to signals passage between the schemes of functional units, increased boundary frequencies for the Schottky barrier diodes.

1 dwg

FIELD: electricity.

SUBSTANCE: in a semiconductor device a diode area and IGBT area are formed at the same semiconductor substrate. The diode area includes a multitude of anode layers with the first type of conductivity open at the surface of the semiconductor substrate and separated from each other. The IGBT area includes a multitude of contact layers of the body with the first type of conductivity open at the surface of the semiconductor substrate and separated from each other. An anode layer includes at least one or more first anode layers. The first anode layer is formed close to the IGBT area at least, and the square area in each of the first anode layers in the direction of the semiconductor substrate plane is more than the square area in each contact layer of the body in direct vicinity from the diode area in the direction of the semiconductor substrate plane.

EFFECT: invention prevents direct voltage growth in the diode area and increased heat losses.

2 cl, 5 dwg

FIELD: process engineering.

SUBSTANCE: invention relates to microelectronics, particularly, to production of solid-state devices by evaporation of metal coating on the substrate back surface. Claimed process consists in that the substrate is flexed in reverse direction before evaporation of metal coating. It differs from known processes in that said coating is evaporated on substrate back surface through stencil with through holes shaped and sized to crystals. Jumpers between said holes in stencil are comparable with the width of division webs made between crystals on substrate face surface.

EFFECT: reduced residual thermomechanical strains at said boundary.

5 dwg

FIELD: manufacturing technology.

SUBSTANCE: invention relates to production of integrated microcircuits in part of interposer forming for 3D assembly of several chips in single micro-system and process of its production. Invention is aimed at reducing effect of temperature gradients and associated mechanical stresses arising in body of interposer during operation of integrated microelectronic system. For this purpose, in body of interposer around through holes (TSV) filled with conducting material to create electric connection of metallized electric wiring working side with metallized layout of interposer reverse side formed holes, one of topological dimensions considerably smaller than minimum feature size TSV.

EFFECT: formed holes for reducing effect of temperature gradients are filled with material with heat conductivity higher than that of silicon, for compensation of mechanical stresses are not filled or are filled partially with formation of cavities inside hole.

18 cl, 11 dwg

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