Device for visual inspection of the execution of programs

 

(57) Abstract:

The device relates to computing and can be used to control the execution of programs of microcomputers, controllers, personal computers and mainframe computers. The purpose of the invention consists in extending the functionality of: increasing the information content, accuracy, control, reduce the labor cost control. For this purpose, the device comprises a block 1 current address registers and data block 2 set modes, block 3 multiplexers, unit 4 registers the start address, block 5 comparison unit 6 RAM block 7 choice of rooms and has a group of inputs, States and synchronization, the address input and data input, which are the inputs of the device for connection respectively to the output of the synchronization state, the output address and data of the controlled device, the first clock input of the block RAM, the group of inputs of the mode control block registers current address and data the group of inputs of the mode control block registers start address, which are the control inputs of the device for connection to respective outputs of the control mode of the microcomputer. 9 Il.

The device relates to computing those who Lehr, Computers, microcomputers, mainframe computers, and so on ).

The aim of the invention is the extension of functionality (raising awareness, precision control, reducing the time spent on the control device for visual inspection by ensuring the registration of inspection results in the form of a data array, due to the compliance of the registered address and data pragmata program for a period of time of operation of the controlled device relative to the repetitive address selected by the operator.

In Fig. 1 shows a block diagram of the device for visual inspection of the execution of the program of Fig. 2 is a block circuit current address registers and data; Fig. 3 is a block circuit set modes; Fig. 4 is a block circuit diagram of the multiplexer of Fig. 5 is a block circuit registers start address; Fig. 6 is a block circuit diagram of the comparison; Fig. 7 is a diagram of the memory block of Fig. 8 is a block circuit diagram of a choice of rooms; Fig. 9 algorithm collaboration device with the computer and controlled by the device.

Device for visual inspection of the execution of the program (Fig. 1) block contains 1 register current address and data block 2 set modes, block 3 more, a group of 8 inputs synchronization and conditions address input 9 input 10 data, which are input devices to connect to the group of outputs synchronization and state, the output address and data of the controlled device (system controller, computers, computer and so on ), the output 11 of block 2, which is connected with the first group of control inputs of unit 3 multiplexers, a group of information outputs 12 unit 4 registers the start address, which is connected to the first group of information inputs of the block 5 comparison of the first and second group of input-output block 6 RAM which is the input address and the device data and the output data of the block 6, and the first group of outputs-inputs connected to the first group of information inputs of block 1 current address registers and data and to the second group of information inputs of block 5 of the comparison, and the second group to the second group of information inputs of block 1 current address registers and data, a group of control inputs of the modes of block 1 current address registers and data group input mode control unit 4 registers the start address, the first clock input unit 6 RAM, which are the control inputs 13-20 devices connected and data which is the output 21 sign of activity information of the device to connect to the input of the confirmation of the availability of microcomputers, exit 22 initial installation of the unit 2 set modes, which is connected to the reset inputs of block 1 current address registers and data unit 4 registers starting address to the first input of the mode control unit 5 comparison of block 6 of the RAM and the block 7 to select a number, the second control input mode which is the first output 23 of the equality of operands block 5 comparison the first output 24 of the block 6 RAM is the output of the sign of the buffer for connection to the information input unit 1 current address registers and data, the second output unit 5 of the comparison is output 25 for connection to the clock output unit 7 selecting a second clock input unit 6 RAM connected to the output of gate 26 States unit 3 multiplexers, the input and the second group of inputs which are a group of 8 inputs and synchronization States of the device to connect to the outputs of the synchronization state of the device, the second output 27 unit 6 RAM is the output of the sign of the buffer for connection to the second control input mode is a, the output 29 which is connected to the second input of the mode control unit 6 RAM.

Unit 1 current address registers and data (Fig. 2) contains the registers 30 shift.

Unit 2 set modes (Fig. 3) contains the unit 31 registers, RS-flip-flop 32, the And gate 33, a switch 34, a push-button switch 35, a capacitor 36.

Unit 3 multiplexers (Fig. 4) contains elements And 37, the elements OR 38, the And gate 39.

Unit 4 registers the start address (Fig. 5) contains registers 40 offset, tire shaper 41, item, OR 42.

Unit 5 comparison (Fig. 6) contains the schema 43 comparison, the And gate 44, the RS-flip-flop 45, the one-shot 46.

Unit 6 RAM (Fig. 7) contains an element of the RAM 47, the counter 48, item, OR 49, the elements 50, the element OR NOT 51, IK-trigger 52.

Unit 7 number selection (Fig. 8) contains a block of counters 53 and 54 of the switch block 55, block resistors 56, LEDs 57, IK-trigger 58, the element 2I 59.

Unit 1 current address registers and the data is intended for temporary storage in the register 30 of the current addresses and data from block 6 RAM through the first and second groups of outputs-inputs to the first and second group of information inputs of the unit 1 C is ez the first and second groups of outputs-inputs to the first group of information input unit 1 for storing the signal Buffer is filled through the outlet 24 of the block 6 to the information input unit 1, and also for the formation of a confirmation signal to the microcomputer, which is fed to the input 21 sign of activity information of block 1 from the output of the register 30 in accordance with the algorithm (Fig. 9). The bit width of the register 30 is determined by the bit width of the address bus and data bus controlled devices that are connected to the address input 9 input 10 data device.

Unit 2 set modes is used to select States of the controlled device selection command from the ROM, the address to the ROM, RAM, accessing external devices through switches 34, as well as for generating the reset signal, which is received from the push-button switch 35 through the RS-flip-flop 32, and signal initial setup of the RC chain block 31 of the resistors and capacitor 36 and to the output 22 of the reset (initial setup power), which leads to the initial state of the device.

Unit 3 multiplexers is designed to generate pulses at points in time determined by the position of switches 34 unit 2 set modes.

Unit 4 registers the start address is for memorizing the address that defines the beginning of a piece of software required to view the program operator. Address snowline from the microcomputer, received at the inputs 16, 17, 18, 19 of the control device in accordance with the algorithm (Fig. 9). The bit width of the register 40 is determined by the bit address buses controlled devices that are connected to the address input 9 of the device.

Unit 5 comparison is to compare the current address of the controlled device, which is supplied to the second group of information inputs of A circuit 43 comparison through the address input device, and the specified address, which is supplied to the first group of information inputs B of scheme 43 comparison with information output 12 unit 4 registers the start address. When comparing addresses scheme 43 comparison generates a pulse to the input of an RS flip-flop 45, the output of which is transmitted to the output 23 of the equality of operands block 5 comparison in block 7 number selection, which allows the passage of clock signals output from gate 26 States unit 3 multiplexers at some point.

Unit 6 memory is for memorizing the code that runs in a controlled device in real time, i.e., current information coming from the controlled device via the address input 9 input 10 of donnchada gate 26 States unit 3 multiplexers and output 29 resolution recording unit 7 select through the elements And 50.2 and OR NOT 51 and the clock input of counter 48 for reading the recorded current information, the incoming unit 6 memory through the input / output of RAM and 47.1 47. m on the first and second group of information inputs of block 1 current address registers and data points defined by the control signal from the microcomputer, in accordance with the algorithm (Fig. 9) via the control input 20 of the device, namely through the elements AND 50.2, OR NOT 51 on the clock input of counter 48 and through the cells AND 50.2, OR NOT 51 OR 49 to the input of the write-enable and read-only memory and 47.1 47. m, and for signal "Buffer full" from the output of the transfer counter 48 through IK-trigger 52 is supplied to the first output characteristic of the buffer unit 6 RAM for signal "Ban", coming from the output of the transfer counter 48 through the element And 50.1 per second output 27 of block 6 of RAM. Bit of RAM and 47.1 47. m is determined by the bit width of the address bus and data bus controlled devices that are connected to the address input 9 input 10 data device.

Information capacity of RAM and 47.1 47. m is determined by the maximum amount of memory required to fill the desired code.

Unit 1 current address registers and data the sa is an eight-bit shift registers of the type CAR and the eight-bit bus shapers type VA.

As circuit 43 comparison unit 5 comparison can be used schema comparison type SP.

RAM and 47.1 47. m block 6 RAM is a RAM statistical type capacity (for example, C) BUS, and as a counter 48 may be used chip type II (four-bit asynchronous counter).

As the circuit 46 can be used one-shot IS.

In block 7 number selection can be applied indicators 57 type SLSS.

The device is intended for visual inspection of the performance of the controlled devices based on microprocessors CMA, KRUM, KRUM, and controlled devices built on the basis of the microprocessor sets 1802, 1804, 589 (see the Reference. Digital and analog integrated circuits. / Ed. by S. C. Jakubowski. : Radio and communications, 1990, sections 3.2, 3.6, 3.7, 3.8).

The device operates as follows.

To bring the device visual inspection of the execution of the programs in the initial state to the reset input of block 1 current address registers and data unit 4 registers the start address, block 6 of RAM, at first I the 22 initial installation of the unit 2 set modes, which is formed after the power output from the RC-chain 31, 36, or by pressing the operator button switch 35.

As a result, the registers 30 and 40 sdwiki blocks 1 and 4 current address registers and data registers start address set in the initial state, the output IK-flip-flop 58 unit 7 number selection signal is formed prohibition of the resulting quantum state sequences, which enters through the outlet 29 of the equality of operands to the first input element And 50.2 unit 6 RAM output IK-flip-flop 52 which is formed by the signal recording resolution, which bundle OR 49 with the output signal of the element OR NOT 51 is fed to the input of the write-enable RAM 47, on the inverse output IK-trigger block 52, a signal is generated to the lack of "buffer", which is supplied to the first output 24 sign of the buffer unit 6 memory, the outputs of the counter 48 unit you receive the initial address code memory 47, which is formed by the signal initial setup, input resolution parallel load counter with the output element And 50.1.

The device operates in two modes: the first device in real time through the address input 9 input 10 data device; in the reading mode information of the block 6 RAM in the microcomputer from the information output unit 1 current address registers and data through the output 21 confirm the presence of the signal device.

The first and second modes perform together. The separation of these modes in time is solved by the hardware device and the control signals, outputs of the microcomputer to control inputs 13-20.

Management units 1, 4, 6 current address registers and data registers start address and memory is provided from the control output of the microcomputer, which is connected to the control inputs 13-20 device in accordance with the algorithm shown in Fig. 9.

The starting address of arbitrary code is sent sequentially on the information input for left shift register 40 of the shift unit 4 registers the start address through the control input 19 of the device accompanied by control signals received at a clock input, first and second inputs of the mode selection register 40 via control inputs 16, 17, 18 of the device in accordance with Fig. 9a. The starting address is stored in register 40 shift and transmitted when the mode of storing the water which receives signals permissions control inputs 17, 18 of the device. The start address output 12 unit 4 registers the start address is supplied to the first group of information inputs of block 5 of the comparison, a second group of information inputs of which is transferred to the current address with the address outputs of the controlled device via the address input 9 of the device. When comparing the codes of the addresses present on the first and second information input circuit 43 comparison, at its output, a signal is generated which is fed to the input of the RS flip-flop 45 and an inverse input of one-shot 46, producing a pulse at the address of a certain duration. Output RS-flip-flop 45 through the output 23 of the equality of operands and output the one-shot 46 through the outlet 25 signals are respectively input to the load and the clock input of the counter 54 and translate it into a state of counting n-iterative addresses, the number of repetitions which is pre-selected by the operator push-button switches 55 loaded in the return code in the counter 54 through the meter 53 and displayed on the indicators 57 through resistor Assembly 56. When calculating the n addresses at the output of the transfer counter 54 is formed in the transfer characteristic, which through the element And 50.2 arrives at the clock input IK-flip-flop 58. With the release of the latest formeset pass signals resulting quantum state sequences. This sequence comes from the output 26 of block 3 of multiplexers, the second group of inputs, States, and the gate of which the signals from the output state and output synchronization of the controlled device through a group of 8 inputs.

The state of the processor controlled device varies with each of its internal clock. Therefore, the second group of inputs of the conditions of block 3 of the multiplexer is formed by a sequence of pulses corresponding to certain aspects of the controlled device (the address for the first byte, i.e., a command from the ROM, the address to the RAM addressing RAM, accessing external devices and so on ). All generated sequences of States are received at the inputs of the elements 37.1 . . . 37. n block 3 multiplexer, but their outputs are only those that are selected by the operator by means of switches 34.1 . . . 34n block 2 set modes. After convolution OR 38.1 . . . 38n with the synchronization signal received at the input elements OR 38.1 . . . 38n from the monitored device, and then their convolution And 39, the resulting clock sequence is output 26 unit 3 multiplexers.

Address and given the 10 data devices on the first and second groups of input-output block 6 RAM.

Address and data are written into memory and 47.1 47. m the resulting clock sequence of status signals from the output of gate 26 States, which is supplied to the second input element And 50.2. The output element And 50.2 connected to the first input of the element OR NOT 51, the output of which the signal flows through the element OR 49 to the input recording resolution in the RAM 47 and at the same time this signal is applied to the clock input of counter 48, the positive difference which selects the next address of the RAM 47 unit 6 RAM. When the buffer RAM 47 information of the current program segment, the outputs of the transfer counter 48 through the element And 50.1 arrives at the clock input IK-flip-flop 52, with direct access through which the element OR 49 is formed by the enable signal read from the RAM 47 and the inverse output of which a signal is generated "Buffer full". The latter is fed through the exit 24 sign of the buffer unit 6 RAM on the information input unit 1 current address registers and data output 21 sign of activity information which the signal is transmitted to the input of the confirmation of the microcomputer in accordance with the algorithm niania information in the computer.

The outputs of the control of the microcomputer through the inputs 13, 14, 15 of the control device are transmitted control signals to the clock input of the mode selection register 30 of the shift block 1 current address registers and data and through input to the second input of the OR element 49, the output of which the signal arrives at the clock input of counter 48. Information is read from the first and second groups of outputs-inputs of block 6 of the RAM block 1 current address registers and data stored in the register 30 of the shift and is passed in series with its information output 21 to the input of the confirmation of microcomputers, where it is stored in a array A in accordance with the algorithm of Fig. 9b. With the control output of the microcomputer via the control input 20 of the device to the clock input unit 6 RAM signal, positive transfer of which from the output of the counter 48 selects the next address of the RAM 47, the first and second groups of outputs input unit 6 memory information is read out as described above in accordance with the algorithm of Fig. 9b.

Information listed in the array A of microcomputers can be considered from any address of the current fragment program in both forward and backward reference analnogo control program execution.

Technical appraisal and economic benefits of the proposed technical solution is to expand the functionality of the proposed device by ensuring the preservation of an arbitrary fragment of the program being examined, the possibility of multiple view the progress of the program and control any information (including address, data) is determined by the aggregate used in the device hardware and the new organization contacts.

The proposed solution provides cost reduction, real-time control performance of the controlled device, in particular for NMIS with integrated system controller. The effectiveness of the proposed technical solution is derived from the calculated data, confirming the reduction of costs of real time.

DEVICE FOR VISUAL inspection of the EXECUTION of PROGRAMS containing the power control unit registers the current address and the data block set modes, the block multiplexors, block registers start address, block compare, and group outputs block set modes connected with a group of control inputs of the block multipliers, group information output unit registers the initial hell is Eden block RAM the block selecting address, and the first and second groups of inputs-outputs of the block RAM are connected to the inputs respectively of the address and data devices to connect to the outputs of the address and data of the controlled device, and the first group of inputs-outputs of the block RAM connected to the first group of information inputs of the registers unit current address and data and to the second group of information inputs of the block comparison, the second group of inputs-outputs of the block RAM is connected with the second group of information inputs of the registers unit current address and data group input mode control which group of inputs of the mode control block registers start address, the first clock input of the block RAM connected to the corresponding outputs of the control unit, the information input unit registers the current address and the data is connected to the input of the characteristic activity information control unit, the output of the initial installation of the unit set modes connected to the reset inputs of the registers unit current address and data block registers start address to the first inputs of the mode control block compare block of memory, and a block selecting address in the buffer memory block is connected to the information input unit registers the current address and the data the second output unit of comparison is connected to the clock input of the block selecting address, the second clock input of the block RAM is connected to the output of multiplexers, the second group of inputs which is a group of inputs of the synchronization state of the device to connect to the outputs of the synchronization and state of the controlled device, the output characteristic of the prohibition of the memory block connected to the second input of the mode control unit comparing the third output of which is connected to the third input of the mode control block selecting address, the output of which is connected to the second input of the control mode of the memory block, and the block selecting address contains the first and second counters, the node switches site indicators, JK flip-flop element And the first input of which the input load of the second counter, the second input of the mode control block selecting address, the second input element And is connected to the output of the second transfer counter, the clock input of which is connected to the clock input of the block selecting address information input of a second counter connected to the outputs of the first counter and the input node of the indicators, the clock inputs of the first counter is connected to vichka select the address number the reset inputs of the first and second counter and the K-input of the JK-flip-flop is connected to the zero potential bus device, and the J input of the JK-flip-flop connected to the bus unit capacity of the device, the reset input of the JK-flip-flop is connected to the third input of the mode control block selecting address clock input of the JK-flip-flop coupled to the output element And the inverse output of the JK-flip-flop is the output of the block selecting address.

 

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