The decoding device


H03M13/02 -

 

(57) Abstract:

The device relates to communication technology and can be used in communication systems. The purpose of the invention is improving the performance of your device and expand its functionality. The device comprises a generator of code words, the output register block ban, algebraic adder, multi-line shift register, the register memory block comparison of the reliability control unit. 1 C. p. F.-ly, 4 Il.

The invention relates to communication technology, and in particular to devices for decoding information encoded block correction code, and can be used in communication systems with replay code words.

Closest to the present invention is a decoding device containing a multi-line shift register, adder, comparator reliability, memory register, circular case, the output register and the switch, and outputs high-order multi-register through the switch, other inputs which are input devices that are connected to its inputs and outputs bits are connected to the inputs of the adder, the outputs of which are connected with inputs of the device sravneniai - respectively to the inputs of the register memory, and with the control input of the output register information the input of which is connected to the outputs of the ring register, and the output is the output device.

The disadvantage of this device is the large decoding delay and impossibility of its use in communication systems with replay code words.

The issuance of the decoding in the described device may be made only after comparing the received code combinations with all possible code words, which leads to the decoding delay, increasing as the number of information bits of the code word. In addition, this device can not be directly used in systems with repetition code words. You can use this device for decoding each of the repeated code words separately with subsequent majoritarianism results of the decoding, but it will lead to decreased immunity due to incomplete use of the correcting ability of the code.

The aim of the invention is to improve performance, expand the functionality of the device.

In Fig.- diagram of the control unit; in Fig. 4 is a block circuit diagram of the comparison of reliability.

The decoding device (Fig. 1) comprises a generator of code words 1, the output register 2, block ban 3, the algebraic adder 4, the multi-channel shift register 5, the memory register 6, the block comparison of reliability 7 and the control unit 8.

The multichannel outputs of the shift register 5 is connected to the first input of the algebraic adder 4, the second inputs of which are connected to the outputs of block ban 3, the first inputs of which are the inputs of the device, and the second input is connected to the first generator output code words is 1, the second outputs of which are connected to the inputs of the output register 2, the outputs of which are output devices.

The outputs of the algebraic adder 4 is connected to the corresponding inputs of multi-channel shift register 5, the second input unit of the comparing reliability 7 and with the inputs of the memory register 6, the outputs of which are connected with the first inputs of the block comparison of reliability 7, the output of which is connected to the enable inputs write memory register 6 and the output register 2.

The clock generator output code words 1 is connected to a clock input of the control unit 8, the first and second installation and control outputs to the RA 2, installation multichannel input of the shift register 5 and the controlling unit comparing the reliability 7. Combined installation inputs generator code words 1 and the control unit 8, and an integrated clock inputs of the generator code words 1, multi-channel shift register 5 and the clock inputs of the output register 2 and register memory 6 are respectively mounting the input and reference input frequency devices.

Generator code words 1 contains (Fig. 2) the count of code words 9, the pulse shaper 10, the counter non discharge 11, the unit's permanent memory 12, the shift register 13 and the driver clock signal 14.

The output bits of the counter 9 are the second generator outputs code words 1 and is connected to the inputs of the driver 10, the output of which is connected to the enable input of the account of the counter non discharge 11 and entry permit entry of the shift register 13. The output bits of the counter non discharge connected to the inputs of the driver clock signal 14 and the address inputs of the unit's permanent memory 12, the outputs of which are connected with the inputs of the parallel recording of the shift register 13, the output of the high-order bit which is the first generator output code words 1. O are respectively the clock and installation inputs, and the shaper's output clock signal 14 is the clock generator output code words 1.

The control unit 8 includes (Fig. 3) count the number of repetitions of 15, the pulse shaper 16, the selector pulses 17 and shapers of the first 18 and second 19 installation of signals.

The output bits of the counter of the number of repetitions 15 is connected with the inputs of the driver 16, the output of which is connected to the first input of the selector pulses 17, the second input is combined with a clock input of a counter of the number of repetitions of 15 and is a clock input of the control unit 8, and the output connected to the inputs of the shapers of the first 18 and second 19 installation of signals and is a control output of the control unit 8. The installation log count of the number of repetitions of 15, the outputs of the shapers of the first 18 and second 19 installation of signals are respectively the installation log, the first and second installation outputs of the control unit 8.

The Comparer reliability 7 includes (Fig. 4) the comparator 20 and the element And 21, and first and second inputs of the comparator 20 are respectively first and second inputs of the comparator reliability 7, and the output connected with one input element And 21, the second input is assessable set of m input elements And, and one of the inputs of each element is an input device, and other inputs are combined and connected to the generator output code words 1. The value of m is determined by the width at the input of the decoding device information.

The algebraic adder 4 is a binary adder with cyclic transfer (exit to transfer the senior level is connected to the input of the transfer LSB). The number of bits of the adder 4 is l = m + N1M - 1, where N1- the maximum number of units in the code layer, M is the number of repetitions of the code word.

Registers 6 and 2 represent registers with parallel input and output and the number of digits, respectively, l and K, where K is the number of information bits of the code word.

Multichannel shift register 5 is a set of (l - 1) 2k- bit shift registers, inputs sequential write and outputs the senior level are respectively inputs and outputs, and the combined clock and set inputs, respectively clock and installation multichannel inputs of the shift register 5.

Bit counter 9 is equal To that of the counter code words 11 - log2N (x oznachaet irovel 14 represent combinational devices and are based on standard logic elements. The functions implemented by these devices, described below. The ROM 12 can't be of any type, not less than N x 2kdischarges. The bit width of the register 13 is equal to 2k. The selector pulses 17 and the element 21 is input elements And. the Formers 18 and 19 represent the highlighters respectively front and rear fronts.

The comparator 20 is a digital comparator of two l-bit binary numbers with a sign. To ensure comparability with the subject sign the sign bit of the incoming number is inverted.

The device operates as follows. Let the communication channel information is transmitted using correcting (N, K) code with M-fold repetition code words (the case M = 1 corresponds to the system without repeat). A demodulator (not shown) converts the incoming analog signal into a sequence of m-bit binary numbers, each of which indicates the reliability of the corresponding symbols of the received code word. This conversion may be performed, for example, by an analog-to-digital conversion samples of the signal at the output of the matched filter (see j. Clark, Jr. , J. Kane. Encoding with error correction in digital communication systems. - M , Radio and communications, 1987, S. 33-37). PR is (when passing zero). Negative number, it is convenient to write in the reverse code. The number of bits m is determined by the bit width used by the ADC. When using the demodulator threshold device (see L. M. Fink Theory of the transmission of discrete messages. - M. , 1970, S. 158) the number of bits of the input information m = 1, i.e. the input signal only the sign bit.

Calculated in the demodulator values of reliability of the received symbols in the parallel code are received at the inputs of the block ban 3. The passage of signals to the output unit of the ban 3 is permitted only when the signal Log. 1" is supplied to the second input of the block ban 3 with the generator output code words 1, otherwise outputs block ban 3 are formed from the signals of the Log. 0".

Algebraically, the adder 4 in conjunction with a multi-channel shift register 5 performs nakaplivalsya the algebraic summation of signals from the output of the block ban 3. At the beginning of each cycle of decoding multichannel register 5 is reset by a signal on its installation input from the control unit 8. After that, the input unit of the ban 3 receives signals corresponding to the reliability of the first character of the received code and the generator code words 1 posledovatelya. The value of reliability of the first character of the received code will be written in those cells multichannel shift register 5, which correspond to non-zero symbols at the output of the generator code words 1. Frequency change information on the generator outputs code words 1 must be in the 2ktimes the frequency of receipt of the information input device.

In the next cycle to the input unit of the ban 3 receives the value of the reliability of the second received symbol generator code words 1 generates a sequence of signals corresponding to the second bits of all 2kcode words, the value of reliability algebraically summed with the contents of the cells multichannel register 5, the corresponding non-zero symbols at the output of the generator code words 1 and so on Described process is repeated N x M times. As a result, in each of the 2kcells multichannel register 5 is formed by a number representing the algebraic sum of the reliability of the symbols of the received code combination corresponding to the nonzero symbols corresponding to the cell code words. These numbers represent the likelihood function of a given code word for a given analog signal, the pic is of code words, having the greatest likelihood function. Work unit comparing the reliability 7 is permitted only on the last of the N x M cycles of operation of the device. All other time is prohibited by the signal coming from the control output of the control unit 8. At the output of the Comparer reliability is the potential of prohibiting the recording of information in the registers 2 and 6. On the last step of the cycle, the unit performs algebraic comparison of the numbers received at its inputs, and if the value of the likelihood function generated at the output of the adder 4, exceeds the value of the contents of the memory register 6, the output of the Comparer reliability 7, a signal is generated that enables the writing of a new value of the likelihood function in the memory register 6 and the information bits of the corresponding code word in the output register 2.

At the beginning of the process of comparing the signal with the first installation of the output control unit 8, the memory register 6 is set in the status, obviously less (including sign) than the minimum possible value of the likelihood function. Most simply this can be done by setting register 6 in the state corresponding to the maximum absolute value Autry is secure from the output of the adder 4 is guaranteed to be written to the register 6 and is used for further comparison.

Thus, by the end of the cycle decoding in the output register 2 are recorded the information bits to the most probable code word, and in the memory register 6 - its likelihood function. Then on a signal from the second installation of the output control unit 8 resets the contents of the multi-channel shift register 5 and the described process is repeated. Obtained at each cycle the contents of the output register 2 and register memory 6 stores within (NM - 1) cycles of the next cycle and can be used by external devices (such as serial and parallel).

If the set of code words used code includes a code word consisting of all zeros, this word can be excluded from the search because its likelihood function is known in advance (and equal to 0). The ratio of the frequency generator code words 1 and the clock frequency can be reduced to (2k- 1), and setting registers 2 and 6 must be in the zero state. If the likelihood function of all non-zero code words is less than 0 (i.e., the most plausible is the zero codeword), then registers 2 and 6 at the end of the comparison process of the of egovernance, applicants to the block ban 3. (I x j)-th also decode the code word, where i = 1, 2, . . . , N, j = 1, . . . M, the code generator generates a sequence of words consisting of the i-th bits of all 2kpossible code words (or 2k- 1 code words, if the analysis of the zero code word is not performed).

Generator code words 1 works as follows (see Fig. 2). The counter 9 performs the division arriving at its clock input the reference frequency on the 2kor 2k- 1 depending on the number of analyzed code words. At the output of the shaper 10 is formed a pulse duration of 1 period of the reference frequency with a period equal to 2kor 2k- 1.

This pulse is parallel to the recording information generated at the outputs of the ROM 12 in the shift register 13, and then the contents of the counter non discharge 11 is incremented by 1 and outputs the ROM 12 is a new information.

Upon termination of the pulse coming from the output of the analyzer 10, the information in the shift register 13 begins to move on the reference frequency at the output of high-order bit of the shift register 13 are sequentially formed signals corresponding information, the new words 1, to the ROM 12 at the address I, where I = 0 . . . N - 1 were recorded bits i = I + 1 for all 2kor 2k- 1 code words to be analyzed. Thus, the capacity of the ROM 12 and the shift register 13 must be equal to 2kor 2k- 1. The multiplier counter non discharge 11 is equal to n

Driver clock signal 14 is designed to highlight the end of processing the code word and is a combinational device that generates a pulse signal at the counter 11 state N - 1.

The initial phase of the counters 9 and 11 is effected by a signal on their installation inputs of the device frame synchronization. Shaper 10 is a combinational device that generates a pulse signal when the zero state of the counter 9, so after the initial setup is recording information about the first digits of all code words in the register 13. Thereafter the above process can be performed without additional phasing.

The control unit 8 operates as follows (see Fig. 3). To the clock input of the counter of the number of repetitions 15 receives pulses from the clock generator output s 17 missing). When the counter reaches 15 state M - 1 at the output of driver 16, a signal is generated that allows the passage of the pulse through the selector 17. Thus, at the output of the selector pulse 17 is formed by a sequence of pulses with duration 2k of periods of the reference frequency at the input of the decoding device (which is 1 cycle frequency, which receives input information), and with a period of N M clock cycles clock frequency. During the duration of this pulse may be permitted Comparer reliability 7.

Before starting the comparison process at the output of the shaper first distribution signal 18 is generated pulse, setting the initial state of the registers 2 and 6, and after his graduation at the output of the shaper 19 is formed impulse Abdoulaye multichannel content of the shift register 5. The formers 18 and 19 represent the highlighters respectively front and rear edges of the pulses at the output of the selector 17.

The Comparer reliability 7 operates as follows (Fig. 4). The comparator 20 performs algebraic comparison of two binary numbers present at its inputs. If the number received at the second inputs of the adder 4 is greater than the number that comes the od element And 21 in the presence of the signal Log. 1" at the control input of the block comparison of reliability 7. In the presence of the control input signal Log. 0" at the output of the element 21 is the signal Log. 0" and the comparator reliability is prohibited.

The advantage of the proposed device is the lack of decoding delay and possible use in systems with repetition code words.

Unlike device-prototype comparison of likelihood functions and the choice of the most reliable code word occurs within one (last) beat receipt of the input information. At the end of the reception received from the channel code combinations the result of decoding is already present at the output of the device.

The ability to use the system with replay code words is determined by accumulating the sum of the comparison results with all possible code words, which may be conducted during any time. Moreover, the complexity of the described device is only slightly changed with increasing number of repetitions of the code word. The number of repetitions can easily be made manageable, which increases the versatility of the device. (56) Copyright sweetimsetup codes. Technology communications, vol. TRS, 1982, vol. 8, S. 79.

The UK patent N 1400649, CL H 04 M 1/10, 1973.

1. The DECODING DEVICE containing the block comparison of reliability, the memory register, the output register and the control unit, the outputs of the memory register connected to the first inputs of the block comparison of reliability, the output of which is connected to the enable inputs write memory register and the output register whose outputs are the outputs of the device, characterized in that, to improve performance and extend the functionality of the device due to the possibility of use in systems with repetition code words, it introduced the generator code words, the unit of the ban, the algebraic adder and a multi-line shift register, the outputs of which are connected with the first input of the algebraic adder, the second inputs of which are connected to the outputs of the block of the ban, the first inputs of which are information input device, the first and second generator outputs code words respectively connected with a second input unit of the ban and the information inputs of the output register, the outputs of the algebraic adder connected to information inputs multi-channel shift register, Ren with a clock input of the control unit, the first and second installation and managing the outputs of which are connected respectively with the combined installation of the inputs of the memory register and the output register, set the input multi-channel shift register and control unit comparing the reliability, the clock inputs of the generator code words, multi-channel shift register, the output register and memory register are combined and input reference frequency of the device, the installation inputs generator code words and the control unit are setup input devices.

2. The device under item 1, characterized in that the generator code words contains the count of code words, the shaper pulse, count the number of digits, the unit's permanent memory, the shift register and the driver clock signal, the outputs of the counter code words are second generator outputs code words and is connected to the input of pulse shaper, the output of which is connected to the enable input of the write shift register and login permissions account counter non discharge, the outputs of which are connected with inputs of the driver clock signal, and the address inputs of the unit's permanent memory, the outputs of which are connected to the inputs of parallel recording re is dy counter code words, counter non discharge and shift register are combined and a clock generator input code words, setting the inputs of the counter code words and count the number of discharge are setup generator input code words, the output driver clock signal is the third generator output code words.

 

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