The device for decoding reed - solomon code

 

(57) Abstract:

The invention relates to telecommunication and computer engineering and can be used to enhance noise immunity in the transmission and processing of digital information, in particular in digital audio. The aim of the invention is the simplification of the device and increase its reliability. This goal is achieved by the introduction of the decoder 14, which allows the display unit single errors 7 to determine whether the error is only one equation in the device containing the block calculation syndrome 1, buffer 2, block 6 calculation of the error locator, block 5 of mask formation, unit 7 error indication, block 12 of the memory values of the syndrome, block 11 keys, block 9 adders. 1 Il.

The invention relates to telecommunication and computer engineering and can be used to enhance noise immunity in the transmission and processing of digital information, in particular in digital video or audio.

A device for decoding reed-Solomon code decoding blocks of computing and cyclic conversion syndromes containing buffer, adders, inverters raditsa fix two erase.

Closest to the proposed device is a decoding device that includes a buffer memory on a 64 byte block of the calculation of the syndromes Siunit storing a value of the syndrome Sothe display unit single errors, the unit for computing the error locator unit forming mask, and blocks of keys and adders; and the first input buffer storage and computing unit syndromes are combined and the corresponding inputs of the device (Ref. INF. ), a clock input device (S) connected to the second inputs of the buffer memory and computing unit syndromes, as well as in parallel to the first inputs of the block forming mask and the unit for computing the error locator, a second input connected to the first output unit display a single error, the second output of which is connected with the second input of the block forming the mask, the third input of which is connected to the synchronization input of the device and in parallel with the third input of the unit for computing the syndromes and the fifth input of the display unit single errors, the first, second, third and fourth inputs of which are connected to the same outputs of the computing unit syndromes; the information output device is output block summate, first input connected to the output of the unit for computing the error locator, the second input of the block of keys is connected to the third input of the above-mentioned block and in parallel with the output unit storing a value of the syndrome So, whose input is connected to the first output of the computing unit syndromes; the third input of the block of keys is connected to the first output of the display unit single errors; the fourth input of the display unit single errors connected to the second output of the computing unit syndromes; output processing unit mask is a control output devices.

The decoding device (prototype) works as follows.

On entering the input sequence are defined syndromes So, S1, S2, S3. If the block is one of erroneous bytes, the syndromes will have the following form:

So= Y1< / BR>
S1= Y1X1< / BR>
S2= Y1X12(1)

S3= Y1X13where Y1- error value;

X1address erroneous symbol;

From this system of equations are equations for the condition of the existence of a single error:

SoS2= S12< / BR>
SoS3= S is atalina reading the block from the buffer memory at the moment when converted syndrome S1coincides with Soi.e. when performing equality S1-i= = So. If the processing unit will be that at least one of the syndromes is nonzero, and is not performed at least one of the equations is the presence of a single error (2), it means that the block has two or more erroneous bytes. In this case, the entire block is masked. If all the syndromes are zero, i.e., So= S1= S2= = S3= 0, it means that there are no errors and the entire unit is supplied to the output without modification.

The disadvantage of the prototype is that the scheme of the decoding device has a large power consumption, and low reliability. This disadvantage stems from the need to check all three equations of system (2) and therefore block circuit indicators mistakes can be quite cumbersome and complex (i.e., includes a large number of chips, which increases power consumption and reduces the reliability of the device).

The aim of the invention is the simplification of the device and increase its reliability by significantly reducing the number of circuits in the display unit single errors and reducing the consumption of electron istwa the opportunity to use to display a single error only one check equation of system (2), namely

S1S3= S1S2, (3) which allows to significantly simplify the block circuit diagram indicating a single error decoding device. However, you receive the chance of a false correction as would a single erroneous bytes in the defeat in the block 4 or more bytes. To test the likelihood of this situation (see research and Development of the codec correcting reed-Solomon code for high-speed videotrack Studio digital video recorder.

The structural scheme of the proposed decoding device shown in the drawing.

It contains a computing unit syndromes 1, buffer 2, and the information input device 3, the clock input device 4, a block forming mask 5, the unit for computing the error locator 6, the display unit single error 7, the synchronization input device 8, the block of the adder 9, the information output device 10, the block of keys 11, a memory unit values of the syndrome 12 control output 13 and the decoder non-zero values of all syndromes 14.

Diagram of the device is as follows.

Upon receipt at the input 3 of the information and the check bytes are written in S3). If all the syndromes are zero, then error correction or masking unit is not performed and no change is given on the output device. If all the syndromes are non-zero, but the equation SoS3= S1S2not running, it means that the block error ratio of 2 or more (t 2), and then, in this case the signal from the second output unit 7 (indicating a single error occurs, the erroneous masking block the signal from the output device 13. When this is entered into the decoder circuit 14 allows you to check not three equations (2) and only one (3), which can be executed only when all of the syndromes are non-zero. If all the syndromes are zero, then begins the process of correcting the erroneous byte in accordance with the algorithm. When this occurs the transformation of the syndrome S1up until T = S1191becomes equal to So(T = So) that specifies the address of the erroneous bytes, to which the signal from the unit for computing the error locator 6 is superimposed syndrome through the power of the keys 11 on the power adders 9 and the outlet 10 receives fixed bytes.

The decoder 14 is implemented on the chip CLE.

The introduction of advanced decoder 14 enables mark to exclude from the device map 4 chips KIM, 4 - CRT and 4 - CSP who consumed the 1.7 A.

Decrease by 12 the number of chips in the scheme of the decoding device increases the reliability of its operation. (56) USSR Author's certificate N 1332539, CL H 03 M 13/00, 1987.

Research and development of the codec correcting reed-Solomon code for high-speed videotrack Studio digital video recorder. Final report on the subject 052-89-09, state reg. N 018900 38301, LEIS, 1990, S. 32.

The DEVICE FOR DECODING REED - SOLOMON CODE containing buffer, the first input of which is combined with the first input of the computing unit syndromes and an information input device, second input buffer storage and computing unit syndromes combined with the first inputs of the unit for computing the error locator and block the formation of the mask and are clocked by the input device, the third input of the computing unit syndromes combined with the second input of the block forming mask and the first input of the error indication and is synchronizing input of the output buffer memory connected to the first input unit adders, the output of which is an information output device, the first output of the computing unit syndromes soedinenii input block key and the second input of the unit for computing the error locator, the output of which is connected to a second input of block keys, the output of which is connected to the second input of the adders, the second output of the computing unit syndromes connected to third inputs of the computing unit locator error and block error indication, the first output of which is connected to the third input of the block key and the fourth input of the unit for computing the error locator, third and fourth outputs of the computing unit of the syndrome are connected respectively to the fourth and fifth inputs of the block error indication, the second output of which is connected to the third input of the block forming the mask, the output of which is a control output, wherein, to simplify the device and improve its reliability, the device entered the decoder, the first-fourth input of which is connected to the same outputs of the computing unit syndromes, the output is connected to the sixth input of the error indication.

 

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