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System of functional testing cards of semiconductor memory Invention relates to testing technology and can be used to diagnose functioning and determining the reliability margin of the semiconductor memory cards. The system consists of the control automatic unit, the interface controller Ethernet, the random access memory, the interface controller of semiconductor memory card, the unit of control registers, the unit of forming and measuring time parameters of the memory card interface with a resolution of 2.5 ns, the frequency multiplier based on the phase-locked loop, the control unit of input device and the display device, the unit of transceiver of the serial interface, the programmable logic integrated circuit, the microcircuit chip of transceiver of the interface Ethernet, the secondary power supply, the constant reprogrammable memory, the voltage level converter of the memory card interface, the clock signal generator 25 MHz, the input device, the display device, the temperature sensor of the memory card, the controlled power supply with the output voltage from 1 V to 5 V, the current sensor, and the contact device for connecting the semiconductor memory card. |
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Method of recovering records in storage device and system for realising said method Method of recovering records in a storage device in case of malfunction or damage to part of the storage device or distortion of data in the storage device, wherein memory of the storage device is partitioned into information areas of the same size and control areas, selected from different parts of the storage device. Each group of data to be stored is recorded in form of a set of code words in a corresponding information area. Three control sums are found, each according a predetermined formula, during each data recording using a corresponding computing unit. Each of the found control sums is then recorded in form of a code word with the same number in the corresponding control area, wherein each of the three control sums is stored in a separate area of the storage device. In case of malfunction or damage to part of the storage device, the computing unit calculates current control sums using formulae for each set of code words with the same numbers in all information areas. Values of the stored control sums and values of the current control sums are used to recover lost data by solving a system of equations. |
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Systems and methods for dynamic power saving in electronic memory operation Memory has a series segmented bit line for accessing data in said memory, a latch repeater which controls bit line segments, wherein the latch repeater is controlled by memory address bits and determinants selected from a list of read- and write-enable signals. The method describes operation of said memory. |
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Adaptation of word line pulse widths in memory systems Systems, schemes and methods for adaptation of word line (WL) pulse widths used in memory systems are disclosed. One version of invention implementation is aimed to device containing memory system. The device includes the following: memory device operating according to pulse of word line (WL) with associated pulse width WL; built-in self test (BIST) module which interacts with memory device where BIST module is made capable to execute self-testing of memory device internal functionality and provide signal indicating whether the memory device has passed self-testing or not; and WL adaptive control scheme, which interacts with BIST module and memory device where WL adaptive control scheme is made capable to adjust memory device WL pulse width based on signal provided by BIST module. |
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Method for random access memory devices testing Method for RAM testing using P-digit pseudo-random number generator based on circular shift register with linear feedback and repetition cycle M. Generator structure is preliminary determined based on inequality system. The method consists in the process where not less than K cycles of testing are carried out in succession in each one of which following procedures are interleaved: procedure of writing test L-digit pseudo-random numbers to all N cells of RAM, and then procedure of reading recorded data from each RAM cell and comparing this data with test pseudo-random numbers. In this process, to generate test L-digit pseudo-random numbers at first new initial non-zero binary P-digit number L digits of which are later used as the first test number is written to pseudo-random number generator, then (N-1) cyclic shifts are carried out sequentially in the shift register with linear feedback and thus N L-digit test numbers are generated. Additionally, selection operation is introduced in which from successively generated pseudo-random numbers only those are selected as test numbers that are spaced apart accurately by L pseudo-random numbers. |
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Apparatus has a memory unit, an input encoding unit, an output encoding unit, an error syndrome calculating unit, a decoder, a switch, a block of switches, a corrector, a block of correctors, a first OR element, a second OR element, an inverter, an AND element, a block of AND elements, a zero state setting input, a write input, a read input, address inputs, data inputs, a clock input, data outputs and an error signal output. |
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Method of restoring records in a storage device, in which, when recording data into information areas of the storage device, its corresponding control areas are populated with at least two reference control sums calculated using predetermined formulas, and when using the storage device, current control sums are calculated multiple times using a computation unit and using the same formulas for each set of codewords with identical numbers in all information areas and each of the calculated current control sums is compared with the corresponding reference control sum to find the error syndrome and replacing the detected errors in records with correct values. |
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Apparatus has a memory module, an input coding unit, an output coding unit, an error syndrome calculating unit, a decoder, switches, compensators, OR elements, an inverter and AND elements. |
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When compressing messages, a word is identified in a massif of initial text information, availability or unavailability of the identified word is determined in a permanent dictionary, if this word is available in the permanent dictionary, the numbering code that identifies the word in the permanent dictionary is placed into the massif of compressed text information, if the word is not available in the permanent dictionary, its availability or unavailability in a temporary dictionary is detected, and if this word is available in the temporary dictionary, the numbering code that identifies the word in the temporary dictionary is also placed in the massif of compressed text information. If the identified word is not available in the temporary dictionary, the identified word is placed into the temporary dictionary and into the massif of the compressed text information. After coding of all layers of the initial text information massif the sequence of numbering codes of the permanent dictionary in the compressed text information is coded with a statistic code. |
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Highly reliable information storage and transmission device Highly-reliable information storage and transmission device has a memory unit, an input coding unit, an output coding unit, an error detection unit, a block of AND elements, an AND element, and OR element, a device reset input, a write input, a read input, address inputs, data inputs, a clock input, data outputs and an "error" signal output. |
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Method and device for speed testing multiport memory array Method of testing a memory array in test mode involves the following: simultaneous writing a first data template on a first address into the memory array through a first write port and a second data template on a second address into the memory array through a second write port, where the first data template is different from the second data template, reading the first and second data templates from the memory array through at least a first read port, and simultaneous comparison of the first data template read from the memory array with the first data template written into the memory array on a first comparator and comparison of the second data template read from the memory array with the second data template written into the memory array on a second comparator which is different from the first comparator, in test mode: receiving a permanent data template at the data input of the first comparator. |
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Read-only memory has memory blocks, initialisation bus, operation mode bus, address bus, recording bus, single error corrector and data bus, word bit packing control unit, blocks of AND elements, block of OR elements and word output unit. Separate address buses for the memory blocks and the word bit packing control unit are connected to each other, forming the common address bus of the device. Separate operation mode buses of the memory blocks are connected to each other, forming a common operation mode bus. Separate initilisation buses of memory blocks, the word bit packing control unit, the single error corrector and the word output unit are connected to each other, forming a common initialisation bus. |
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Invention relates to computer engineering and automation and can be used in memory devices made from large width memory units. The memory device enables use in the memory field of the memory units of large information capacity and large memory width L>1 with pre-packaging of the array of K bit data words after their transformation into an array of N bit code words and their recording in the memory field. The memory device has a corrector for correcting errors in bit words, N memory units with number of data outputs in each equal to L, a common address bus, N separate buses for recording L-bit words, an operation mode common bus and an initialisation common bus, a switch, port registers, port control decoder and an internal dataway. |
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Invention relates to data compression. A network system is made with possibility of setting up data compression and comprises a network, a client and a server which provides the client with a terminal service. The server can compress data and has at least one look-aside buffer. One or more parametres of the compression procedure can be set up in accordance with feedback information which indicates availability of resources for transferring data in the said look-aside buffer of compressed data over the network from the terminal service to the client, and obtained based on amount of time spent on transferring all data from the said look-aside buffer. Methods describe operation of the said system. |
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Method of developing ice control unit software Invention can be used to protect software of the ICE control unit against unauthorised changing. Proposed method of developing software of the running ICE control unit consists in rewriting the software of the ICE control unit into external two-port RAM, restarting ICE, specifying the software data array including calibration tables and constants for ICE running under various operating conditions. The data made more specific is entered into aforesaid two-port external RAM. The development made, the improved software is written into ERPOM of the ICE control unit microcontroller. Note here that, prior to starting ICE, software is divided into an executable code and data array including calibration tables and constants and rewritten into the said two-port RAM. The executable code is written into EPROM, reading out from EPROM is locked by program means. Finally, the data array with calibration tables and constants is changed. The changed data addresses are added to said executable code. Now, improved software is written into EPROM of the ICE control unit microcontroller and reading out from EPROM is locked by program means. |
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Compression of data traces for integral circuit with multiple memory units Invention is related to methods for realisation of data traces in integral circuit with multiple introduced memory units. Tracing module in integral circuit forms packets of tracing data for access to memory of multiple memory units. Memory module comprises multiple data trapping devices (one per every memory) and generator of tracing flow. Every unit of data tracing comprises register, comparator, address compressor and packetisation device. Register stores address for previous access to memory of associated memory. Comparator compares address for current access to memory with address saved in register. Compressors of address and data perform compression of address and data, accordingly, for current access to memory. Packetisation device forms packet of tracing data for current access to memory. Generator of tracing flow generates flow that comprises packets of tracing data, from all devices of data trapping. |
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Architecture of built-in self test (BIST) has distributed interpretation of algorithms and includes three stages of abstraction: centralized controller of built-in self test (BIST), pointer set of sequence and set of interfaces of the storing device. The controller of built-in self test (BIST) saves command sets, which determine algorithm for testing of the storing device's units irrelatively to physical characteristics or distribution requirements of the units of the storing device through time. Sequencers interpreter the commands according to the protocol of commands and generate sequence of operations of the storing device. |
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Random access memory with high extent of fault tolerance Invention is related to the sphere of automatics and computer equipment and is intended for increase of RAM fault tolerance in control systems of true time. Device consists of memory address register (1) redundant RAM (2) equipped with Hamming code, controller of Hamming code (3) register of memory data (4) adder by module two (5) diagnostic cash memory (6) two registers - inverters (7) and (8) input (9) and output (10) multiplexers, element OR (11) element AND (12), adder of word error bits threshold (13) and control box (14). |
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Processing of message authentication control commands providing for data security Invention pertains to the means of providing for computer architecture. Description is given of the method, system and the computer program for computing the data authentication code. The data are stored in the memory of the computing medium. The memory unit required for computing the authentication code is given through commands. During the computing operation the processor defines one of the encoding methods, which is subject to implementation during computation of the authentication code. |
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Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector. |
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Fault-tolerant memorizing device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
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Fault-tolerant information storage device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector. |
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Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector. |
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Self-correcting memorizing device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector. |
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Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector. |
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Self-correcting information storage device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
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Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector. |
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Device contains original circuit, three groups of AND elements, AND element, group of OR elements, OR element, encoding device, register, error syndrome circuit, checks circuit, three decoders. |
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Recording medium for storage of information about record/playback in real-time Information about record/playback in real-time, ensuring record/playback in real-time, is stored in file control information area, in every real-time file, or in a separate file; file is given attributes of record/playback in real-time. |
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Method for storing data with autonomous control and device for storing said data Device has storage, data control block, decoders groups, commutator, encoders group. Method describes operation of said device. |
Another patent 2513106.