# Method of forming s-block

FIELD: information technology.

SUBSTANCE: invention relates to information processing and cryptography and, in particular, to methods of forming S-blocks for replacement with minimum number of logic elements. Proposed method consists of an analytical step, which comprises successive decomposition of initial polynomials, setting S-block, into a sum and product of simpler polynomials, implementation of which requires less total circuit design costs, a synthesis phase, on which are created circuits for implementing said polynomials which cannot be simplified further and on basis of said circuits in reverse order of decomposition final logic circuit for implementation S-block is built, and a third step, during which final logic circuit is implemented in electronic circuit.

EFFECT: reduced circuit design costs when implementing S-block using logic elements & and ⊕ (XOR), providing possibility of taking into account various circuit design costs on implementation of elements & and ⊕ in process of minimising resultant logic circuit of S-block.

1 cl, 6 dwg

**Same patents:**

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to steganography. The method includes the stages of formation of the vector of image compression parameters, input of hidden information, separation of domains and rank areas, correlation of rank areas and domains, forming of final archive. In the method at the stage of separation of domains and rank areas the power of the domain pixels is corrected in view of the value of the hidden information bits.

EFFECT: possibility of hidden transfer of confidential data, using the container represented in the form of fractal compressed image.

2 dwg

FIELD: medicine.

SUBSTANCE: round device realising a sequence of actions for each data encryption device, comprises a summation unit CM1, a substitution box K, a shift unit R, an extra register PREG. In view of using the extra register, a maximum clock frequency in the data flow chart is determined by a maximum delay in the unit CM1, and in the boxes S and R.

EFFECT: higher clock frequency of the encryption device.

3 dwg

FIELD: information technology.

SUBSTANCE: device for encrypting data includes a GOST 28147-89 conversion circuit, an AES conversion circuit, an AES key conversion unit, a first multiplexer, a second multiplexer, a data storage and a key storage; the output of the data storage is connected to the first input of the GOST 28147-89 conversion circuit and to the first input of the AES conversion circuit; the output of the key storage is connected to the second input of the GOST 28147-89 conversion circuit, the second input of the AES conversion circuit, the input of the AES key conversion unit and the second input of the second multiplexer; outputs of the GOST 28147-89 conversion circuit and the AES conversion circuit are connected to the first and second inputs of the first multiplexer, respectively; the output of the first multiplexer is connected to the input of the data storage; the output of the AES key conversion unit is connected to the first input of the second multiplexer; the output of the second multiplexer is connected to the input of the key storage; encryption algorithm selection signals are transmitted to the control inputs of the first and second multiplexers.

EFFECT: reducing the amount of memory required to encrypt data.

3 dwg

FIELD: radio engineering, communication.

SUBSTANCE: system of communication to exchange data via a communication network, which is at least partially public for open use, between the first data processing system and the second data processing system, containing the first data processing system made as capable of data exchange according to the communication protocol, besides, the first data processing system is connected via the first connection with the communication network, which is at least partially public for open use, and the second data processing system containing at least one data processing system made as capable of data exchange according to the communication protocol, at the same time the second data processing system is connected via the second connection with the communication network, which is at least partially public for open use, differing by the fact that at least one of connections contains a connection for data transfer, which is not accessible for data traffic according to the communication protocol.

EFFECT: alarm signal verification provision.

9 cl, 5 dwg

FIELD: information technologies.

SUBSTANCE: method contains stages, at which a sequence of the first rows (29, 30) in data units (P_{j}) is received from a flow, an order of the units (P_{i}) is reversed in each of the first rows (29, 30) of the units, in order to generate the appropriate second rows (31, 37) of the data units, and units are coded on each second row (31, 37) of the units with the help of a code (E_{c}) in the mode of units coupling, initiated with the help of an appropriate vector of initiation (IV_{3}, IV_{N}) for every second row (31, 37) of the units. For the sequence of the first rows (29, 30) of the units included into a single data unit (26) within the flow, at least one initiation vector (IV_{N}) is generated to code the second row (37) of units generated from the first row (30) of the units in the data unit, depending on at least one unit in the preceding first row (29) of the data unit blocks.

EFFECT: reduced required short-term memory at the sender's side.

24 cl, 7 dwg

FIELD: information technologies.

SUBSTANCE: in register forming read-protected zone, a coding key (K) is produced with the help of combination of at least two key parts (KM, M) with application of switching operator, then in memory device serially combination is carried out between the first part of key, verification coding key (Kv) and the second part of key to produce the last combination (Mv), in register combination is provided between K and Mv to produce final verification key (Kf), coding of verification data is carried out (Dv) with the help of symmetrical algorithm of coding (DES), using Kf, and produced result is compared to verification coding (Cv), produced by means of direct coding Dv with the help of Kv.

EFFECT: improved protection of key against unauthorised use in process of transfer from memorising device into register.

2 cl, 1 dwg

FIELD: information technology.

SUBSTANCE: cryptographic processing apparatus and method employ an extended Feistel structure having a number of data lines d which is set to an integer satisfying the condition d≥3. In the said Feistel structure, a several different matrices are selectively applied to linear transformation processes performed in F-function sections. A condition is satisfied, where the minimum number of branches for all data lines corresponding to linear transformation matrices is equal to or greater than a predetermined value. The minimum number of branches for all data lines is selected from among minimum numbers of branches corresponding to the data lines.

EFFECT: high resistance to differential and linear cryptoanalysis.

24 cl, 20 dwg

FIELD: information technologies.

SUBSTANCE: invention is related to the field of coding in data transfer networks. Substance of invention consists in the fact that in system (600) server (610) provides function f of digital signals processing into actuating device (620) in deliberately confused form. Function f includes cascade of functions from functions f_{i} of signals processing, 1≤i≤N, according to formula (I). Server comprises processor (612) to select set of 2N reversible conversions p_{i}, 1≤i≤2N; calculation of set from N functions g, where g is functional equivalent for formula (II) for 1≤i≤N; and calculation of set from N-1 functions h, where h is functional equivalent for formula (III) for 2≤i≤N. Server comprises facility (614) for giving of executive device functions cascade to actuating device, which includes formula (IV), where y_{1},…,y_{N} represent functional parameters for formula (V), and facility (616) for presentation of functions g_{i},…,g_{N} into actuating device. Actuating device includes facility (626) for production of functions g_{i},…,g_{N} and processor (622) for downloading of executive device functions cascade and application of downloaded cascade of executive device functions to functions g_{i},…,g_{N} (for instance, ED,(g_{i},…,g_{N})).

EFFECT: higher extent of protection of cascade signal processing functions.

23 cl, 9 dwg

FIELD: information technology.

SUBSTANCE: present invention relates to cryptography. The essence of the invention lies in the fact that cryptographic computation is carried out in an electronic component according to a particular cryptographic algorithm, which includes at least one specific nonlinear operation on k-bit data blocks, where k is an integer greater than 2. Several masked intermediate data blocks from j bits (b⊕m, c⊕m2, Δ⊕n) based on the initial data block (a) from k bits are generated, where j is an integer less than k. Then a nonlinear operation S is carried out on at least one j-bit masked intermediate data block (Δ⊕n) with the help of a substitution table (106) with 2^{j} two inputs, to obtain a j-bit changed data block (S(Δ)⊕n). The changed j-bit data block is joined with at least several of the indicated j-bit masked intermediate data blocks into one final k-bit block (a'), corresponding to the initial k-bit data block, through transformation, which includes the indicated specific nonlinear operation.

EFFECT: reduction in the memory required for encryption.

19 cl, 2 dwg

FIELD: radio communications engineering, namely, method and device for encrypting signals intended for transmission.

SUBSTANCE: during encryption, five encryption rounds are passed in accordance to block encryption code of alternating length with use of first and second encryption tables and encryption key, first encryption round is performed for one of set of messaging signals in accordance with first encryption key-based transformation, second encryption round of one of messaging signals set is performed in accordance with at least one additional transformation based on encryption key, third encryption round of one of messaging signals set is performed in accordance with self-inverting transformation, during which at least one message from signals set is altered, fourth encryption round of one of set messaging signals is performed in accordance with at least one additional inversed transformation based on encryption key, which is inversion of one additional transformation based on encryption key, fifth encryption round is performed for one of set messaging signals in accordance to first inversed transformation based on encryption key, which is inversion of first encryption key-based transformation.

EFFECT: prevented interception and unauthorized implementation of encrypted information.

8 cl, 6 dwg

FIELD: information technology.

SUBSTANCE: invention realises a common key block encryption processing with improved immunity against attacks, such as attack by saturation and algebraic attacks (RYAS attacks). In the encryption device which performs common key encryption processing, S blocks which are used as nonlinear conversion processing modules in round functions established in round function execution modules are configured to use S blocks of at least two different types. Such a configuration can improve immunity against attacks by saturation. Furthermore, the types of S blocks are a mixture of different types. Use of such a configuration can improve immunity against algebraic attacks, thereby realising a highly secure encryption device.

EFFECT: harder cryptanalysis and realisation of a highly secure common key block encryption algorithm.

52 cl, 19 dwg

FIELD: information technology.

SUBSTANCE: block cipher with common key processing configuration is implemented with improved immunity against such attacks as saturation attacks and algebraic attacks ("РЯС" attack). In the encryption processing device which executes processing of block cipher with common key, S-blocks used as modules of nonlinear transformation processing in round function and installed in round functions execution modules are made capable to use S-blocks of at least two different types. With such configuration, immunity against saturation attacks can be improved. Additionally, types of S-blocks represent mixture of various types.

EFFECT: increased difficulty of cryptanalysis and implementation of highly protected algorithm of block cipher with common key.

14 cl, 19 dwg

FIELD: technology for processing digital data by means of electric devices, in particular, engineering of devices for administrative, commercial, managing, controlling and analytic use.

SUBSTANCE: method for exchanging confidential information, including, in particular, operations for reproducing at a server of single information data block system for remote client terminal performed with decryption of identification address of remote terminal of client and with cryptographic transformation of information data, while transmission of single information data block for remote client terminal is performed in conjunction with generation and dispatching of any number of fake information data blocks.

EFFECT: prevented unauthorized access to information pertaining to connections between participants of confidential information exchange.

5 cl, 3 dwg

FIELD: technology for processing digital data by means of electric devices, in particular, engineering of devices for administrative, commercial, managing, controlling and analytic use.

SUBSTANCE: method for exchanging confidential information, including, in particular, operations for reproducing at a server of single information data block system for remote client terminal performed with decryption of identification address of remote terminal of client and with cryptographic transformation of information data, while transmission of single information data block for remote client terminal is performed in conjunction with generation and dispatching of any number of fake information data blocks.

EFFECT: prevented unauthorized access to information pertaining to connections between participants of confidential information exchange.

5 cl, 3 dwg

FIELD: information technology.

SUBSTANCE: block cipher with common key processing configuration is implemented with improved immunity against such attacks as saturation attacks and algebraic attacks ("РЯС" attack). In the encryption processing device which executes processing of block cipher with common key, S-blocks used as modules of nonlinear transformation processing in round function and installed in round functions execution modules are made capable to use S-blocks of at least two different types. With such configuration, immunity against saturation attacks can be improved. Additionally, types of S-blocks represent mixture of various types.

EFFECT: increased difficulty of cryptanalysis and implementation of highly protected algorithm of block cipher with common key.

14 cl, 19 dwg

FIELD: information technology.

SUBSTANCE: invention realises a common key block encryption processing with improved immunity against attacks, such as attack by saturation and algebraic attacks (RYAS attacks). In the encryption device which performs common key encryption processing, S blocks which are used as nonlinear conversion processing modules in round functions established in round function execution modules are configured to use S blocks of at least two different types. Such a configuration can improve immunity against attacks by saturation. Furthermore, the types of S blocks are a mixture of different types. Use of such a configuration can improve immunity against algebraic attacks, thereby realising a highly secure encryption device.

EFFECT: harder cryptanalysis and realisation of a highly secure common key block encryption algorithm.

52 cl, 19 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and cryptography, and particularly to methods of forming S-blocks with a minimum number of logic elements for subsequent implementation in devices for protecting data using cryptographic methods. The method comprises: based on a given S-block, constructing a system of Boolean functions in the form of truth tables; multiplying a 2^{n}×2^{n} binary matrix by a Boolean function value; obtaining a system of Zhegalkin polynomials; at the analysis step, determining data for minimisation, and at the synthesis step, obtaining the resultant logic circuit for implementing the S-block, followed by hardware implementation of the circuit based on different integrated microcircuits, including programmable logic devices.

EFFECT: low circuit design costs when implementing an S-block by minimising the resultant logic circuit.

8 dwg, 5 tbl

FIELD: information technology.

SUBSTANCE: invention relates to information processing and cryptography and, in particular, to methods of forming S-blocks for replacement with minimum number of logic elements. Proposed method consists of an analytical step, which comprises successive decomposition of initial polynomials, setting S-block, into a sum and product of simpler polynomials, implementation of which requires less total circuit design costs, a synthesis phase, on which are created circuits for implementing said polynomials which cannot be simplified further and on basis of said circuits in reverse order of decomposition final logic circuit for implementation S-block is built, and a third step, during which final logic circuit is implemented in electronic circuit.

EFFECT: reduced circuit design costs when implementing S-block using logic elements & and ⊕ (XOR), providing possibility of taking into account various circuit design costs on implementation of elements & and ⊕ in process of minimising resultant logic circuit of S-block.

1 cl, 6 dwg

FIELD: physics.

SUBSTANCE: device contains a random number generation block, a block of the original logical data encryption, a logical data decryption unit, 2^{n} channel for transferring the values of the coefficients, n a channel bus for transferring the values of the logical variables, a 5-channel bus for transferring the values of the delimiter modules, k a channel data transmission line of the values of the first system of k modules, q a channel data transmission line of the second system q modules, a 3-channel bus transfer of random numbers, 2^{n}kq channel data transmission line of encrypted coefficients values, knq channel data transmission line of encrypted logical variables, kq channel transmission bus of polynomial calculation values, s channel bus of Boolean function calculation transfer values.

EFFECT: increasing the performance of the device supporting secure of logical calculations.

8 dwg

FIELD: cryptography.

SUBSTANCE: block for generation of sub-keys data uses two different processes for open generation of sub-keys. During encoding of T*n block of open text, where T - length of predetermined cycle, n - positive integer, sixteen sets of sub-key data is generated. In al other cases two sets of sub-key data are generated. Encryption block encrypts open text, using formed sixteen or two sets of sub-keys data.

EFFECT: higher efficiency.

6 cl, 15 dwg