Method of producing structure

FIELD: electronics.

SUBSTANCE: invention can be used for creation of high-frequency structures. Core of invention is that method of making structure containing in certain order support substrate, dielectric layer, active layer, made in semiconductor material, so called separation layer of polycrystalline silicon, placed between support substrate and dielectric layer, wherein method involves following steps: step of providing donor substrate made in said semiconductor material; step of making field embrittlement in donor substrate to separate first and second parts of donor substrate on each side of field of embrittlement, wherein first part is intended for forming active layer; stage of provision of support substrate with resistivity above predetermined value; step of forming separating layer on support substrate; step of making dielectric layer on first part of donor substrate and/or on separating layer; stage of assembling donor substrate and support substrate through intermediate link of said dielectric layer and separating layer; stage of cracking donor substrate in area of embrittlement to obtain said structure; stage of reinforcing structure by annealing at least during 10 minutes after cracking; wherein said method is performed so, that polycrystalline silicon of separating layer (20) has completely random orientation of grains in at least part of thickness of separating layer (20), facing support substrate (2), and so that hardening annealing is performed at temperature strictly higher than 950 C and lower than 1,200 C.

EFFECT: technical result is possibility of creation of high-frequency structures without intermediate processing.

16 cl, 4 dwg

 



 

Same patents:

FIELD: chemistry.

SUBSTANCE: invention relates to semiconductor technology and can be used for manufacturing device structures. Implantation of ions is performed into silicon substrate with formation of layer, intended for transfer. Activating processing of surface, on which splicing is carried out, is realised. Silicon and sapphire substrates are joined in pairs with surfaces, intended for splicing. They are preliminarily given the temperature, corresponding to the state of their materials, conditioned by thermal expansion, which guarantees absence of destruction causing internal mechanical tensions when they are joined in pairs and then subjected to thermal impact. Splicing of surfaces of silicon substrate and sapphire substrate with each other are layering are performed, realising transfer of silicon layer on sapphire substrate and obtaining structure.

EFFECT: due to preliminary, before joining into pairs, heating of substrates to temperatures 200-400C increased resistance of silicon-on sapphire structure to mechanical destruction in case of heating/cooling, reduction of concentration of defects in silicon are achieved.

11 cl, 4 dwg

FIELD: nanotechnology.

SUBSTANCE: invention relates to the field of micro-and nanoelectronics. The method of manufacturing a dielectric layer of MIS structures having the effect of switching is application of the nanocomposite film of silicon oxynitride with the incorporated silicon clusters. Application is carried out by the method of plasma sputtering of the silicon target at a deposition rate of 5-7 nm/min in argon medium with additives of 3-5 vol% oxygen and 6-8 vol% nitrogen.

EFFECT: obtaining dielectric layers having the effect of conductivity switching, fully compatible with the materials, as well as with most technological influences used in traditional silicon technology of integrated circuits.

2 cl, 3 dwg

FIELD: electricity.

SUBSTANCE: to amorphous insulating layer SiO2 of Si substrate ions of light segregating impurity are implanted which are capable to form nanocrystals within volume of the layer SiO2-Si+ or Ge+. Localisation area of the implanted impurity is obtained. Implantation modes ensure concentration of the implanted additive sufficient to form nanocrystals not less than 10 at.% and not more than 20 at.% at which the distance between introduced foreign atoms is less than their diffusion length at annealing and location of localisation area for the implanted impurity at distance of the semiconductor surface layer is not less than diffusion length of the implanted impurity at annealing. Donor substrate made of Si is connected with SiO2 layer of the substrate and coupling procedure is performed with formation of surface Si layer of the required thickness at SiO2 thus making silicone-on-insulator structure. Finally annealing is made providing diffusion of the introduced impurity, coalescence and formation of nanocrystals in amorphous insulating layer.

EFFECT: due to formation of nanocrystals being traps for negative charges unfavourable influence of the built-in positive charge in dielectric compensated thus ensuring improvement in structure quality, removing sequences of ionising radiation expanding application scope.

14 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: method for making silicon-on-insulator structure involves implantation to amorphous insulating SiO2 layer of a silicon substrate of ions of easily diffusing mixture removing irregular connections and saturating failed connections in SiO2 layer and/or at the boundary between SiO2 layer and surface layer of silicon - F+. A localisation area of implanted impurity is formed under conditions providing concentration of implemented impurity of not less than 0.05 at % and not more than 1 at %, which is sufficient for elimination of negative occurrences of irregular and failed connections, at doses of not less than 31014 cm-2 and less than 51015 cm-2. A silicon donor substrate is connected to SiO2 layer of the substrate and splicing is performed with formation of a surface silicon layer of the required thickness on SiO2, thus making silicon-on-insulator structure. Finally, annealing is performed under conditions providing diffusion of introduced impurity with removal of irregular connections and saturation of failed connections in SiO2 and/or at the boundary between SiO2 layer and SiO surface layer, at the temperatures of 700-1100C, with duration of more than 0.5 hour, in inert atmosphere.

EFFECT: improving quality of the structure, enlarging application field of the method for creation of devices with increased stability to action of ionising emission.

12 cl, 2 dwg

FIELD: electricity.

SUBSTANCE: solid-state material is taken, which has a thermal expansion ratio and at least one surface suitable for generation of a layer on it. A polymer layer is formed on the specified surface so that adhesion remains between a solid-state layer and a polymer layer within the entire specified range of TS temperatures between the first temperature and the second temperature. The polymer layer has a thermal expansion ratio different from the thermal expansion ratio of the solid-state material. Further the solid-state material and the polymer layer attached by adhesion are exposed to variation of local temperature from the first temperature, which is not higher than approximately 300C, to the second temperature, which is lower than approximately room temperature, thus causing mechanical stress in the solid-state material due to difference between the thermal expansion ratio of the solid-state material and the thermal expansion ratio of the polymer layer, in order to cause breakage of the solid-state material along the inner plane in the thickness of the solid-state material, to manufacture at least one autonomous solid-state layer from the specified solid-state material. The polymer layer is additionally characterised by vitrification temperature, which is lower than approximately the first temperature and higher than approximately the second temperature, and is sufficiently low to prevent breakage or cracking of the polymer at the second temperature.

EFFECT: development of the method of thermal treatment to manufacture high-quality autonomous solid-state layers preserving characteristics of an initial material, of which they are made, and used for microelectronics.

20 cl, 6 dwg, 1 ex

FIELD: electricity.

SUBSTANCE: method for formation of dielectric layer with conductivity switching effect consists in application of composite material representing silicon-based dielectric array with inclusions of clusters. Such material structure permits to provide conductivity switching effect. Application is executed by deposition of siliceous material representing mixture of silane with oxygen- and/or nitrogen-containing gases in low-frequency glow discharge plasma at the frequency of 3-200 kHz.

EFFECT: obtaining dielectric layers with conductivity switching effect which are fully compatible with materials as well as most of manufacturing impacts used in conventional silicon technology of integrated circuits.

3 dwg

FIELD: physics, semiconductors.

SUBSTANCE: application: microelectronics, technology of integral microchips (IMC) manufacture. In method of self-aligned formation of insulation of IMC elements and polysilicon contacts to substrate and n+ - hidden layer on semiconducting substrate with solid hidden and epitaxial layers, the first and second dielectric layers are formed, in which photolithography is used to open window in place of future collector contact to n+ - hidden layer, separating third dielectric is formed on window vertical walls, screening layer is formed in window, simultaneously windows are opened in the first and second dielectrics for deep insulating area and contact to substrate, slot is etched for depth of epitaxial, hidden layers and partially substrate, and in place of collector contact separating dielectric is formed for depth of screening and epitaxial layers on vertical walls of slot, back channel areas are formed on the bottom of deep insulating slots, the second and third dielectric are formed in slots, dielectrics are locally etched from slot bottom for contacts, and slots are filled with polysilicon, polysilicon and dielectrics planarisation is carried out, dielectric is formed on substrate, windows are opened in dielectric for contacts to substrate and to hidden layer, contacts are formed.

EFFECT: increased density of layout and reduction of technological cycle time.

9 dwg

The invention relates to semiconductor equipment

FIELD: physics, semiconductors.

SUBSTANCE: application: microelectronics, technology of integral microchips (IMC) manufacture. In method of self-aligned formation of insulation of IMC elements and polysilicon contacts to substrate and n+ - hidden layer on semiconducting substrate with solid hidden and epitaxial layers, the first and second dielectric layers are formed, in which photolithography is used to open window in place of future collector contact to n+ - hidden layer, separating third dielectric is formed on window vertical walls, screening layer is formed in window, simultaneously windows are opened in the first and second dielectrics for deep insulating area and contact to substrate, slot is etched for depth of epitaxial, hidden layers and partially substrate, and in place of collector contact separating dielectric is formed for depth of screening and epitaxial layers on vertical walls of slot, back channel areas are formed on the bottom of deep insulating slots, the second and third dielectric are formed in slots, dielectrics are locally etched from slot bottom for contacts, and slots are filled with polysilicon, polysilicon and dielectrics planarisation is carried out, dielectric is formed on substrate, windows are opened in dielectric for contacts to substrate and to hidden layer, contacts are formed.

EFFECT: increased density of layout and reduction of technological cycle time.

9 dwg

FIELD: electricity.

SUBSTANCE: method for formation of dielectric layer with conductivity switching effect consists in application of composite material representing silicon-based dielectric array with inclusions of clusters. Such material structure permits to provide conductivity switching effect. Application is executed by deposition of siliceous material representing mixture of silane with oxygen- and/or nitrogen-containing gases in low-frequency glow discharge plasma at the frequency of 3-200 kHz.

EFFECT: obtaining dielectric layers with conductivity switching effect which are fully compatible with materials as well as most of manufacturing impacts used in conventional silicon technology of integrated circuits.

3 dwg

FIELD: electricity.

SUBSTANCE: solid-state material is taken, which has a thermal expansion ratio and at least one surface suitable for generation of a layer on it. A polymer layer is formed on the specified surface so that adhesion remains between a solid-state layer and a polymer layer within the entire specified range of TS temperatures between the first temperature and the second temperature. The polymer layer has a thermal expansion ratio different from the thermal expansion ratio of the solid-state material. Further the solid-state material and the polymer layer attached by adhesion are exposed to variation of local temperature from the first temperature, which is not higher than approximately 300C, to the second temperature, which is lower than approximately room temperature, thus causing mechanical stress in the solid-state material due to difference between the thermal expansion ratio of the solid-state material and the thermal expansion ratio of the polymer layer, in order to cause breakage of the solid-state material along the inner plane in the thickness of the solid-state material, to manufacture at least one autonomous solid-state layer from the specified solid-state material. The polymer layer is additionally characterised by vitrification temperature, which is lower than approximately the first temperature and higher than approximately the second temperature, and is sufficiently low to prevent breakage or cracking of the polymer at the second temperature.

EFFECT: development of the method of thermal treatment to manufacture high-quality autonomous solid-state layers preserving characteristics of an initial material, of which they are made, and used for microelectronics.

20 cl, 6 dwg, 1 ex

FIELD: electricity.

SUBSTANCE: method for making silicon-on-insulator structure involves implantation to amorphous insulating SiO2 layer of a silicon substrate of ions of easily diffusing mixture removing irregular connections and saturating failed connections in SiO2 layer and/or at the boundary between SiO2 layer and surface layer of silicon - F+. A localisation area of implanted impurity is formed under conditions providing concentration of implemented impurity of not less than 0.05 at % and not more than 1 at %, which is sufficient for elimination of negative occurrences of irregular and failed connections, at doses of not less than 31014 cm-2 and less than 51015 cm-2. A silicon donor substrate is connected to SiO2 layer of the substrate and splicing is performed with formation of a surface silicon layer of the required thickness on SiO2, thus making silicon-on-insulator structure. Finally, annealing is performed under conditions providing diffusion of introduced impurity with removal of irregular connections and saturation of failed connections in SiO2 and/or at the boundary between SiO2 layer and SiO surface layer, at the temperatures of 700-1100C, with duration of more than 0.5 hour, in inert atmosphere.

EFFECT: improving quality of the structure, enlarging application field of the method for creation of devices with increased stability to action of ionising emission.

12 cl, 2 dwg

FIELD: electricity.

SUBSTANCE: to amorphous insulating layer SiO2 of Si substrate ions of light segregating impurity are implanted which are capable to form nanocrystals within volume of the layer SiO2-Si+ or Ge+. Localisation area of the implanted impurity is obtained. Implantation modes ensure concentration of the implanted additive sufficient to form nanocrystals not less than 10 at.% and not more than 20 at.% at which the distance between introduced foreign atoms is less than their diffusion length at annealing and location of localisation area for the implanted impurity at distance of the semiconductor surface layer is not less than diffusion length of the implanted impurity at annealing. Donor substrate made of Si is connected with SiO2 layer of the substrate and coupling procedure is performed with formation of surface Si layer of the required thickness at SiO2 thus making silicone-on-insulator structure. Finally annealing is made providing diffusion of the introduced impurity, coalescence and formation of nanocrystals in amorphous insulating layer.

EFFECT: due to formation of nanocrystals being traps for negative charges unfavourable influence of the built-in positive charge in dielectric compensated thus ensuring improvement in structure quality, removing sequences of ionising radiation expanding application scope.

14 cl, 4 dwg

FIELD: nanotechnology.

SUBSTANCE: invention relates to the field of micro-and nanoelectronics. The method of manufacturing a dielectric layer of MIS structures having the effect of switching is application of the nanocomposite film of silicon oxynitride with the incorporated silicon clusters. Application is carried out by the method of plasma sputtering of the silicon target at a deposition rate of 5-7 nm/min in argon medium with additives of 3-5 vol% oxygen and 6-8 vol% nitrogen.

EFFECT: obtaining dielectric layers having the effect of conductivity switching, fully compatible with the materials, as well as with most technological influences used in traditional silicon technology of integrated circuits.

2 cl, 3 dwg

FIELD: chemistry.

SUBSTANCE: invention relates to semiconductor technology and can be used for manufacturing device structures. Implantation of ions is performed into silicon substrate with formation of layer, intended for transfer. Activating processing of surface, on which splicing is carried out, is realised. Silicon and sapphire substrates are joined in pairs with surfaces, intended for splicing. They are preliminarily given the temperature, corresponding to the state of their materials, conditioned by thermal expansion, which guarantees absence of destruction causing internal mechanical tensions when they are joined in pairs and then subjected to thermal impact. Splicing of surfaces of silicon substrate and sapphire substrate with each other are layering are performed, realising transfer of silicon layer on sapphire substrate and obtaining structure.

EFFECT: due to preliminary, before joining into pairs, heating of substrates to temperatures 200-400C increased resistance of silicon-on sapphire structure to mechanical destruction in case of heating/cooling, reduction of concentration of defects in silicon are achieved.

11 cl, 4 dwg

FIELD: electricity.

SUBSTANCE: invention is related to the area of micro- and nanoelectronics, and namely to structure of dielectric layer for MIS structures having conductivity switching effect. Peculiarity of the suggested structure consists in formation of 1-5 layers of silicon-based material with thickness of 1-5nm inside the main dielectric film - large-gap semiconductor of oxide and/or silicone nitride or their alloys with carbon or germanium, with built-in nanosize silicon clusters; and the above material differs in chemical composition and less width of forbidden gap from material of the main layer.

EFFECT: manufacturing silicon-based dielectric layers for MIS structures having conductivity switching effect, which allows manufacturing MIS structures off small area with increased yield of good structures.

2 dwg

FIELD: electronics.

SUBSTANCE: invention can be used for creation of high-frequency structures. Core of invention is that method of making structure containing in certain order support substrate, dielectric layer, active layer, made in semiconductor material, so called separation layer of polycrystalline silicon, placed between support substrate and dielectric layer, wherein method involves following steps: step of providing donor substrate made in said semiconductor material; step of making field embrittlement in donor substrate to separate first and second parts of donor substrate on each side of field of embrittlement, wherein first part is intended for forming active layer; stage of provision of support substrate with resistivity above predetermined value; step of forming separating layer on support substrate; step of making dielectric layer on first part of donor substrate and/or on separating layer; stage of assembling donor substrate and support substrate through intermediate link of said dielectric layer and separating layer; stage of cracking donor substrate in area of embrittlement to obtain said structure; stage of reinforcing structure by annealing at least during 10 minutes after cracking; wherein said method is performed so, that polycrystalline silicon of separating layer (20) has completely random orientation of grains in at least part of thickness of separating layer (20), facing support substrate (2), and so that hardening annealing is performed at temperature strictly higher than 950 C and lower than 1,200 C.

EFFECT: technical result is possibility of creation of high-frequency structures without intermediate processing.

16 cl, 4 dwg

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