Neurocomputer

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing strapdown inertial reference systems which are part of automatic control systems for highly-manoeuvrable ships, aircraft, space rockets and spacecraft in particular, as well as mobile robotic systems which are characterised by operability in extreme conditions. The device includes a microprogramme control unit, two matrix neuroprocessor units, an operational device, matrix memory, a secondary power source, a communication unit, authorised access memory and an environment sensor.

EFFECT: faster matrix computations.

23 cl, 20 dwg

 

This invention relates to computing.

Control systems of mobile objects such as aviation and rocket-space technology, as well as mobile robotic systems as one of the main links include subsystem inertial navigation, which traditionally was based on a gyroscopic platform. However, a limited range of variation of the angular positions of an object virtually eliminates its use for highly maneuverable objects. In this regard, recently more and more widespread device of the inertial system (sins), in which no mechanical gyroscopes, defining the basic orientation of the inertial system of coordinates, funds and power stabilization with numerous wiring harnesses that restrict angular movement rigidly connected with the design of the control object of the hull of the platform.

In a strapdown inertial navigation system inertial coordinate system is calculated mathematically on-Board computing devices on information from accelerometers and angular velocity sensor, which is used as the ring laser sensors, ring laser gyroscopes and fiber optic gyroscopes. Regardless of the type of sensor requires high-speed processing of information about the corner soon�level positions, and its conversion into an inertial coordinate system. At the heart of these transformations are matrix calculations, where the elements of matrices are used trigonometric functions sinx and cosx. Despite significant progress in the field of airborne digital computers (OBC) their performance is not sufficient for solving problems of the sins, because the software calculation of the trigonometric function takes significant time (several milliseconds), and is required for 1 millisecond to form a complete three-axis inertial system. This raises the need for the introduction of the OBC or in addition to specialized computing devices, oriented according to the desired time tasks bins, These devices must be focused primarily on fast computation of trigonometric functions and matrix calculations. A number of specialists in recent times for the computation of functions of one or several variables is proposed to use a neural network. This trend seems to be quite promising for the modernization of the OBC, in order to accelerate the solving of the sins. It is well known that the trigonometric functions sinx and cosx can be represented by a polynomial representing the sum of the members of the various degrees of the variable x with the corresponding coefficients. For fast imple�ation of computing the applicable neural networks, in which you need to implement a quick summation and multiplication, and "training" the network lead by recording in the memory of the computers of the corresponding functions computed coefficients of the polynomial. In neural computers known proposals (See article A. N. Gorban "Generalized approximate theorem and computational capabilities of neural networks" / Siberian journal of computational mathematics, 1998, T1 No. 1, pp. 12-24), where the figures (Fig.1 - Fig.4) some examples of constructing components of neural networks based on the adders with a set of weighting coefficients at the input. However, the absence in their composition of hardware multipliers and money factor for "training" the network, which is a requirement for configuring compute specific functions can not use them to create specialized calculators beans. Some decisions on the components of neural networks are given in another source (See L. N. Yasenetsky "Introduction to artificial intelligence" Training. manual for schools, 2nd edition. Ed. "Academy"), where on page 29 describes the neuron Mac-Kalona, Pitts on the basis of several components containing the adder works variable and coefficients, and the elements AND, OR, NOT). However, the lack of multipliers and money factor for "training" the network is also not possible to use these �demand of the task: fast computation of trigonometric functions.

Most fully the task of creating calculators, based on the principles of neural networks is solved in the invention "Neuroprocessor" (Cm. patent RU №2473126, from 20.01.2013), which can be taken as a prototype. Known neuroprocessor contains a communication unit (BS) with OBC upper level of the automatic control system, the unit microprogrammed control (LCU) and a set of multipliers with adders. However, in the present invention are not fully solved the problem of fast matrix computation, which is the basis of bins algorithms, as well as the task of the evaluator in the composition of the management systems of rocket and space technology (in particular spacecraft and robotic systems, designed to operate in extreme conditions(wide range of changes in ambient temperature from -60 to +125 degree Celsius, mechanical effects in the form of strikes and broadband vibration) fields and ionizing radiation of outer space, pulsed radiation during solar flares, the accidents of nuclear power plants and sent to the opposition causing short-term disruptions in the operation of the equipment and parametric changes in electrical characteristics of semiconductor structures, which are the basis of the BIS, which sold components of the processor, and causing a change bistromath�ia BIS, which ultimately makes the CPU is unworkable and does not allow to use fully the capabilities of neural network architectures for solving tasks of the sins in the systems of automatic control of the products and objects of rocket and space technology and, in particular, spacecraft, and robotic systems designed to operate in extreme conditions and fields of ionizing radiation.

For systems that control spacecraft with a long time there is also the problem of neutralization of failures caused by natural aging of the equipment and the flow of heavy charged particles.

In this regard, in the use of digital computing devices in automatic control systems such facilities and systems require neutralization as catastrophic failures caused by natural aging of the equipment and the flow of charged particles, and parametric changes in semiconductor materials due to temperature changes and radiation effects in integrated circuits, to create a modern on-Board computing device. All this requires new solutions in the field of building computing devices, focused on the use in the control system with the sins. To solve postavljen�x problems we propose to use a directed at solving problems Binns

The NEURAL network EVALUATOR (hereinafter Neuromechanical or just the Transmitter).

The composition of the transmitter includes a communication unit (BS), connected the main line with a storage device (memory) and storage device authorized access, blocking the entrance of which is connected to the output of the sensor to an external influence. The outputs are connected to the BS unit and microprogrammed control (LCU) and setting the input of the secondary power supply (SMPS). To trunk line connected to the first and second matrix blocks neuroprocessor (BNP) whose inputs are connected to the outputs of BS, and their outputs connected to the operating unit (OU) containing series-connected multiplier and the adder. The output of op-amp is connected to the memory storing the resulting matrix computations, the contents of which are using BS OBC can be read as a trunk multiplex input / output BS is the input-output of the transmitter connected to the OBC. The outputs of the BMU is connected to the control inputs of all digital components of the transmitter.

Besides the power input of the SMPS is the power input of the transmitter, and the installation input of the SMPS is connected to the installation exit BS.

IWEP contains module DC supply (WFP) and a pulse power module (MIP), power input is the power input source, set�reference input of which is the same entrance WFP and the shaper clock (SIF), three control outputs of which are connected to the control inputs of the MIP, and the outputs of the DC and pulsed power modules, and the clock SIF outputs are the outputs of the DC and pulsed power and clock power.

Every BNP contains nine neuroprocessor, forming a matrix of dimension 3×3. The input of each of the neuroprocessor is connected to the output of the coupling network with OBC, and the main inputs-exits the neuroprocessor is connected to the duplicated route, which is the outer line of the block.

LCU base register contains the opcode, base register signs, the inputs of which are inputs of the indication unit, a base counter base address and the register offset, the installation inputs which are input unit is connected to the output of BS, and their outputs form the address bus connected to the base firmware of the storage device (BESU), the outputs of which are outputs of the block and additional outputs BESU connected to the inputs of the base register offset.

The communication unit includes a processor, input-output of which is the main entrance-exit of the block. Through the first bidirectional communication is connected to the processor connected to a storage device, and via a second bi-directional communication through coding-decoding device about�essor connected to the receiving and the transmitting device main multiplex line connection, which line of the block and neuromechanical overall with the top-level subsystems and OBC in particular.

Each neuroprocessor, a part BMNP contains a microprocessor, inputs and input-output of which are the inputs and the input-output neuroprocessor. Via a bidirectional bus connected to CPU memory, and the output of the microprocessor via a buffer register connected to the set input of the processor BMU and to the n inputs of multipliers connected in series tires transfer. The outputs of the multipliers are connected to the inputs of the adder, the output connected to the input of the circuit connection, the input-output of which is combined with the input-output of the microprocessor is the entrance-exit of the neuroprocessor.

Processor LCU processor contains a register code, processor register signs, the inputs of which are inputs of the indication unit, the CPU address counter and processor register offset, the installation inputs of these registers and the counter are installation input unit, and their outputs form the address processor bus connected to the CPU firmware storage device, the outputs of which are control block outputs, and the additional outputs of this memory device are connected to the inputs of processor register mixing.

SUSD includes first and �Torah drives, the blocking inputs of which are blocking the entrance SUSD. In addition to the input of each drive the first and the second connected to the output of its adder timestamps, respectively, of the first and the second input of each of which is an input timestamp of the storage device and via the first bidirectional communication to each drive is connected to the first and second the adder arrays, respectively, first and second input-output of each of which, together with the entrance-exit of each of the drives connected to the main memory bus, which is the backbone of neuromechanical.

The SMPS includes with its membership module DC supply (WFP) and a pulse power module (MIP), power inputs of which are the power input source, set the input of which is the installation of the entrance WFP and the shaper clock (SIF), three control outputs of which are connected to the corresponding inputs of the MIP, and the outputs of the timestamp and clock SIF, DC WFP and pulse MIP are the same SMPS outputs.

WFP contains three identical Converter, the installation inputs are setup input source. The frequency outputs of the converters are connected to the frequency inputs of the control unit and the Board (BCU).

The outputs of the converters also under�mediately to the control inputs through the SCU and block off (BO) are connected to the inputs of the alignment unit (BV), the yield which is the output of the module and the power supplies and connected to the additional control input of the SCU, the outputs of which are connected to the control inputs BO.

The MIP contains three identical branches, combined with each of the parties, one of which is a power input, a second output. Every branch of two series-connected field effect transistors, and three input control signal is diluted so that each of them is connected to the gates of two transistors mounted in different branches. This layout provides reservation execution control signals according to the principle of the majority of the sample "2 of 3".

The Converter contains a filter, the input of which is the power input of the Converter. Behind the filter transformer included in the gap primary winding of which is mounted the transistor - breaker. After the secondary winding installed a rectifying diode (diode bridge), followed by the output low pass filter. The output of this filter is the output of the Converter, which is connected to the feedback circuit, beginning with a Converter voltage to frequency. The output of this Converter is connected to the input of element isolation (galvanic isolation), the output of which is frequency output of the Converter and, in turn, is connected to the input of pulse-frequency modulator (PFM), which ends about�atna communication, because its output connected to the base of transistor - breaker, the switching frequency for changing the output voltage level of the Converter, and an introduction to CHIME installation log, which is the installation input of the Converter allows you to set the value generated by the frequency modulator interrupt transistor and hence to control the output voltage of the Converter.

BO contains three field effect transistors, the origins of which are the inputs, the remaining outputs, and control inputs connected to the gates of transistors.

BV contains three identical chains. In each circuit series resistor and diode. The first resistor is input. A second output resistor connected to the anode of the diode of the circuit. The cathodes of all three diodes are combined to form the output block.

The SCU contains the first, second, third and fourth frequency counters. The first three inputs are frequency inputs of the block are connected respectively to the frequency outputs of the first, second and third converters. The input of the fourth counter connected to the output of the control voltage Converter in the frequency, the inputs of which are the control and additional control inputs of the unit connected to the outputs of the converters and the alignment unit. The output of the first counter connected to the first inputs of the first and the second summit�the moat. The output of the second counter connected to the second input of the second adder and the first input of the third adder, and the output of the third counter connected to the second inputs of the third and first adders. The output of the fourth counter connected to the first input of the fourth adder, the second input of which is connected to the register output control code, the output of which is connected to second inputs of all control schemes comparison. In this case, the input register of the control code is combined with the input of the admission register, the outputs of which are connected to second inputs of the first, second, third and fourth control circuits of the comparison. The outputs of these circuits are connected to the inputs of corresponding first, second, third and fourth triggers errors, the outputs of which are connected to a control group of logic elements, the outputs of which are outputs of the unit connected to the control inputs of the block off.

SIF contains the first, second and third pulse generator, set the input of each of which is an installation input of the shaper, and the output of each generator is connected to the input of their, respectively, the first second and third block phasing. Phasing the output of each of these blocks is connected to a phasing of the two inputs of other units and phasing of the inputs of the block of majoritatea, to the clock inputs catalogoptions synchronizing the outputs of blocks phasing, and the outputs of the block of majoritatea are exit timestamp and clock driver.

The pulse generator included in the SIF contains multiple (n) of series-connected inverters, connected the outputs to the inputs of the first multiplexer. The output of this multiplexer is the output of the generator and is connected to the input of the first inverter and the input of the first counter frequency. The outputs of this counter are connected to the first inputs of the first comparison circuit, the second inputs of which are connected the outputs of the first register code. The increment and decrement outputs of the first comparison circuit connected to the corresponding inputs of the first counter code frequency, the outputs of which are connected to the control inputs of the first multiplexer. In addition the installation input of the first register code and the installation input of the first counter installation code are the input of the generator.

The unit contains an element phasing And, a first input which is the input unit and the output connected to the input of the shift register and implemented on dynamic triggers the counter, the output of which through a decoder connected to the input of the trigger stop, the output of this trigger is phasing the output of the block and connected to the second input element And the first input of the majority element, the output of which is connected to the input trigger start, connected�about access to the reset input of the trigger stop. Second and third input of the majority element connected to the outputs of the triggers binding, the inputs of which are phasing inputs of the block. The outputs of even and odd bits of the shift register are connected respectively to the start and reset inputs f triggers - shapers, the outputs of which are the clock outputs of the block.

CHIM contains a group of serially connected inverters, connected the outputs to the inputs of the second multiplexer. The output of this multiplexer is connected to the input of the first inverter group and is the generator output, the input of which is the input of the second counter frequency. The output of the second frequency counter connected to the first inputs of the second comparison circuit, the second inputs of which are connected the outputs of the second register code. The increment and decrement outputs of the second comparison circuit connected to the corresponding inputs of the second counter code frequency, the outputs of which are connected to the control inputs of the second multiplexer. In addition the installation input of the second register code and the installation input of the second counter installation code are the input of the generator.

Dynamic trigger is implemented as a transistor amplifier with a peculiarity to the base of transistor trigger in addition to the resistor divider that sets the operating point of the transistor p�clucene as an element of the memory circuit of inductance L and capacitor C. The feature is that to provide protection from external trigger electromagnetic interference inductance has two windings, the working and compensation.

Compensation winding is wound on top working counter to the working coil winding arrangement of the coils.

The composition of Neuromechanical and constituents are given in the form of schemes and structures in the figures from 1 to 8.

Figure 1 shows the composition of Neuromechanical, where the numeral 1 designates LCU, figures 2-1 and 2-2 denote the first and second blocks of the matrix calculators, numeral 3 denotes Oh, figure 2-3 designated matrix storage device, figure 4 - power supplies and the number 5 marked with the communication unit.

The block matrix of processors is shown in figure 2. Here by the numerals 21-1 to 23-3 marked the neuroprocessor and figure 24 is a communication device.

Neuroprocessor is shown in figure 2-1. Here numerals 210 designated microprocessor, numerals 211 to the CPU memory 212 is a buffer register, numerals 213 designated processor LCU, the numbers 214-1 to 214-n are multipliers, numerals 215 - adder and numeral 216 is designated communication device.

Operating the device shown in figure 3, where the numbers 31 marked block multiplication, the digits of a 32 - unit adders and figures 33 designated communication unit matrix with memory.

SMPS is shown in figure 4, where qi�Rami 41, 42 and 43 denote the module DC power module pulse power and SIF.

WFP is shown in figure 4-1. The figure numerals 41-1, 41-2 and 41-3 designated converters, numerals 412 BEECH and numerals 413 and 414 denote the BO and BV.

This is shown in figure 4-1-1. Here the numbers 4111 and 4112 denote the filter and output filter. Numbers 4116 designated transformer. Figures 4113 marked voltage Converter in the frequency, number 4114 - element isolation and figures 4115 marked CHIM.

Figure 4-1-2 shows BEECH. In this figure, the numbers 4121-1 to 4121-4 designated first, second, third and fourth frequency counters. Figures from 4122-1 to 4122-4 designated first, second, third and fourth adders. Figures from 4123-1 to 4123-4 designated first, second, third and fourth control circuits of the coincidence. Figures from 4124-1 to 4124-4 designated first, second, third and fourth triggers the fault. Figures 4125 marked the group of logical circuits, numerals 4126 4127 and marked with the code and register the admission register, respectively, and figures 4128 specified control voltage Converter in frequency.

The filter is shown in figure 4-1-3.

CHIM is shown in the figure 4-1-4, where numbers 4141 designated group of inverters, numerals 4142 - the second multiplexer, the numbers 4143 marked the second counter code frequency, numbers 4144 - �Torah frequency counter, figures 4145 marked the second comparison circuit and figures 4146 marked the second register code frequency.

MIP is shown in figure 4-2.

SIF is shown in figure 4-3. Here the numbers 431-1, 431-2, and 431-3 denote the first, second and third pulse generators. Figures 432-1, 432-2 and 432-3 designated first, second, and third units of the phasing and numbers 433 designated block of majoritatea.

GI is shown in figure 4-3-1, where numbers 4311 marked inverters, numerals 4312, the first multiplexer, the numbers 4313 marked the first counter code frequency, number 4314 designated by the first frequency counter, numerals 4315 - the first comparison circuit and figures 4316 marked the first register code frequency.

Unit phasing is shown in figure 4-3-2. Here the numbers 4320-marked element And digits 4321 and 4322 denote the counter on dynamic triggers and the shift register. Figures 4323 designated decoder, numbers 4324 4325 and marked, respectively, a trigger stop and a trigger start. Figures 4326 marked majoritarian element, numerals 4327 - triggers binding and figures from 4328-1 to 4328-f marked triggers shapers.

The communication unit shown in figure 5, where the numbers marked 50 processor, numerals 51 - storage device, numerals 52 and 53 denote the coding-decoding device and the receiving-transmitting device.

DWI leads�Yong in figure 6, where the numerals are designated 60 and 61, respectively, the sensing element of the sensor and the signal generator.

The sensitive element of DWI is shown in figure 6-1.

Signal generator is shown in figure 7, where the numbers 70 marked AlMg, numerals 71-timed counter, numerals 72 marked timer decoder, numerals 73 marked with a trigger lock, numerals 74 and 75, designated respectively the register code and decoder code and figures 76 designated logical element.

Dynamic trigger is shown in figure 8.

SUSD shown in figure 9, where the numerals 91-1 and 91-2 are marked non-volatile storage devices, numerals 92-1 and 92-2 are marked adders timestamps and numbers 93-1 and 93-2 marked adders arrays.

Neuromechanical can be implemented as follows:

All digital nodes are implemented on the basis of a set radioconnection BIS series 1825 and storage devices on the basis of the BIS series 1620 produced in the production of JSC "Angstrem", supplemented with BIS on the basis of basic matrix crystals series 1555 and 1556, manufactured ibid. SUSD is implemented on the basis mnogotselevym magnetic cores or thin cylindrical magnetic films produced in the production of the FSUE "NPOA", Ekaterinburg, which are made up of discrete elements SMPS, DWI and dynamic trigger

Neuromechanical works as follows. Before you start from OBC upper level all firmware storage device to load the firmware and "educational" factors providing the calculation of the required functions and algorithms of matrix transformations. WFP and SIF of the secondary power source are entered setpoint, corresponding to the nominal power and repetition rate of the clock. According to the results of periodic commands to the OBC test checks, which are loaded with corresponding firmware, is the determination of the actual speed of digital nodes and enter the setpoint in WFP and SIF corresponding to the maximum possible speed, which can change with changing ambient temperature and to decrease when the set of visible dose of at least 100 Krad) or increase when the initial set of doses (up to 10 Krad).

All computations once per cycle (approximately dig every 1 MS) is written to multiple identical in composition data zones SUSD, the drives which are locked against unauthorized handling. The lock is supported by the DWI signal at the time of external impact, After the impact the driver of DWI signal generates a signal to reset/start over which the transmitter moves on to in�to implement firmware restart, recorded in the permanent memory of all his LCU, using preserved in SUSD an array of the results of the last before the failure cycle calculations. Reliable array of multiple backup is selected by examining its contents according to a checksum generated for each array before you start recording in SUSD.

Thus, the introduction of the calculator unit matrix reprocessors in which each neuroprocessor, as an element of the matrix, provides a fast computation of trigonometric functions, and each block is, in fact, the original matrix into products of two matrices.

Entered after this block operating device provides a high speed when calculating the elements of the resulting matrix, whose elements are the components of the spatial vectors of the three inertial coordinate system.

Which results in the desired(no more than 1 MS) for strapdown inertial navigation system consisting SAU highly maneuverable objects the formation of the inertial system of coordinates.

Maintaining redundancy at the level of separate units of the components of the transmitter and the introduction of modes of adjustment of the values of supply voltage and repetition rate of the pulses allows to neutralize as catastrophic failures of elements of the transmitter due to normal aging(and�and) flow of heavy charged particles of space and to ensure the greatest possible performance evaluator for each interval of work by neutralizing or using to improve performance, change the performance of semiconductor elements caused by the change of environmental temperature and(or) dose effects in semiconductor materials element structures because of the action of ionizing radiation of outer space, nuclear power plants or polluted environments.

Additionally, the introduction of the restart of the computing process using stored in SUSD restartovan arrays in each cycle of computation could compensate for the malfunction of the transmitter, caused by external ionizing pulsed radiation during solar flares, the accidents of nuclear power plants and directional opposition.

All these properties of the proposed Neuromechanical allow to use it in the composition of the sins that are installed in the control system highly maneuverable space vehicles and in particular comic devices and robotic systems designed to eliminate accidents Chernobyl type or to work in engineering troops.

1. Neuromechanical containing the communication unit, the input-output of which is the entrance-exit of narrow�the numerator and the output connected to the set input of the unit and microprogrammed control, the outputs of which are connected with control inputs of all digital components of the transmitter, characterized in that its composition is introduced first and second matrix blocks neuroprocessor, through which the trunk is connected to a matrix storage device and storage device authorized access, blocking the entrance of which is connected to the output of the sensor external influence, and the communication unit outputs connected to the inputs of blocks of matrix neuroprocessor, whose outputs are connected to the operating device, the output of which is connected to the storage device, and an installation unit output is connected to a set input of the secondary power supply, exit timestamp which is connected to a temporary input storage device is authorized access, and synchronizing the outputs and power outputs of which are connected to respective inputs of other units of neuromechanical.

2. Neuromechanical according to claim 1, characterized in that the unit firmware control base register contains the opcode, base register signs, the inputs of which are the inputs of the block, a base counter base address and the register offset, set the input of each of which is ustanavochny�m input unit and their outputs form the address bus unit connected to the base firmware of the storage device, the outputs of which are outputs of the block and the complementary output of the basic firmware of the storage device is connected to the input base register offset.

3. Neuromechanical according to claim 1, characterized in that the block matrix neuroprocessor, contains nine neuroprocessor, forming a matrix of dimension 3×3, and inputs neuroprocessor are the outputs of the communication device, the input-output of which is input-output unit, and the main input / output of each of the neuroprocessor is connected to the trunk, which is the outer line of the block.

4. Neuromechanical according to claim 1, characterized in that the secondary power supply module contains a constant power and a pulse power module, power input of each of which is a power input source, the installation log which is a startup entry module DC power and the direction of the clock, three control outputs of which are connected to the corresponding inputs of a pulse power module, the output of which, as well as the outputs of the module DC power supply and clock driver outputs are pulsed, DC, timestamp and clock viholliseni.

5. Neuromechanical according to claim 1, characterized in that the communication unit contains a processor, which processor via a line connected to a connected storage device and the communication device via the highway, and the input-output processor via a coding-decoding device is connected to the input-output transceiver, trunk multiplexed input-output of which is the same input-output of the unit.

6. Neuromechanical according to claim 1, characterized in that the storage device is authorized access includes first and second non-volatile storage devices, blocking the entrance of each of which is the same input device and to the input of each drive, first and second, connected to the outputs of corresponding first and second adders timestamp, the input of each of which is an input time stamp of the device, the first input-output of each storage device connected to the bidirectional bus external connection storage device connected to its first input-output of the corresponding storage devices of the first and second arrays of adders, each of which, first and second, its second input / output connected to the second input respectively of the first and second storage device.

7. Neuromechanical according to claim 1, characterized in that the external sensor being affected by� contains the sensing element, connected the output to the input of the signal generator, whose output is the output of the sensor.

8. Neuromechanical according to claim 3, wherein said neuroprocessor contains a microprocessor, inputs and input-output of which are the inputs and the input-output neuroprocessor, and the output of the microprocessor via a buffer register connected to the set input of processing unit and microprogrammed control, the outputs of which are connected to the control inputs of other components of the neuroprocessor and n inputs connected in series tires transfer multipliers, connected the outputs to the inputs of the adder, the output of which is the output of the neuroprocessor.

9. Neuromechanical according to claim 4, characterized in that the module DC power supply contains three identical Converter, the installation inputs of which are installation input module, and the outputs connected to the control inputs of the control unit and control and through the switch off unit connected to the inputs of the alignment unit, the output of which is the output of the module connected to the additional control input of the control unit and control, control outputs which are connected to the corresponding inputs of the block off.

10. Neuromechanical according to claim 4, characterized in that a pulse power module contains three identical branches, combined with each of the Stour�n, one of which is an input, the second output, and each branch has two series-connected field effect transistors, and three input control signal is diluted so that each of them is connected to the gates of two transistors mounted in different branches, forming a sample "2 of 3".

11. Neuromechanical according to claim 4, wherein the clock driver comprises a first, second and third pulse generators, the installation inputs of which are the installation input of the shaper, and the output of each generator, first, second and third connected to the input of the block phase, respectively first, second and third, phasing the output of each of which is connected to a phasing of the two inputs of other units and phasing of the inputs of the block of majoritatea, to the clock inputs of which are connected synchronizing the outputs of blocks phase, and the outputs of the block of majoritatea are the outputs of the timestamp and clock driver.

12. Neuromechanical according to claim 7, characterized in that the sensor probe external influence designed as a blocking oscillator, to the base of the transistor which in addition to the resistor divider connected aboutnomoney diode.

13. Neuromechanical according to claim 7, characterized in that the signal generator includes a quartz arse�schy generator, connected the output to the input of the interval counter connected to the output through the interval decoder to the reset input of the trigger of the ban, the trigger input which is the input of the shaper and combined with the triggering input of the interval counter and logic element, the output of which is the output of the shaper, and a blocking input of this element is connected to the output of the block decoder, the inputs of which are connected to the outputs of the register code, the input of which is an input lock code generator.

14. Neuromechanical according to claim 8, characterized in that the processor unit and microprogrammed control processor contains a register of the opcode, the processor register signs, the inputs of which are the inputs of the block, the CPU address counter and processor register offset, the installation log which is installation input unit, and their outputs form the address bus unit, connected to the input processor firmware storage device, the outputs of which are outputs of the block and an additional output processor of the storage device is connected to the input processor of the register of mixing.

15. Neuromechanical according to claim 9, characterized in that the alignment unit contains three identical chains, combined with each of the parties, one of which is a m�is input, the second output, and in each circuit series resistor and diode, and the first output resistor is input, the second is connected to the anode of the diode, and the cathodes of diodes all circuits are combined and the output of the module.

16. Neuromechanical according to claim 9, characterized in that the Converter comprises a series-active filter, the input of which is the power input of the Converter, the transformer includes a primary winding of the breaker transistor, a rectifying diode in the secondary winding and the output filter, the output of which is the output of the Converter and is connected to the input of the voltage Converter in the frequency, connected to the output junction element, the output of which is frequency output of the Converter and is connected to the input of pulse-frequency modulator, the installation log which is the installation input of the Converter, and the output connected to the base of the transistor switch.

17. Neuromechanical according to claim 9, characterized in that the switch off unit includes three field effect transistors, the source of each of which is an input, flow - output, and each of the three input control signals connected to the gate of the corresponding transistor.

18. Neuromechanical according to claim 9, characterized in that the control unit and the control contains four frequency counter, the inputs of the first, second and third of which yavl�are frequency inputs of the block and a fourth input connected to the output of the circuit converting voltage to frequency, the inputs of which are the control and additional control input unit and the output of the first counter connected to the first inputs of the first and the third adder, a second output connected to the second input of the first adder and the first input of the third adder, and the output of the third counter connected to the second inputs of the first and the third adder, the output of the fourth counter connected to the first input of the fourth device of coincidence, to the second input of which is connected the output of the register code, the input of which is the installation input unit and combined with the input register of admission, the output of which is connected to the first inputs of the first, second and third devices match, to the second inputs of which are connected to the outputs respectively of the first, second and third adder, and the output of each device matches the first, second, third and fourth, respectively through its first, second, third and fourth triggers the error is connected to the input of the logical unit, the outputs of which are outputs of the block.

19. Neuromechanical according to claim 11, characterized in that the pulse generator comprises n series-connected inverters, whose outputs are connected to inputs of the first multiplexer, the output of which is�tsya the output of the generator and is connected to the input of the first inverter and the input of the first frequency counter, the outputs of which are connected to first inputs of the first comparison circuit, the second inputs of which are connected the outputs of the first register code frequency, and the increment and decrement outputs of the first comparison circuit connected to the corresponding inputs of the first counter code frequency, the outputs of which are connected to the control inputs of the first multiplexer, and the installation input of the first counter code frequency and the first register code frequencies are the installation input of the generator.

20. Neuromechanical according to claim 11, characterized in that the block contains an element phasing And, a first input which is the input unit, the output connected to the input of the shift register and the input of the implemented dynamic triggers the counter, outputs connected through a decoder to the trigger input of the trigger stop, the output of which is phasing the output of the block and connected to the first input element "And" and to the first input of the majority element, the output of which is connected to the trigger input start, output connected to the reset input of the trigger stop, and second and third inputs of the majority element connected to the outputs of triggers binding inputs of which are phasing inputs of the block, wherein the outputs of even and odd bits of the shift register are connected respectively to launching and dumping WMOs�am f shapers of the clock, whose outputs are clock outputs of the block.

21. Neuromechanical according to claim 16, characterized in that the pulse-frequency modulator contains a group of serially connected inverters, the outputs of which are connected to the inputs of the second multiplexer, the output of which is connected to the input of the first inverter and an output of the modulator, the input of which is the input of the second frequency counter, which outputs are connected to first inputs of the second comparison circuit, the second inputs of which are connected the outputs of the second register code frequency, and the increment and decrement outputs of the comparator circuit is connected to the corresponding inputs of the second counter code frequency, the outputs of which are connected to control the second multiplexer, with the installation input of the second counter code frequency and a second register code frequency is setup the input of the modulator.

22. Neuromechanical according to claim 16, characterized in that the filter contains a positive circuit is a diode, the anode of which is an input, the cathode output, between which and the negative rail installed low-pass capacitor, and the cathode of the diode and the negative bus in turn using their high-frequency capacitor connected to the bus of the earth.

23. Neuromechanical according to claim 20, characterized in that the dynamic trigger is implemented as a transistor amplifier, the base of transist�RA which in addition to the resistor divider connected LC circuit, the inductance of which has an operating winding and is wound on top of her counter-compensatory, the ends of which are short-circuited.



 

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