Logical element of loose comparison for inequality of two multivalued variables

FIELD: electrical engineering.

SUBSTANCE: this device comprises first and second current inputs (1) and (2), current output (3), first and second output transistors (4) and (5) with combined bases, third and fourth output transistors (6) and (7) of the conductivity type with combined bases, first reference current source (8), first current mirror (9) coupled with power supply bus (10), second current mirror (11) coupled with second said bus (12), extra current mirror (13) coupled with second power supply mirror (12), first and second extra voltage sources (14) and (15).

EFFECT: increased response.

5 dwg

 

The present invention relates to the field of computer engineering, automation, communications and can be used in various digital structures and automatic control systems, digital communications, etc.

In various analog-to-digital computing and control devices are widely used transistor cascades of transformations of the input variables (currents), implemented on the basis of current mirrors [1-14]. These functional units, for example, are used in the input stages operating signal transducers with the so-called "current feedback" [1-14], and also as an independent non-linear switches input currents without feedback circuits [9], realizing the function of converting an input current variables.

In [15], and co-author monographs present application [16-17] it is shown that a Boolean algebra is a special case of more General linear algebra, practical implementation of which in the structure calculation and logical automation devices of new generation requires the creation of special hardware components, implemented on the basis of logic with multivalued internal representation of signals, in which the equivalent of a standard logic signal is the quantum current. The claimed device relates to this type of logical elements�comrade.

The closest prototype of the claimed device is a logical unit that is presented in the patent US 5742154, fig. 1, the structure of which is present in many other patents [1-14]. It contains the first 1 and second 2 current inputs of the device current output device 3, the first 4 and second 5 output transistors with the joint bases, the third 6 and fourth 7 the output transistors of the other conductivity type with the joint bases, and the emitter of the first 4 and the third 6 output transistors are combined, and the emitters of the second 5 and 7 fourth output transistors connected to each other, the first 8 reference current, the first 9 current mirror, consistent with the first 10 bus power source, the second 11 current mirror, consistent 12 with the second bus of the power source, moreover, the collector of the third of the output transistor 6 is connected to the second input 11 of the current mirror.

A significant disadvantage of the known device is that it does not implement the comparison function for inequality of two multivalued input variables (x1x2) corresponding to multi-level values of the input currents (I1, I2. It is not possible to create a complete basis of computing machinery, operating on the principles of transformation of multivalued current signals.

The main objective of the proposed Fig�plants is to create a logical unit non-strict comparison for inequality of two multivalued variables in which the transformation of information is conducted in a multi-value output signal shape. Ultimately, this can improve performance and create the element base of computing devices operating on the principles of multivalued linear algebra [16-17].

The problem is solved in that in the logical element of non-strict comparison for inequality of two multivalued variables (Fig. 1), containing the first 1 and second 2 current inputs of the device current output device 3, the first 4 and second 5 output transistors with the joint bases, the third 6 and fourth 7 the output transistors of the other conductivity type with the joint bases, and the emitter of the first 4 and the third 6 output transistors are combined, and the emitters of the second 5 and 7 fourth output transistors connected to each other, the first 8 reference current, the first 9 current mirror, consistent with the first 10 bus power source, the second 11 current mirror, consistent 12 with the second bus of the power source, moreover, the collector of the third of the output transistor 6 is connected to the input of the second 11 current mirrors, there are new elements and connections - first 1 current input device is connected to the input of the first 9 of the current mirror, the output of which is connected to combined emitters of the first 4 and the third 6 output transistors and is connected to �which 2 current input device, the collectors of the first 4 and second 5 output transistor 10 is connected to the first bus of the power source, the second output 11 of the current mirror is connected with the joint emitters of the second 5 and 7 fourth output transistors through the first 8 reference current associated with the first 10 bus power source, the collector of the fourth 7 of the output transistor is connected to the input of the additional current mirror 13, a consistent 12 with the second bus of the power source, the output of which is connected to the output device 3, and the base of the first 4 and second 5 output transistors 14 connected to the first source of auxiliary voltage and the third 6 and fourth 7 output transistors 15 connected to the second source of auxiliary voltage.

Diagram of the known device shown in the drawing of Fig. 1. In the drawing Fig. 2 presents a diagram of the inventive device in accordance with the claims.

In the drawing Fig. 3 is a diagram studied in the environment MS the inventive device of Fig. 2 specific performance of its functional units bipolar transistors.

In the drawing Fig. 4 shows the results of computer simulation of the circuit of Fig. 3 for the case when the input multivalued current signals (x1, x2) have two levels.

In the drawing Fig. 5 shows the results of a computer model no�tion of the circuit of Fig. 3 for the case when the input multivalued current signals (x1, x2) have three levels.

The logical element non-strict comparison for inequality of two multivalued variables Fig. 2 contains the first 1 and second 2 current inputs of the device current output device 3, the first 4 and second 5 output transistors with the joint bases, the third 6 and fourth 7 the output transistors of the other conductivity type with the joint bases, and the emitter of the first 4 and the third 6 output transistors are combined, and the emitters of the second 5 and 7 fourth output transistors connected to each other, the first 8 reference current, the first 9 current mirror, consistent with the first 10 bus power source, the second 11 current mirror, consistent 12 with the second bus of the power source, moreover, the collector of the third of the output transistor 6 is connected to the second input 11 of the current mirror. First 1 current input device is connected to the input of the first 9 of the current mirror, the output of which is connected to combined emitters of the first 4 and the third 6 output transistors 2 connected to the second current input of the device, the collectors of the first 4 and second 5 output transistor 10 is connected to the first bus of the power source, the second output 11 of the current mirror is connected with the joint emitters of the second 5 and 7 fourth output transistors and through �first 8 reference current associated with the first 10 bus power source, the collector of the fourth 7 of the output transistor is connected to the input of the additional current mirror 13, a consistent 12 with the second bus of the power source, the output of which is connected to the output device 3, and the base of the first 4 and second 5 output transistors 14 connected to the first source of auxiliary voltage, and the third 6 and fourth 7 output transistors 15 connected to the second source of auxiliary voltage.

Consider the operation of the device that defines the logical fact of exceeding the values of the input variable x2the value of the input variable x1, i.e. implements a logical function is non-strict comparison of two multivalued variables x1and x2(the comparison "greater than or equal to"). The comparison function (predicate)

accepts a single value if the condition is recorded in the left part of expression (1) is performed.

Input variables are multivalued variables x1and x2in the form of quanta of current, the result is a binary variable also represent the quantum current. Since the atomicity variables not included in the expression (1), the algorithm of the device does not depend on znanosti.

Subtraction in parentheses of expression (1) is implemented as follows. Input multivalued variables x1and x2/sub> (znanosti 2 or more), in the form of quanta of current fed to the inputs of in11 and in22 the device. The variable x1in the form of quantum inflowing current is fed to the input of the first current mirror 9, is converted into an equivalent signal flowing current and is supplied to the output of the first current mirror 9. At the point of connection of the output of the first current mirror 9 and sign-in22 is subtracted quanta values of the current input variables x1-x2. A differential current is fed to the joint emitters of the transistors 4 and 6. Modes of operation of these transistors are set by the voltages of the first 14 and second 15 additional sources of stress and prevention of saturation of the transistors of the current source x1and a current mirror 11.

While the quantum value of a current input signal x1from the output of the current mirror 9 in magnitude does not exceed the current value of the current source x2the first differential current at the joint emitters of the output transistors 4 and 6 is equal to zero. In this case, the transistor 4 is open and the transistor 6 is closed. The current of the current source x1closes the supply circuit of the device through the transistor 4.

If the quantum value of a current input signal from the output of the current mirror 9 by the value will exceed the value of the current of the current source x2the first differential current at the joint emitters of wygodniejszego 4 and 6 becomes equal in magnitude to the difference of the quanta of the input current and the current of the current source x 2. In this case, the transistor 4 is closed, and the transistor 6 is opened, and the filling of the first differential current is fed through the open transistor 6 to the input of the second current mirror 11.

The rest of the circuits implements the subtraction of 1 in the expression (1) in parentheses. The unit is modeled by the second current source 8, from which is subtracted the first differential current output from the second current mirror 11, forming a second differential current.

Modes of operation of these transistors are set by the voltages of the first 14 and second 15 additional sources of stress and prevention of saturation of the transistors of the second current source 8 and an additional current mirror 13.

While the quantum value of the first differential current output from the second current mirror 11 exceeds the current value of the current source 8 second differential current at the joint emitters of the output transistors 5 and 7 are equal to zero. In this case, the transistor 5 is open and the transistor 7 is closed. The output of the second current mirror 11 is shorted to power circuit through the transistor 5.

If the quantum value of a current input signal from the output of the current mirror 9 in magnitude less than the value of the current of the second current source 8, the second differential current at the joint emitters of the output transistors 5 and 7 becomes equal in magnitude to the difference of the quanta of the first differential current and the current source� current 8. In this case, the transistor 5 is closed, and the transistor 7 is opened and the filling of the second differential current is fed through the open transistor 7 to the input of the additional current mirror 13. The resistor 18 is used to control the output current level and when using the proposed logic circuits in other devices should be removed.

As can be seen from the above description, implementation of logical functions P(x1≥x2)=here is made by forming an algebraic sum of the quanta of current and highlighting certain values of this sum of currents. All elements of this scheme are in the active mode, the alleged lack of saturation in the process of switching, which improves the overall performance of the scheme. Furthermore, the use of multivalued internal representation of signals increases the informativeness of communication lines in real circuits, which reduces their number. The use of stable values of the quanta of current, and determining the output signal by the difference of these currents provides a low dependence of device efficiency from external destabilizing factors (the deviation of the supply voltage, radiation and temperature effects, common mode noise, etc.).

Shown in the drawings Fig. 3, Fig. 4 simulation results confirm these properties of the proposed scheme.

�thus, reviewed schematic of lax logic element comparison of two k-digit variables characterized by a multivalued state of the internal signals and the signals on their current inputs and a binary signal on the current output and can be the basis of computing and control devices using multivalued linear algebra, a special case of which is a Boolean algebra.

References

1. Patent US 8159304, fig. 5.

2. Patent US No. 5977829, fig. 1.

3. Patent US No. 5789982, fig. 2.

4. Patent US No. 5140282.

5. Patent US No. 6624701, fig. 4.

6. Patent US No. 6529078.

7. Patent US No. 5734294.

8. Patent US No. 5557220.

9. Patent US No. 6624701.

10. Patent RU №2319296.

11. Patent RU №2436224.

12. Patent RU №2319296.

13. Patent RU №2321157.

14. Patent RU №2383099

15. Malyugin, V. D. Realization of Boolean functions arithmetic with polynomials // Automatics and telemechanics, 1982, No. 4. P. 84-93.

16. Chernov N. And. Fundamentals of theory of logical synthesis of the digital structures over the field of real numbers // Monograph. - Taganrog: TRTU, 2001. - 147 p.

17. Chernov N. And. Linear synthesis of the digital structures of the information processing system // tutorial Taganrog. - TRTU, 2004, 118 p.

The logical element non-strict comparison for inequality of two multivalued variables containing the first (1) and second (2) current input device, current output (3) of the device, the first (4) and (5 second) output transistors with combined bases, the third (6) and fourth (7) output transistors of the other conductivity type with the joint bases, and the emitter of the first (4) and third (6) output transistors are combined, and the emitters of the second (5) and fourth (7) output transistors are connected with each other, the first (8) reference current, the first (9) current mirror, consistent with the first (10) bus power source, the second (11) current mirror, consistent with the second (12) bus of the power source and the collector of the third (6) the output transistor is connected to the input of the second (11) current mirrors, wherein said first (1) current input device is connected to the input of the first (9) current mirrors, the output of which is connected to combined emitters of the first (4) and third (6) output transistors connected to the second (2) current input device, the collectors of the first (4) and second (5) output transistors connected to the first (10) bus power source, the output of the second (11) current mirror is connected with the joint emitters of the second (5) and fourth (7) output transistors through the first (8) reference current associated with the first (10) bus power source, the collector of the fourth (7) output transistor is connected to the input of the additional current mirror (13), agreed with the second (12) bus power source, the output of which is connected to the output (3) of the device, and �the basics first (4) and second (5) output transistors connected to the first (14) to the source of auxiliary voltage and third base (6) and fourth (7) output transistors connected to the second (15) auxiliary voltage source.



 

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