Device for error control in ethernet-based digital transmission systems

FIELD: radio engineering, communication.

SUBSTANCE: device includes a unit transmission pulse counter, a transmission control unit, a transmission memory unit, a transmission parameter determining unit, a digital transmission system, a unit reception pulse counter, a reception control unit, a reception memory unit, a reception parameter determining unit, a comparator, transmission frame analysis units and a reception frame analysis unit.

EFFECT: high reliability of detecting single and multiple errors in a variable-length Ethernet frame and detecting alternating single and multiple failures in the digital data transmission system under analysis.

3 cl, 4 dwg

 

The invention relates to radio engineering, namely to control operation of the digital systems of data transmission based on Ethernet technology.

A device Ethernet, principles of construction and operation of which are defined by the IEEE 802.3 standard. Along with syncing, first establishing a connection and separation of the medium to realize the possibility of monitoring the integrity of the frame using a 32-bit cyclic redundancy code (Cyclic Redundancy Code, CRC-32) (according to Brayer, K; Hammond, J L Jr. (December 1975). "Evaluation of error detection polynomial performance on the AUTOVON channel" in National Telecommunications Conference, New Orleans, La. Conference Record of 1: 8-21 to 8-25, New York: Institute of Electrical and Electronics Engineers, and Ross N. Wiliams / Anarchriz. All o CRC32 // Ross N. Williams).

However, this device has disadvantages:

each detected error is not necessarily an error of one bit of information;

- multiple bit errors within the block of data give only one error for the block;

- it is possible to compensate the erroneous symbols of the same sign erroneous symbols other symbol in the data block.

The closest in its technical essence to the claimed device is a device error control in digital transmission systems based on ATM technology [Patent for the invention №2408985 from 10.01.11 G.], containing the switching unit of the transmission, the counter is a single pulse transmission, the control unit PE�of Adachi, the memory block transfer, block define the parameters of the transmission, digital transmission system, the switching unit of the reception counter unit receiving pulses, the control unit of the reception, memory reception, comparator, block define the parameters of the reception, electronic key, the output of which is an information output device for error control in digital transmission systems based on ATM technology, a second input connected to the output of the comparator, a second comparator input connected to the second output of the switching unit receiving the first output of which is connected to the first input of the counter unit receiving pulses, a second input connected to a first output of the control unit of the reception the fifth output of which is connected with the third input of the switching unit receiving, a second input connected to the sixth output of the control unit receiving the second output of which is connected with the fourth input of the memory block receiving the first output of which is connected to the first input of the comparator. The fifth input of the memory block connected to receive the counter output single pulses, and first and second inputs of the memory block receiving respectively connected to first and second outputs of the block define the parameters of the reception, the first input coupled to the second output of the memory block receiving the third input of which is connected to the third output of the control unit�the office of admission, the fourth output of which is connected to the second input of the block define the parameters, and the input of the control unit connected to the second reception output check the digital transmission system, which is its output synchronization, and to a fourth input of the switching unit receiving first input coupled to a first input of an electronic key and a first output check the digital transmission system, a data input, a second input which is the input of the synchronization and is connected to the input of the control unit of the transmission, with the fifth input of the block Association, with the fourth input of the switching unit of the transmission and to the input of a frequency synchronization device for error control in digital transmission systems based on ATM technology, and the first input of the check the digital transmission system is connected to the output of block associations, a second input connected to a first output of the memory block transmission, the second output of which is connected to the first input of the block define the parameters of the transmission, a second input connected to the fourth output of the control unit of the transmission, the second and third outputs of which are connected respectively with the fourth and third inputs of the block of memory transmission, the first input of which is connected to a first output unit determining transmission parameters, the second output of which is connected to the second input of the block �Amati transmission, the fifth input of which is connected to the output of the counter unit of the transmit pulses, a second input connected to the first output of the control unit of the transfer, seventh and eighth outputs of which are connected respectively to the fourth and the third input of the block Association, and the fifth and sixth outputs connected respectively to the third and second inputs of the switching unit of the transmission, the output of which is connected to the first input of the counter unit of the transmit pulses and the first input of the switching unit of the transmission is connected to an information input device for error control in digital transmission systems based on ATM technology and to the first input of the block Association.

In this design, the prototype device can detect perelivayuschiesya single and multiple failures.

However, this device has disadvantages:

- suitable for networks with architecture point-to-point;

the inability of the analysis frames of variable length.

The object of the invention is: development of a device for the detection of single and multiple errors in the Ethernet frame of variable length, condition monitoring check the digital transmission system given the different architecture and the discovery in it alternating single and multiple failures.

To solve the problem of the invention in the known device control oshie�OK in digital transmission systems based on ATM technology, contains the count of a single pulse transmission, the control unit transmitting the memory block transfer, block define the parameters of the transmission, digital transmission system, the counter unit receiving pulses, the control unit of the reception, memory reception, comparator, block define the parameters of reception, inputs of the blocks of the analysis frame transmission and the block analysis of frame reception, the first output of which is an information output of the digital transmission system, and a second output connected to the first input of the counter unit pulse reception, third, and fourth outputs and the third and fourth inputs connected respectively to the third, the second inputs, to the sixth and fifth outputs of the control unit receiving, second and third outputs of which are connected respectively with the fourth and third inputs of the memory block receiving the fourth output of the control unit receiving connected to the second input of the block define the parameters of reception, and the first output to the second input of the counter unit receiving pulses, the output of which is connected to the fifth input of the memory block receiving the second output of which is connected to the first input of the block define the parameters of reception, and the first and second inputs of the memory block receiving respectively connected to first and second outputs of the block define the parameters of the reception the first output of the memory block connected to receive the first�at the comparator input, the second input of which is connected to the fifth output of the analysis frame, and the output of the comparator is connected to the fourth input of the control unit receiving first input coupled to the second input unit of analysis of the frame reception and the second output of the digital transmission system, the first input of which is connected to a first output unit of analysis of frame transmission, and the second input to the first input of the control unit of the transmission, to the input clock and to the second input unit of analysis of frame transmission, the first input coupled to an information input device for error control in digital transmission systems based on Ethernet technology, third, the fourth output, the fourth and fifth inputs of the unit of analysis frame transmission connected respectively to the third, the second inputs of the fifth, sixth outputs of the control unit of the transmission, the first output of which is connected to the second input of the counter unit of the transmit pulses and the second and third outputs connected respectively to the fourth and third inputs of the memory block transfer, fourth, seventh and eighth outputs of the control unit of the transmission are connected respectively to the second, fourth and third inputs of the block determine the parameters of the transmission, first and second outputs and the first input of the block define the parameters of the transmission are connected respectively to the first, the second inputs and the second you�ode to the memory block transfer, the first output of which is a data bus and connected to the third input unit of analysis of frame transmission, the second output of which is connected to the first input of the counter unit of the transmit pulses, the output of which is connected to the fifth input of the memory block transfer.

The analysis of the level of technology has allowed to establish that the analogues, characterized by a set of attributes, identical to all features of the claimed device for error control in digital transmission systems based on Ethernet technology, absent, therefore, the invention meets the condition of patentability "Novelty".

Search results known solutions in this and related areas of technology with the purpose of revealing of signs consistent with the distinctive features of the prototype features of the claimed invention, have shown that they do not follow explicitly from the prior art. Of certain of applicant's prior art revealed no known effect provided the essential features of the claimed invention on the achievement of specified technical result. Therefore, the claimed invention meets the condition of patentability "Inventive step".

The stated object of the invention is illustrated by drawings on which is shown:

Fig. 1 is a structural diagram of a device for error control in digital systems �eredeti based on Ethernet technology;

Fig. 2 - structural diagram of the frame analysis of the transfer;

Fig. 3 - structural diagram of the block define the parameters of the transfer;

Fig. 4 - block diagram of the analysis frame reception.

Device error control in digital transmission systems based on Ethernet technology, shown in Fig. 1, consists of a frame analysis of the transmission 1, the counter unit pulse transmission 2, the control unit of the transmission 3, the memory block transfer 4, block define the parameters of the transmission 5, a digital transmission system 6, the unit of analysis frame reception 7, counter unit pulse receiving 8, the control unit receiving 9, the memory block 10, a comparator 11, block define the parameters of the reception 12. The first output unit of analysis of frame reception 7 is an information output of the digital transmission system (local area network) 6, and a second output connected to the first input of the counter unit pulse receiving 8, the third and fourth outputs and the third and fourth inputs connected respectively to the third, the second inputs of the sixth and fifth outputs of the control unit receiving 9, second and third outputs of which are connected respectively with the fourth and third inputs of the memory block 10, the fourth output of the control unit receiving 9 connected to the second input of the block define the parameters of receive 12, and the first output to the second input of the counter unit impul�owls receiving 8, whose output is connected to the fifth input of the memory block 10, the second output of which is connected to the first input of the block define the parameters of the intake 12 and the first and second inputs of the memory block 10 are connected respectively with the first and second outputs of the block define the parameters of the admission 12, the first output of the block memory 10 connected to the first input of the comparator 11, a second input connected to the fifth output of the unit frame analysis of the reception of 7, the output of the comparator 11 is connected to the fourth input of the control unit receiving 9, first input coupled to the second input unit of analysis of frame reception 7 and the second output of the digital transmission system 6, the first input of which is connected to a first output of the block frame analysis of the transmission 1 and the second input to the first input of the control unit of the transmission 3, to the input clock and to the second input unit of analysis of frame transmission 1, the first input coupled to an information input device for error control in digital transmission systems based on Ethernet technology, third, fourth outputs, fourth and fifth inputs of the unit of analysis frame transmission 1 is connected respectively to the third, the second inputs of the fifth, sixth outputs of the control unit of the transmission 3, the first output of which is connected to the second input of the counter unit pulse transmission 2, and the second and third outputs connected respectively�tstone to the fourth and third inputs of the memory block transfer 4, the fourth, seventh and eighth outputs of the control unit of the transmission 3 are connected respectively to the second, fourth and third inputs of the block determine the parameters of the transmission 5, the first, second and outputs the first input of the block define the parameters of the transmission 5 is connected respectively to the first, second inputs and the second output of the memory block of the transmission 4, the first output of which is a data bus and connected to the third input of the block frame analysis of the transmission 1, the second output of which is connected to the first input of the counter unit pulse transmission 2, the output of which is connected to the fifth input of the memory block transfer 4.

The unit of analysis of transmission-frame 1 (Fig. 2) is designed to drop from the Ethernet frame preamble, start delimiter of a frame (Start-of-frame-delimiter), field checksum (Frame Check Sequence, FCS), separation of header and data block for subsequent analysis. The unit of analysis frame transmission includes a timer 9.6 µs 1.1, the shift register 1.2, e-1.3 key element And 1.4, D-flip-flop 1.5, counter to one hundred twenty-eight 1.6, counter unit intervals 1.7, a divide-by-eight 1.8, which is the third output of the unit of analysis frame transmission 1. The third input of the divider-by-eight 1.8 connected to the fifth input of the unit of analysis of transmission-frame 1 and to the fourth input of the counter unit intervals 1.7, the third input catalogobject to the second input of the counter to one hundred twenty-eight 1.6, to the first input of the electronic key 1.3, to the second input unit of analysis of transmission-frame 1 and to the second input of the timer 9.6 µs 1.1, the output of which is connected to the first input of the counter unit time intervals, a second input of divide-by-eight 1.8, the second input of D-flip-flop 1.5 and with the third input of the shift register 1.2, the first, second and fourth outputs, the input of which is connected respectively to first and second outputs and to the third input of the unit of analysis frame transmission 1, the fourth output of which is connected to the output of D-flip-flop 1.5, and the fourth input to the second input of the electronic key 1.3, the output of which is connected to the second input of the shift register 1.2, first input of which is connected to the first input of the timer 9.6 µs 1.1 and to the first input unit of analysis of transmission-frame 1, and the third and fourth outputs of the shift register 1.2 connected respectively to the second and the first input element And 1.4, the output of which is connected to the first input of D-flip-flop with 1.5 and the first input of the counter to one hundred twenty-eight 1.6, the output of which is connected to the second input of the counter unit time intervals, 1.7, the output of which is connected to the first input of the divider-by-eight, the output of which is connected with the third output block frame transmission 1.

Counter single pulse transmission 2 and the counter unit receiving pulses 8 are identical and are designed to determine the number of Edenic�'s characters in each j-th of n six-digit segments of the selected sequences N(1) jand display of this number in binary code.

The control unit of the transmission 3 and the control unit receiving 9 are identical and are designed to generate control signals to implement the desired algorithm for signal conversion and can be implemented on a microcontroller from Atmel AT 89S8253.

The unit of memory transmission 4 and the memory block 10 are identical and are designed for memorizing the values of the number of individual characters in each j-th of n six-digit segments, and also values of the truncation parameters Y and K analyzed data field of the Ethernet frame, storage and issuance of any required values in the appropriate unit determination of the parameters of the transmission 5 and the block define the parameters of the reception 12. As a memory block can be used the device on the memory chip CRU [Korneychuk V. I., Tarasenko V. P. Computing devices on chips: a Handbook. K.: Engineering, 1988. S. 85-87].

The definition block transfer parameters 5 (Fig. 3) and the definition block of the receive settings 12 are identical and are designed to determine the values of parameters of the information sequences: mathematical expectation m(1), the variance d(1), the probability of occurrence of a single symbol p(1), and also values of the truncation parameters Y and K. Structural diagram of the block define the parameters of the transmission 5 (Fig. 3) and the block of determining the parameters of acquisition of 12-comp�it from visitarla 5.1, 5.11, 5.13, adders 5.3, 5.6, 5.8, 5.2 multiplier, dividers 5.4, 5.5, 5.7, 5.9, 5.10, 5.12, the shift register 5.14, encoders 5.15, 5.16.

The first input of the block define the parameters connected to the inputs A of the shift register 5.14 and adder 5.3, the output of which is connected with its input and to the input of the divider And 5.4, the output of which is connected to the input of the divider 5.5, to the input of the subtracter And 5.11, to the inputs of the subtracter In 5.8 and adder 5.1. The input A of the adder 5.1 is connected to the output of the shift register 5.14, and the output of the adder 5.1 connected in parallel to the inputs A and b of the multiplier 5.2, the output of which is connected to the input A of the adder 5.6. The output of the adder connected to 5.6 to his entrance and to the input of the divider And 5.7, the output of which is connected to the inputs And dividers 5.10 and 5.9, the output of which is connected to the input A of the adder 5.8, the output of which is connected to the input of the divider 5.12. The output of the divider 5.12 connected to the input A of the encoder 5.16, whose output is the second output unit determining the parameters 5, the first output of which is connected to the output of the encoder 5.15, the input of which is connected to the output of the subtracter 5.11, the entrance To which is connected to the output of the divider 5.10, the entrance To which is connected to the output of the subtracter 5.13, the input of which is connected to the second input of the block define the parameters 5. The entrance To the subtractor 5.13 connected to the input divider In 5.9 and with the output of the divider 5.5. The third input of the block define the parameters 5 is connected to the inputs � dividers 5.4 and 5.7 and the input From the adder 5.6. The fourth input of the block define the parameters 5 is connected to the inputs of encoders In 5.15, 5.16 shift registers 5.14 and input From the adder 5.3.

The unit of analysis frame reception 7 (Fig. 4) contains a timer 9.6 µs 7.1, the memory control 7.2, the shift register 7.3, 7.4 electronic key, element And 7.5 D 7.6 trigger, count to one hundred twenty-eight 7.7, the counter unit intervals of 7.8, a divide-by-eight 7.9, whose output is the third output of the unit of analysis frame reception 7, the third input of the divider-by-eight 7.9 connected to the fourth input of the unit of analysis frame reception 7 and to the fourth input of the counter unit intervals 7.8, the third input of which is connected to the second input of the counter to one hundred twenty-eight 7.7, to the first input of the electronic key 7.4, to the second input unit of analysis of the frame 7 and reception to the second input of the timer 9.6 µs 7.1, the output of which is connected: to a first input of the counter unit intervals 7.8, to the second input of the divider-by-eight 7.9, to the second input of D-flip-flop 7.6 and to a first input of the memory block control 7.2, the output of which is connected to the fifth output of the unit frame analysis of the transmission 7, and the second input of the memory block control 7.2 is connected to the fifth output of the shift register 7.3, the first and second outputs of which are connected respectively to the first and second outputs of the block of the analysis frame reception 7, the fourth output of which is connected to the output flip-flop 7.6, and the third input to the second input of the electronic key 7.4, the output of which is connected to the second input of the shift register 7.3, the first input of the shift register 7.3 connected to the first input of the timer 9.6 µs 7.1 and to the first input unit of analysis of frame reception 7, and the third and fourth outputs of the shift register 7.3 connected respectively to the second and the first input element And 7.5, the output of which is connected to the first input of D-flip-flop 7.6 and with the first input of the counter to one hundred twenty-eight 7.7, the output of which is connected to the second input of the counter unit intervals 7.8, the output of which is connected to the first input of the divider-by-eight 7.9.

The comparator 11 is designed to compare the values of the truncation parameters Y and K, calculated in block define the parameters of 12, with the values of Υ0and Κ0calculated in the block define the parameters of the transmission 5 and the decision about the presence or absence of error in a received Ethernet frame.

The claimed device error control in digital transmission systems is as follows.

The first step involves the determination of the values of the truncation parameters K0, Y0information bytes of the Ethernet frame and replace on the transmission side of a digital transmission system for these values of the checksum bytes of the current frame.

For admission to the first input unit of analysis of frame transmission cadre Ethernet (preamble, includes seven clock bytes 01010101) output (Reset) of the timer 9.6 μs 1.1 a signal of logical "0" is supplied to the third input of the shift register 1.2 (1-12272), thereby allowing him entry. The appearance sequence of the start delimiter of a frame (Start-of-frame-delimiter, SFD 10101011) at the output of the element And 1.4 a signal of logical "1" input to the first input of the counter to one hundred twenty-eight 1.6, starting it up and driving D-flip-flop 1.5 in "1" state, entering its first input, the fourth output unit of analysis of frame transmission 1 will signal the "Start of frame" (logical "1") supplied to the second input of the control device 3. Counter up to one hundred twenty-eight 1.6 upon completion of readout of 128 clock pulses generates a signal "Start account" (logical "1") coming from its output to the second input of the counter unit intervals 1.7. Counter single time interval 1.7 begins to count the number of unit time intervals of the clock pulses received at a third input.

At the end of the frame at the first input of 9.6 μs timer 1.1 the signal is lost and after a time interval of 9.6 μs at its output will be logic "1" which, by doing:

- to the third input of the shift register 1.2, relieves from 1 to 96 and 113 of 128 bits of information from the end of the packet (96 - a sequence of zeros, for�scientists over the last 9.6 μs and 16 32-bit field checksum (Frame Check Sequence, FCS) contained at the end of the Ethernet frame);

- at the first input of the counter unit intervals 1.7, stopping him.

As a result, 129 cell of the shift register 1.2 on the second output unit of analysis of transmission-frame 1 is formed by a sequence of pulses of the Ethernet frame without the checksum, input to the first input of the counter unit pulse transmission 2. On the fourth output unit of analysis of frame 1 will signal the end of the frame (logical "0") supplied to the second input of the control unit of the transmission 3. On command from the sixth output of the control unit of the transmission 3 to the fifth input of the unit of analysis frame 1 stops the count value of the sync interval counter unit intervals 1.7 and dividing this number by the divisor to eight 1.8, and on coming to the team from the fifth output of the control unit of the transmission 3 to the fourth input unit of analysis of transmission-frame 1 stops clocking of the shift register 1.2. From the output of the divide-by-eight 1.8 (third output of the analysis frame transmission 1) to the third input of the control unit of the transmission 3 is fed the value of N required to calculate crop values.

When receiving the fourth output unit of analysis of the frame transfer 1 signal "Start of frame" to the second input of the control unit of the transmission 3, it generates a control signal "Load" coming from �pervogo output of the control unit of the transmission 3 to the second input of 8-bit counter unit pulse transmission 2. Counter single pulse transmission 2 starts counting the number S(1) a unit of "1" s in each 8-metragem segment. After receiving each 8-th character is read out of the counter values of a single pulse transmission 1.7 by supplying a control signal "address Code" from the third output of the control unit of the transmission 3 to the third input of the memory block of the transmission 4 when the signal "Record", coming from the second output of the control unit of the transmission 3, to the fourth input of the unit of memory transmission 4. The values of Sj(1) the numbers "1", represented in binary code, the output of the counter unit pulse transmission 2 receives the fifth input of the memory block of the transmission 4, which is its information D input, and in accordance with the code combination of the address X is the input (the third input) and control the Z-input (the fourth entry) is the entry values of Sjin the appropriate cells of the memory block of the transmission 4. After that we reset the counter unit pulse transmission 2 by the signal "Clean" at its second input.

Concurrently with entering into the block of memory transmission 4 values of the numbers "1" Sjin the definition block transfer parameters 5 the computation of values of mathematical expectation mj(1) and dispersion (dj(1) the number "1" in 8-bit segment and the probability pj(1) the appearance of "1" in the j-th position 8razryadnogo segment, and by results of calculation of mj(1), dj(1), pj(1) determine the values of the truncation parameters K0, Y0.

From the second output of the memory block transfer 4 is a sequence of readout values of S1j. These values served to the first input of adder 5.3 and the input of the shift register 5.14 block define the parameters of the transmission 5, shown in Fig. 3. In the adder 5.3 is the summation of all j-x values of S1jselected N 8-bit segments by summing each of the j-th value of S1jwith the sum of the previous, coming from the output of the adder 5.3 at its second input:j=1NS1j. When applied to the first input of the adder 5.3 N-th value of S1jand obtain at its output the total value of individual characters of S1in selected N 8-bit segments of the value read.

The output signal of the adder 5.3 is applied to the input of the divider 5.4 with a division ratio of N, whose value comes from the eighth output of the control unit of the transmission 3. In the divider 5.4 is a division by the number N, i.e. the computation of the average value:m1=[ j=1NS1j]/N.

The value of m1from the output of the divider 5.4 is fed to a first input of the divider 5.5, the second input of subtractor 5.1, the second input of adder 5.8 and the first input of the subtractor 5.11. In the divider 5.5 with a constant division ratio of the operation is performed dividing by the number 8, i.e. the computation of the probability p1the appearance of "1" at each position in the 8-bit segments:p1=[j=1NS1j]/N×8. A value of p1served her a second input of the subtracter 5.13 and the second input of the divider 5.9. In the subtractor 5.13, a first input of which is fed the number "one" is represented in binary code, calculation: 1-p1.

The value 1-p1is read out and is supplied to the second input of the second divider.

After calculating the values of m1and feeding it to the second input of the subtracter 5.1 the computation of the variance of d1. From the output of the shift register 5.14, the delay time which is determined by the time neo�needed to calculate the value of m 1produced consistent readings j-x values of S1jselected N 8-bit segments and feed these values to a first input of the subtracter 5.1. In the subtractor 5.1 calculates the difference of S1j-m1.

The output signal of the subtractor 5.1 is fed to first and second inputs of the multiplier 5.2, in which the computation of [S1j-m1]2the result of which is fed to a first input of the adder 5.6.

After that is cleared of the subtracter 5.1 and 5.2 multiplier.

In the adder 5.6, the system adds the difference [S1j-m1]2N times by adding each value of [S1j-m1]2to the sum of the previous, coming from the output of the adder 5.6 at its second input. When applied to the first input of the adder 5.6 N-value [S1j-m1]2and perform calculations total values ofj=1N[S1j-m1]2it reads this value from the output of the adder 5.6 to the input of the divider 5.7 and zeroing of the second adder 5.6.

In the divider 5.7 with a division ratio of N the computation of the variance: d1=j=1N[S1j-m1]2/N. After calculating the d1it reads the values of d1applied to the first inputs of the dividers 5.9 and 5.10. To the second input of the divider 5.9 served a probability value of p1. In the divider 5.9 the computation of the relations of d1/p1the result of which is fed to a first input of the third adder 5.8.

In the adder 5.8, on a second input filed value m1, calculation of values of m1+d1/p1.

The result of the summation is input to the divider 5.12, in which the computation and quantization of the truncation parameter K0=(m1+d1/p1)/8. After calculating and quantizing it reads the values of K0and feed this value to the input of the encoder 5.16, where we convert the values of K0in the eight-bit binary code. From the output of the encoder 5.16 the value of K0supplied to the second output unit determining transmission parameters 5 and further to the second input of the memory block transfer 4, in which are recorded the values of K0

In parallel to calculate the value of K0the computation of the value of the parameter Y0. To the second input of the divider 5.10 is set to 1-p1and at its first input the value of d1. In the divider 5.10 the computation of the relations of d1/(1-p1), the result of which is fed to the second input of the subtracter 5.11. In the subtractor 5.11, a first input of which is filed value m1, calculation and quantization parameter truncation of Y0=m1-d1/(1-p1). After calculating and quantizing it reads the values of Y0and feed this value to the input of the encoder 5.15, where a value of Y0converted to eight-bit binary code. From the output of the encoder 5.15 the value of Y0routed to the first output of the block define the parameters of the transmission 5 and further to a first input of the memory block of the transmission 4, which is writing the values of Y0in the corresponding memory cell. From the first output of the memory block of the transmission 4 is read eight-digit binary values of the truncation parameters K0, Y0to the third input of the unit of analysis frame transmission 1, which records the cells of the shift register 97 through 112. Further resets all values in the elements of the block define the parameters of the transmission 5 to the teams from the seventh output of the control unit of the transmission 3, pic�Upaya to the fourth input of the block define the parameters of the transmission 5. Then on command from the fifth output of the control unit of the transmission 3 to the fourth input of the unit of analysis frame transmission resumes 1 clocking of the shift register 1.2, and the modified Ethernet frame from the first output unit of analysis of frame transmission 1 is supplied to a first input of a digital transmission system 6.

In the second stage of operation of the device for error control in digital transmission systems based on Ethernet technology is the determination of the values of the truncation parameters K, Y information bytes of the Ethernet frame, taken with a digital transmission system 6, the selection of values of the truncation parameters K0, Y0the information bytes in the received Ethernet frame and a decision about the presence or absence of errors.

Adopted by the information pulse sequence of the Ethernet frame (preamble, seven clock bytes 01010101) from the first output of the digital transmission system 6 is supplied to the first input unit of analysis of frame reception 7. At the output of the timer 7.1 9.6 μs appears a logic "0", thereby setting the memory block control reception 7.2, D-flip-flop 7.6, the counter unit time intervals 7.8, a divide-by-eight 7.9 in original condition and allowing the entry in the shift register 7.3 (1-12240). The appearance sequence of the start delimiter of a frame (Start-of-frame-delimiter, SFD 10101011) at the output of the element And 7.5 a signal of logical "", runs counter to one hundred twenty-eight 7.7 and transforming the D-flip-flop 7.6 in the state "1" at the fourth output unit of analysis of frame reception 7 appears the signal "Start of frame" (logical "1"). Counter up to one hundred twenty-eight 7.7 at the conclusion of the account will generate the signal "Start account" (logical "1") to the second input of the counter unit intervals 7.8. The counter unit intervals 7.8 begins to count the number of unit intervals.

At the end of the frame at the first input of timer 7.1 9.6 μs the signal is lost and after a time interval of 9.6 μs at its output will be logic "1" which: is the entry from the shift register 7.3 values of the last two bytes of the Ethernet frame in a memory unit of the control receiving 7.2; stops the counter unit intervals 7.8 and are divided by a divider-by-eight 7.9. As a result, the second output unit of analysis of the frame receiving a sequence of pulses of the Ethernet frame without the checksum, which is supplied to a first input of a pulse counter receiving 8, which is its data input. On the fourth output unit of analysis of frame reception 7 is formed a signal of the end of frame is supplied to the second input of the control unit receiving 9. From the third output of the analysis frame reception 7 to the third input of the control unit receiving 9 is fed the value of N, the necessary�th to calculate crop values.

The principle of operation of the block define the parameters of the admission 12, the memory block 10, a counter unit receiving pulses 8 are identical to the principle of operation of the block define the parameters of the transmission 5, the memory block of the transmission 4, the counter unit pulse transmission 2, which are discussed above.

In the comparator 11 compares the values of the truncation parameters K0, Y0calculated for the information of bytes transmitted Ethernet frame, with the values of the truncation parameters K, Υ, is calculated for the information bytes of a received Ethernet frame.

As a result of comparison output of the comparator 11 when the coincidence cropping parameters to generate a signal "0" and when the mismatch signal "1" which is input to the control unit receiving 9. Upon receipt of the signal "0" to the fourth input of the control unit receiving 9, the sixth output of which is formed the team resume clocking of the shift register 7.3 supplied to the third input of the unit of analysis frame reception 7, and the information sequence is fed to the first output unit of analysis of frame reception 7, which is an information output device for error control in digital transmission systems based on Ethernet technology. In the case of the fourth input of the control unit receiving 9 signal "1" of the received Ethernet frame is discarded as an accepted error.

WMOs�the above in the overall structure of the device for error control in digital transmission systems based on Ethernet technology elements are generic and can be technically implemented at present when using the hardware base.

Schemes counters are known and can be implemented on the chip CIE [Shyla V. L. Popular digital circuits". - M.: Radio and communication, 1987. S. 235-236, Fig. 2.36, a].

Used in the claimed device elements AND the shift register can be made on chips and K155LA3 chip CIR.

Scheme of adders and visitarla can be implemented, for example, on a chip KIP [Batashev VA, Veniaminov V. N. and other Circuits and their applications: a reference guide. - M.: Radio and communication, 1983. Pp. 129-130].

The multiplier circuit can be implemented on the chip KIP [Batashev VA, Veniaminov V. N. and other Circuits and their applications: a reference guide. - M.: Radio and communication, 1983. Pp. 129-130].

The divider circuit can be implemented on chips K155IE8, CIE [Shyla V. L. Popular digital circuits. - M.: Radio and communication, 1987. P. 94-97, Fig. 1.69].

Diagram of the encoder can be implemented on the chip CMIV [Shyla V. L. Popular digital circuits. - M.: Radio and communication, 1987. P. 140-142, Fig. 1.101].

The electronic circuit of the key is known and described, for example, in the book: B. L. Shiloh. "Popular chip CMOS. Guide." - M.: Jaguar, 1993, p. 22.

The comparator circuit can be implemented on the chip CSP [Shyla V. L. Popular digital circuits. - M.: Radio and communication, 1987. C. 183-184, Fig. 1.134].

Diagram of the timer 9.6 μs can be realized at mikros�EME NE 555.

Diagram of D-flip-flop can be implemented on the chip KTM.

The meter circuit unit time intervals can be implemented on the chip CIE.

Thanks to the new essential features in the claimed device error control in digital transmission systems based on Ethernet technology are achieved detection of single and multiple errors in the Ethernet frame of variable length, and condition monitoring check the local network of a different architecture and discovery in it alternating single and multiple failures.

1. Device error control in digital transmission systems based on ATM technology, containing the counter is a single pulse transmission, the control unit transmitting the memory block transfer, block define the parameters of the transmission, digital transmission system, the counter unit receiving pulses, the control unit receiving the memory block, and the block determining parameters for receiving and comparator, characterized in that the device additionally introduced the units of analysis of frame transmission and the block analysis of frame reception, the first output of which is an information output device, a second output connected to the first input of the counter unit pulse reception, third, fourth outputs and the third and fourth inputs connected respectively to the third, the second input, W�stoma and the fifth output of the control unit of the reception the second and third output of which is connected respectively with the fourth and third input of the memory block receiving the fourth output of the control unit receiving connected to the second input of the block define the parameters of reception, and the first output to the second input of the counter unit receiving pulses, the output of which is connected to the fifth input of the memory block receiving the second output of which is connected to a first input and the first and second inputs respectively from the first and second outputs of the block define the parameters of admission, the first output of the memory block connected to receive the first input of the comparator, a second input connected to the fifth output of the unit frame analysis of reception, and the output - with the fourth input of the control unit receiving the first input coupled with the second output of the digital transmission system and a second input unit of analysis of frame reception, the first input coupled to the first output of the digital transmission system, the first input of which is connected to a first output unit of analysis of frame transmission, and the second input to the first input of the control unit of the transmission, to the input clock and to the second input unit of analysis of frame transmission, the first input coupled to an information input device for error control in digital transmission systems based on Ethernet technology, third, the fourth and outputs of the fourth and fifth inputs of the block frame analysis p�of transmission are connected respectively with the third, the second inputs of the fifth, sixth outputs of the control unit of the transmission, the first output of which is connected to the second input of the counter unit of the transmit pulses, the second and third outputs connected respectively to the fourth and the third input of the memory block transfer, and the fourth, seventh, and eighth outputs connected respectively to the second, fourth and the third input of the block define the parameters of the transmission, first and second outputs and the first input of the block define the parameters of the transmission are connected respectively to the first and the second input and second output of the block memory transfer, its first output, which is the bus data line, connected to the third input unit of analysis of frame transmission, the second output of which is connected to the first input of the counter unit of the transmit pulses, the output of which is connected to the fifth input of the memory block transfer.

2. Device error control in digital transmission systems based on ATM technology according to claim 1, containing a block of the analysis frame transmission, which consists of a timer 9.6 μs, of the shift register, an electronic key of the element And D-flip-flop, the counter 128, the counter unit time intervals, the frequency divider 8, the output of which is the third output of the unit of analysis frame transmission, a third input connected to the fifth input of the unit of analysis frame transmission and to the fourth input of the counter unit interval�fishing time the third input of which is connected to the second input of the counter to 128, to the first input of the electronic key, the second input unit of analysis of frame transmission and to the second input of the timer 9.6 μs, the output of which is connected to the first input of the counter unit time intervals, a second input of the divider 8, the second input of D-flip-flop and a third input of the shift register, the first, second and fourth outputs, the input of which is connected respectively to first and second outputs and to the third input unit of analysis of frame transmission, the fourth output of which is connected to the output of D-flip-flop, and the fourth input to the second input of the electronic key, the output of which is connected to the second input of the shift register, the first input of the shift register connected to the first input of the timer 9.6 μs and to the first input unit of analysis of frame transmission, and the third and fourth outputs of the shift register are connected respectively to the second and the first input element And whose output is connected to the first input of D-flip-flop and to a first input of the counter 128, the output of which is coupled to a second input of the counter unit time intervals, the output of which is connected to the first input of the divider by 8.

3. Device error control in digital transmission systems based on ATM technology according to claim 1, containing a block of frame analysis method, which consists of a timer 9.6 μs, of the memory block control, registracija, electronic key, item, And D-flip-flop, the counter 128, the counter unit time intervals, the frequency divider 8, the output of which is the third output of the unit of analysis of frame reception, the third input of the frequency divider 8 is connected to the fourth input of the unit frame analysis of the reception and to the fourth input of the counter unit time intervals, the third input of which is connected to the second input of the counter to 128, to the first input of the electronic key, the second input unit of analysis of frame reception and to the second input of the timer 9.6 μs, the output of which is connected to the first input of the counter unit intervals, to the second input of the divider 8, to the second input of D-flip-flop and to a first input of the memory block control, the output of which is connected to the fifth output of the unit of analysis frame transmission, and the second input is connected to the fifth output of the shift register, the first and second outputs of which are connected respectively to the first and second outputs of the unit of analysis of frame reception, the fourth output of which is connected to the output of D-flip-flop, and a third input to the second input of the electronic key, the output of which is connected to the second input of the shift register, the first input of the shift register connected to the first input of the timer 9.6 μs and to the first input unit of analysis of the frame, and third and fourth outputs connected respectively to the second and the first input element And the output of which is soy�inen with the first input of D-flip-flop and to a first input of the counter 128, the output of which is connected to the second input of the counter unit time intervals, the output of which is connected to the first input of the frequency divider 8.



 

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FIELD: radio engineering, communication.

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4 cl

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