Neural network number-to-frequency converter

FIELD: electricity.

SUBSTANCE: device contains two adders, two "OR" elements, two delay elements, counter, decoder, code memory, four "AND" elements, weight coefficient memory unit, training unit, memory unit for weight coefficients, training unit, multiplier, activation function selection unit.

EFFECT: implementation of various functional relations of output frequency and input code, and improvement of ability of the converter to adjust a multiplicative component of errors of sensors.

2 tbl, 1 dwg

 

The invention relates to automatic control and computer engineering, in particular to devices nonlinear transformation code in the frequency, and can be used in computer and control complexes as non-linear code Converter in the frequency that combines the function of a transformation of the form of presentation of information with its mathematical processing on nonlinear dependencies.

The closest set of features and the technical nature of the claimed device is a neural code Converter in the frequency (patent RF №2420804, IPC G06N 99/00, 2009), which provides for the formation of the output frequency proportional to the input code; containing a counter, decoder, memory codes, the four elements "And" two element "OR" two delay elements, two adder, the digital outputs of the counter are connected through a decoder with inputs memory codes the outputs of the memory codes are connected through the first and second elements And the first inputs of the first and second elements OR, respectively, the second inputs of the first and second elements OR connected through the third and fourth elements And respectively to the first input digital code of the device, the second frequency input device connected to the input of the first element And through the first delay element to the input of the third element And, o is on the first element OR is connected to the first summing input of the first adder, the output of the first adder is connected to the second carry-in input of the second adder, the output of the second adder connected to the input of the second element And through the second delay element to the input of the fourth NAND gate, the output of the second element OR is connected to the first input of the second adder, the output of the second adder connected to the input of the counter, the output of transfer which is output device, characterized in that the Converter typed memory block weights and unit training, the input data of a unit of study connected to the input of the test sequence, the address input of the memory block weights connected to the bus SA addresses the weights of a unit of study, the information input of the memory block weights connected to the SD bus data weighting coefficients of a unit of study, the enable input write memory block weights connected to the output recording resolution we teaching block, the outputs w1 and w2 of the memory block weighting coefficients respectively connected with the second inputs of the first and second adders, which specifies the mode of operation of the adders (adders can operate in the following modes summation and subtraction), the outputs vi(i=1, 2, ..., k) and ui(i=1, 2, ..., k) of the memory block weights connected with the third input buses of the first and second adders, specifying the touch value, used in the operations of summation and subtraction, the output si(i=1, 2, ..., k) of the memory block weights are connected to the inputs of memory codes.

The disadvantages of the prototype is its limited functionality, namely circuit-structurally you can use in a single cycle conversion of different activation functions of the neurons in the network Converter to implement a wide range of functional dependencies of the output frequency from the input code and correction multiplicative component of the error sensors, so as activation functions are used only fractional-rational function with two tuning coefficients.

The technical result of the present invention is aimed at expanding the functionality and improving the ability of the Converter to adjust the multiplicative component of the error sensors, namely the implementation of various functional dependences of the output frequency from the input code, which is reached at the expense of use in one cycle of the conversion of different types of activation functions of the neurons in the network Converter and by introducing a third of the adjustment coefficient in the rational approximating functions. Use the block selecting activation allows you to use the AMB in one cycle of converting different types of activation functions of the neurons in the network Converter, running in different cycles of transformation, which allows to extend the range of reproducible functional dependencies. The use of the multiplier allows to introduce a third adjustment coefficient in the rational approximating functions to improve the ability of the Converter to adjust the multiplicative component of the error sensors.

The technical result is achieved by the code Converter in the frequency containing the counter, decoder, memory codes, the four elements "And" two element "OR" two delay elements, two adder, a memory unit weights and unit training, the input data of a unit of study connected to the input of the test sequence, the address input of the memory block weights connected to the bus SA addresses the weights of a unit of study, the information input of the memory block weights connected to the SD bus data weighting coefficients teaching block, the enable input write memory block weights connected to the output recording resolution we teaching block, the outputs vi(i=1, 2, ..., k) and ui(i=1, 2, ..., k) of the memory block weights connected with the third input buses of the first and second adders, sets the initial value to be used in the operations of summation and subtraction, the output si(i=1, 2, ... k) block of memory the weights connected with the first group of inputs of memory codes group digital outputs of the counter are connected through the decoder with the second group of inputs of memory codes, the third and first outputs of the memory codes are connected through the first and second elements And the first inputs of the first and second elements OR, respectively, the second input of the first element OR is connected via the third element And to the first input digital code of the device, the second input of the second element "OR" coupled to the output of the fourth element "And", the second frequency input device connected to the input of the first element And through the first delay element to the input of the third NAND gate, the output of the first element OR is connected to the first summing input of the first adder, the output of the first adder is connected to the second carry-in input of the second adder, the output of the second adder connected to the input of the second element And through the second delay element to the input of the fourth NAND gate, the output of the second element OR is connected to the first input of the second adder, the output of the second adder connected to the input of the counter, the output of the transport which is output device.

enter the multiplier and the block selection function is activated, the inputs of the multiplier is connected to the first input digital code of the device and with the second output of the memory block codes, the output of the multiplier is connected to the input of the fourth element And the fourth output memory the systems connected to the input of the block selecting activation, outputs w1and w2block selecting activation respectively connected with the second inputs of the first and second adders, which specifies the mode of operation of the adders (adders can operate in the following modes summation and subtraction).

In Fig.1 shows a structural diagram of the device.

Neural network code Converter in the frequency contains the first adder 1, the second adder 2, the first element "OR" 3, the second element "OR" 4, the first delay element 5, the second delay element 6, a counter 7, a decoder 8, a memory 9 codes, the first element And 10, the second element "And" 11, the third element And 12, the fourth element "And" 13, the input reference frequency F014, the input is converted code Nx15, the output of the output frequency Fy16, the memory unit weights 17, the education block 18, the input test sequence 19, bus SA 20 addresses the weights of a unit of study, the SD bus 21 data weighting coefficients teaching block, the output recording resolution we 22 teaching block, a multiplier 23, the block selecting activation 24.

The multiplier 23 performs the multiplication operation codes NxandNciwith the resultant codeNxc=N xNci. The tube 23 has two digital inputs and one digital output.

The first adder 1 implements the operation of summation codes NxcandNbiconverting the amount in the frequency ofFi=F0Nxc+Nbi2k(summation mode) orFi=F0V-(Nxc+Nbi)2k- (subtraction), representing a sequence of pulses overflow at the output of the first adder 1 formed by transferring the input codesNbiand Nxcwith frequency F0(k is the number of bits of the adder). The first adder 1 is the tsya an integral part of the artificial neural network of the Converter. The weighting factor w1supplied to the second input of the first adder 1, specifies the type of operation: sum (w1=1) or subtract (w1=0). The value V is supplied to the third input bus of the first adder 1, sets the range of the summation/subtraction (0≤V<2k).

The first adder 1 has a first summing input, a second control input that defines the type of operation (summation or subtraction), the third input bus, sets the initial value of the sum and the output of the transport.

The second adder 2 operates on the principle of deploying structures. Forming at its output period

in the subtraction mode is done by a linear scan codeNWith aM2(t)in the second adder 2 from the initial number, equal to the sum of(Nx+Nai)from the beginning of the periodTziuntil the overflow of the second adder 2. Linear scan code NWith aM2(t)is achieved when the second adder 2 in the counting mode, when at its counting input pulses of a frequency Fi. In summation mode of the second adder 2 outputs its period

The second adder 2 has a first summing input, a second control input that defines the type of operation (summation or subtraction), the third input bus, sets the initial value of the sum and the output of the transfer. The second adder 2 is an integral part of the artificial neural network of the Converter.

The first element "OR" 3 and the second element "OR" 4 have two logic inputs and one Boolean output.

First 10, second 11, the third 12 and fourth 13 elements And have two logic inputs and one Boolean output.

The counter 7 has an input resolution of account, the group of digital outputs and the output transfer. From the output of the transfer counter 7 is removed, the output frequency Fy16.

The decoder 8 is a group of digital inputs and digital outputs.

The code memory 9 has a group of digital inputs and digital outputs and is intended for intermediate storage of digital coefficientsNa i,NbiandNciand codeNfaifunction activation.

The memory block weights 17 has an address input bus, the data bus and the input recording resolution, and outputs the coefficients that define the weight ui(i=1, 2, ... k) and vi(i=1, 2, ... k) synaptic connections of the first and second adders.

Education block 18 is intended for training of the neural network block definition interval on the implementation of the desired function splits the input frequency on its ranges.

Education block 18 has an input test sequence, the output address bus output data bus and the output of the write-enable.

The block selecting activation 24 is designed to switch the type of operations performed first and the second adders (summation and subtraction) on the basis of the codeNfaifunction activation.

The block selecting activation 24 is about is in digital input code Nfaiactivation and two logical output wi(i=1, 2), with which the switch type of operation they perform the first and second adders (summation and subtraction).

Neural network code Converter in the frequency contains a counter 7, a decoder 8, a memory 9 codes, the first element And 10, the second element "And" 11, the third element And 12, the fourth element "And" 13, the first delay element 5, the second delay element 6, a memory unit weights 17, the education block 18, the first adder 1, the second adder 2, the first element "OR" 3, the second element "OR" 4, the first input digital code of the device 15, the second frequency input device 14, the output device 16, the input test pattern 19, the SA bus 20 address of weights, the SD bus 21 data weighting coefficients, the output recording resolution we 22, a multiplier 23, the block selecting activation 24. Group digital outputs of the counter 7 is connected through the decoder 8 to the inputs of the memory 9 codes. The first and third outputs of the memory codes 9 is connected through the first element "And" 10 and the second element "And" 11 with the first inputs of the first element "OR" 3 and the second element, OR 4, respectively. The second input of the first element "OR" 3 is connected via the third element "And" 12 to the first input of the digital to the Yes N xdevice 15. The second input of the second element "OR" 4 is connected to the output of the multiplier 23. The inputs of the multiplier 23 is connected to the first input digital code of Nxdevice 15 and to the second output of the memory block 9 codes. The fourth output memory codes 9 is connected to the input of the block selecting activation 24. Outputs w1and w2block selecting activation 24 are connected respectively to the second input of the first adder 1 and the second input of the second adder 2. The second frequency input F0the device 14 is connected to the input of the first element And 3 and through the first delay element 5 to the input of the third element "And" 12. The output of the first element "OR" 3 is connected to the first summing input of the first adder 1. The output of the first adder 1 is connected with the second carry-in input of the second adder 2. The output of the second adder 2 is connected to the input of the second element And 11 and through the second delay element 6 to the input of the fourth element "And" 13. The output of the second element "OR" 4 is connected to the first input of the second adder 2. The output of the second adder 2 is connected to the input of the counter 7, the output of transfer which is output device. The input data of a unit of study 18 connected to the input test sequence 19. The address input of the memory block weights 17 is connected to the SA bus 20 address weighting coefficients teaching block 18. The information shall include the input of the memory block weights 17 is connected to the SD bus 21 data weighting coefficients teaching block 18. The enable input write memory block weights 17 is connected to the output recording resolution we 22 teaching block 18. Outputs w1and w2block selecting activation 24 is connected with the second inputs of the first adder 1 and the second adder 2, respectively, defines the type of the function is activated by setting the operation modes of the adders. The first adder 1 and the second adder 2 can operate in the following modes summation and subtraction. The outputs of the vi(i=1, 2, ..., k) and ui(i=1, 2, ..., k) of the memory block weights 17 are connected with the third input buses of the first adder 1 and the second adder 2, respectively, sets the initial value to be used in the operations of summation and subtraction. The outputs of the si(i=1, 2, ..., k) of the memory block weights 17 are connected with the inputs of the memory 9 codes.

Neural network definition block interval is as follows.

To implement the non-linear dependence of the conversion of the neural code Converter in the frequency should be trained in using teaching block 18. Training is carried out by feeding the test sequence 19. The test sequence consists of sequentially supplied input code Nx15 and corresponding values of the output frequency Fy16. The volume of the test sequence affect the ability of learning. The more test sequence, the better the learning device for the implementation according to the output frequency Fy16 from the input code, Nx15.

Education block 18 may be implemented, for example, on the external or internal expansion card for a personal computer.

When applying the test sequence 19 to the input of a unit of study 18 operation begins training. Upon completion of the operation instruction writes new values of the weights and thresholds of the neurons in the memory unit weights 17. For this input to confirm the write memory block weights 17 from the output we 22 teaching block 18 is supplied value we=1. On the input address bus of the memory block weights 17 output SA 20 teaching block 18 is supplied address of a corresponding weighting factor. The data bus SD 21 is fed the value of the weighting factor.

The input device receives an input code Nxand the reference frequency F0.

The formation of the amounts ofNx+NaiandNxc+Nbi( Nxc=Nx+Nci)in the first adder 1 and the second adder 2, respectively, occurs when the supply of the pulse reference frequency F0and pulse overflow of the second adder 2. Code Nxserved in the first 1 and second 2 adders with some delay τC<T0, the duration of which is provided by the delay elements 5 and 6. The resulting frequency Fzremoved from the counter 7.

The described neural network Converter belongs to the class of hybrid computing devices with discrete-managed options (including using digital weights of the artificial neural network), using the principle of multiple use pulse-digital decisive elements included in the operational unit. The control sequence of the individual operations performed by the counter 7 and the decoder 8.

Operational block simulating each i-th step (i=1, 2, ..., n) is a simple fraction of the form (x+ai)/(x·ci+bi), consists of a series connection of a linear transducers (cont'd) code-frequency (N→F) and code-period (N→T). Converter N→F" is built on the basis of the first adder 1, d is lisowska the operation of summation codes Nxc=NxNciandNbiwith the conversion of the sum/difference in frequency

(summation mode) or

(subtract mode) representing a sequence of pulses overflow at the output of the first adder 1 formed by transferring the input codesNbiand Nxcwith frequency F0(k is the number of bits of the adder). The first adder 1 is an integral part of the artificial neural network of the Converter. The weighting factor w1supplied to the second input of the first adder 1, specifies the type of operation: sum (w1=1) or subtract (w1=0). The value V is supplied to the third input bus of the first adder 1, sets the range of the summation/subtraction (0≤V<2k).

PR N→T" is built on the basis of the second adder 2 and works on the principle of unfolding structures. Forming at its output period

mode is subtraction (weighting factor w 2=0, and the weighting factor 0≤U<2kspecifies the border) is done by a linear scan codeNWith aM2(t)in the second adder 2 from the initial number, equal to the sum of(Nx+Nai)from the beginning of the periodTziuntil the overflow of the second adder 2. Linear scan codeNWith aM2(t)is achieved when the second adder 2 in the counting mode, when at its counting input pulses of a frequency Fi. Therefore, taking into account (1) the expression (3) in the summation mode of the first adder 1 and subtracting the second adder 2 takes the form:

At the time of formation of the pulse period endTzithe counter 7 changes yet its state and by decoder 8 connects from memory codes 9 through the elements "And" 10 and 11 to the elements "OR" 3 and 4 codes Nai+1andNbi+1respectively, and connects to the multiplier 23 codeNci+1.

Given the possible combinations of modes of operation (modes summation and subtraction) of the first and second adders 1 and 2, the Converter implements a functional relationship by its approximation by using approximating functions are presented in table 1. Approximating functions are activated neuronal network of the Converter.

Table 1
Types of approximating functions
No.Control signalsThe type of approximating function
1w1=0, w2=0
2w1=1, w2=0
3w1=0, w2=1
4w1=1, w2=1

The formation of the next periodTzi+1similar to the previous one. The forming cycle is one period Tzthe output frequency Fzequal to n cycles, the number of which is specified by the conversion factor of the counter 7. In addition, the counter 7 produces coherent summation periodsTziforming at its output the total period equal to

Thus the resulting frequency Fzon the neural network output of the Converter respectively

To implement the non-linear dependence of the neural code Converter in the frequency should be trained in using teaching block 18. Training is carried out by feeding the test sequence 19. The test sequence consists of a series podawa the number of values of the input code, N x15 and corresponding values of the output frequency Fy16. The test sequences are shown in table 2. The volume of the test sequence affects the accuracy of learning. The more test sequence, the better the learning device for the implementation according to the output frequency Fy16 from the input code, Nx15.

Table 2
The example test sequence for training the neural network of a code Converter in a frequency
The value of the input code, NxThe value of the output frequency Fy
11111.924 MHz
11101.898 MHz
11011.871 MHz
11001.841 MHz
10111.808 MHz
10101.772 MHz
10011.732 MHz
10001.688 MHz
0111 1.64 MHz
01101.586 MHz
01011.524 MHz
01001.455 MHz
00111.376 MHz
00101.285 MHz
00011.178 MHz
00001.052 MHz

When applying the test sequence 19 to the input of a unit of study 18 operation begins training. Upon completion of the operation instruction writes new values of the weights and thresholds of the neurons in the memory unit weights 17. For this input to confirm the write memory block weights 17 from the output we 22 teaching block 18 is supplied value we=1. On the input address bus of the memory block weights 17 output SA 20 teaching block 18 is supplied address of a corresponding weighting factor. The data bus SD 21 is fed the value of the weighting factor.

Thus, the application of the proposed neural network of a code Converter in the frequency allows you to extend the functionality, namely to expand the range of reproducible function is optional dependencies when implementing functional transformation of the input code in the frequency and improve the ability of the Converter to adjust the multiplicative component of the error sensors.

Neural network code Converter in the frequency containing the counter, decoder, memory codes, the four elements "And" two element "OR" two delay elements, two adder, a memory unit weights and unit training, the input data of a unit of study connected to the input of the test sequence, the address input of the memory block weights connected to the bus SA addresses the weights of a unit of study, the information input of the memory block weights connected to the SD bus data weighting coefficients of a unit of study, the enable input write memory block weights connected to the output recording resolution we teaching block, the outputs of the vi(i=1, 2, ..., k) and ui(i=1, 2, ... k) of the memory block weights connected with the third input buses of the first and second adders, sets the initial value to be used in the operations of summation and subtraction, the output si(i=1, 2, ..., l) of the memory block weights connected with the first group of inputs of memory codes, the group of digital outputs of the counter are connected through the decoder with the second group of inputs of memory codes, the third and first outputs of the memory codes are connected through the first and second elements And the first inputs of the first is the first and the second element OR, respectively, the second input of the first element OR is connected via the third element And to the first input digital code of the device, the second input of the second element "OR" coupled to the output of the fourth element And the second frequency input device connected to the input of the first element And through the first delay element to the input of the third NAND gate, the output of the first element OR is connected to the first summing input of the first adder, the output of the first adder is connected to the second carry-in input of the second adder, the output of the second adder connected to the input of the second element And through the second delay element to the input of the fourth NAND gate, the output of the second element OR is connected to the first input of the second adder, the output of the second adder connected to the input of the counter, the output of transfer which is output device, characterized in that the Converter introduced the multiplier and the block selection function is activated, the inputs of the multiplier is connected to the first input digital code of the device and with the second output of the memory block codes, the output of the multiplier is connected to the input of the fourth element "And", the fourth output memory codes connected to the input of the block selecting activation, outputs w1and w2block selecting activation respectively connected with the second inputs of the first and second adders, specifying the mode of robotisation (adders can operate in the following modes summation and subtraction).



 

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5 cl, 5 dwg

FIELD: physics.

SUBSTANCE: method comprises steps for: obtaining seismic data for an area of interest; obtaining an initial seismic cube using said seismic data, wherein the initial seismic cube is a three-dimensional representation of the seismic data; generating a plurality of shifted seismic cubes within the area of interest using said seismic data and a shifting parameter, wherein each of the plurality of shifted seismic cubes is shifted from the initial seismic cube; and wherein the shifting parameter defines a direction and a range that the initial seismic cube should be shifted; generating a neural network using the initial seismic cube, the plurality of shifted seismic cubes, and well log data; and applying the neural network to said seismic data to obtain a model for the area of interest, the model being configured for use in adjusting an operation of the wellsite.

EFFECT: high accuracy.

20 cl, 19 dwg

FIELD: information technology.

SUBSTANCE: in an ophthalmic-microsurgical computer local area network for vitreoretinal operations, formatting devices are in form of a radial-annular structure consisting of a single set of automated workstations (AWS), which synchronously or asynchronously functioning, processing, converting, transmitting, analysing, synthesising hierarchical structures of an artificial neural network: diagnosis AWS (DAWS), ophthalmic-microsurgical AWS (OMAWS), subsequent operation stages AWS (SOSAWS), component AWS (CAWS), surgeon's operating unit (SOUAWS), with opposite forward and reverse flow of information in between, where each AWS has at least one neural circuit, interconnected identification units (IU), an interpolation unit (INU), an extrapolation unit (EU), which are the neural network converting and transmitting elements (NNCTE), a decision unit (DU), which is the neural network analysis and synthesis element (NNASE).

EFFECT: simultaneous improvement of accuracy of determination and quality of identifying diagnoses, determining indications for conducting operations, high selectivity when conducting operations, accuracy in determining the sequence of operations, simulating operations, accuracy in choosing the anaesthetic method, accuracy of providing implants and expendable materials, optimisation of flow of information and necessities during vitreoretinal ophthalmic-microsurgical operations.

1 dwg

FIELD: physics.

SUBSTANCE: neuron simulation method is based on calculation of squares of Euclidean distance from the input vector to each of 2n vertices of a unit n-dimensional cube in weighting units, and multiplication of values inverse to these distance values with components of the target vector respectively, and then summation in an adder and conversion in the activation unit through an activation function.

EFFECT: possibility of simulating a neuron of any given Boolean function from a complete set of from n variables.

6 dwg, 1 tbl

FIELD: information technology.

SUBSTANCE: multilayer modular computer system has several layers, including a neural network layer, a transport layer and a processor layer, wherein the transport layer contains network controller-router modules, the processor layer contains processor modules, and all the said modules have multiple inputs and outputs connected to each other and connected to the inputs and outputs of the system. The processor modules train neural network domain modules.

EFFECT: high decision speed, possibility of grafting layers and modules in each layer during operation of the system with a complex task, high reliability of the computer system.

3 cl, 1 dwg

FIELD: information technologies.

SUBSTANCE: invention may be used for building of modular neural computers, which function in symmetrical system of residual classes. Stated neuron network comprises unit of neuron network of end ring of senior coefficient generation for generalised positional system of numeration, unit of polarity shift, unit of error detection, buses "with errors" and "without errors".

EFFECT: reduced hardware complexity.

3 dwg

FIELD: physics; computer engineering.

SUBSTANCE: present invention pertains to neurocomputers. The device has a unit for storing a binary input signal, a logic AND-OR circuit, internal memory unit, unit for generating the output string of codes, a generator of synchronising pulses, control unit, a unit for selecting duration and extracting information, analysis block and a corrector unit.

EFFECT: increased rate of operation, providing for the possibility of distinguishing change in state of processed signals, increased noise immunity, possibility of making super-complex neural networks, and simplification of design.

9 cl, 1 dwg

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