Image recognition device

FIELD: radio engineering, communication.

SUBSTANCE: image recognition device contains a multichannel switch, an ADC, a marker associativity coefficient memory unit, a logical AND unit, a shift register unit, a control unit, a logical OR element, an address register, an address selection memory unit, a buffer register.

EFFECT: device performance improvement.

4 dwg, 4 tbl

 

The invention relates to automation and computer engineering and is intended for use in automatic pattern recognition, in particular for the recognition of States of complex objects for some values of their parameters.

A device for pattern recognition (RF patent for the invention №2306605, publ. 20.09.2007, BI No. 26), used to identify States of interest by the values of their parameters, which in its technical essence is the closest to the proposed device. This device contains a multi-line switchboard, information the input of which is connected to the information input device, an analog-to-digital Converter, an information input of which is connected to the output of the multi-channel switch, the address counter, a memory block whose address inputs of the least significant bits are connected to the output of the analog-to-digital Converter, and the address inputs high-order bits of the memory block connected to the outputs of the address counter to the address inputs of the multi-channel switch, the unit logic elements And in which the first and second inputs of the logic elements And connected to the respective first and second inputs of the logical elements And the outputs of logic elements And outputs are unit logic elements And the unit shift registers, in which the information inputs of the first shift register connected to the corresponding information input unit shift registers, the shift inputs of shift registers connected to the corresponding lateral inputs of the unit shift registers, and the outputs of the last shift register connected to the outputs of the unit shift registers, control unit, first, second, third and fourth outputs of which are connected respectively to the control inputs of the counter address of the memory block, the second input of the logic element And to the control input of the analog-to-digital Converter, and the control unit is a control input device, the outputs of the memory block is connected directly to the corresponding information input unit shift registers and to the respective first inputs of the logical elements And the outputs of which are connected to the corresponding shear unit shift registers whose outputs are the outputs of the device.

The disadvantage of this device prototype is poor performance, due to the constant cycle of recognition, the duration of which is proportional to the number of signs n.

The technical result of the present invention is to improve the performance of the device.

To achieve results in the recognition device containing a multi-line switchboard, information the input of which is connected to inform the operating inputs of the indication device, analog-to-digital Converter, an information input of which is connected to the output of the multi-channel switch count address high-order bits, the memory block of coefficients associativity of signs, whose address inputs of the least significant bits are connected to the output of the analog-to-digital Converter, and the address inputs high-order bits of the memory block of coefficients associativity signs connected to the outputs of the counter address high-order bits and the address inputs of the multi-channel switch, the unit logic elements And in which the first and second inputs of the logic elements And connected to the respective first and second inputs of the logical elements And the outputs of logic elements And are the outputs of the logical elements, And the unit shift registers in which information inputs of the first shift register connected to the corresponding information input unit shift registers, the shift inputs of shift registers connected to the corresponding lateral inputs of the unit shift registers, control unit, first, second, third and fourth outputs of which are connected respectively to the counting input of the counter address high-order bits, to the control input of the conversion memory block of coefficients associativity of signs, to the second input of the logical elements stored the And and to the control input of the analog-to-digital Converter, a first control unit connected to the control input of the outputs of the memory block of coefficients associativity signs connected directly to the corresponding information input unit shift registers and to the respective first inputs of logical block elements And whose outputs are connected to the corresponding lateral inputs of the unit shift registers further include a logic element OR an address register, the memory block selection address and the buffer register, and the outputs of the address register is connected to the address inputs of the high-order bits of the memory block selection addresses, the address inputs of the least significant bits of which are connected to the outputs of the unit shift registers, all outputs of the memory block selection address are connected to the inputs buffer register, and the outputs of the least significant bits of the memory block selection address corresponding to the address of the next sign, also connected to the address inputs of the multi-channel switch and to the address inputs of the high-order bits of the memory block of coefficients associativity characteristics, the control input of buffer register connected to the control input of the analog-to-digital Converter and to the fourth output control unit, and outputs a buffer register connected to the inputs of the address register, the fault input of which is connected to the fault input of the block is dugovich registers and to the fifth output control unit, and the control input of the address register connected to the second input of the logic elements And to the third output of the control unit, the first output of which is connected to the control input of the memory block address selection, all the outputs of the shift registers are connected to the outputs of the unit shift registers, and fault inputs of all shift registers are combined and connected to the fault input of the shift register, the outputs of the last digits of which are the outputs of the device and connected to the inputs of a logic gate OR the output of which is connected to the second control input of the control unit.

In Fig.1 shows a structural diagram of the device of Fig.2 is a structural diagram of the logical elements And the unit shift registers of Fig.3 to explain the operation principle of the proposed device and as an example implementation of a control unit, presents a structural diagram of the control unit of Fig.4 is a timing chart of a signal at its output.

The device comprises a multi-channel switch 1, the logical element OR 2, the address register 3, an analog-to-digital Converter 4, the control unit 5, the memory block selection address 6, the memory block of coefficients associativity signs 7, block of logic elements And 8, the buffer register 9, the unit shift register 10, and the information the data inputs multi-channel switch 1 is connected to the information input characteristics of the device, information input analog-to-digital Converter 4 is connected to the multichannel output of the switch 1, the address inputs of the least significant bits of the memory block of coefficients associativity signs 7 is connected to the output of the analog-to-digital Converter 4, and the address inputs high-order bits of the memory block of coefficients associativity signs 7 is connected to the address inputs of the multi-channel switch 1 and outputs the youngest of information bits of the memory block selection address 6, all the outputs of which are connected to the inputs of the buffer register 9, the outputs of which are connected to the inputs of the address register 3, the outputs of which are connected to the address inputs of the high-order bits of the memory block selection address 6 and address inputs younger bits of the memory block selection address 6 is connected to the outputs of the unit shift registers 10, where the information inputs of the first shift register 12 is connected to the corresponding information input unit shift registers 10, shift inputs of shift register 12 is connected to the corresponding lateral inputs of the unit shift register 10, the information input of which is connected to the outputs of the memory block of coefficients associativity signs 7 and to the respective first inputs of logical block elements And 8, in which the first and second inputs of the logic elements And 11 Conn is obtained to the respective first and second inputs of logical block elements And 8, the outputs of logic elements And 11 are the outputs of the logical elements And 8, the outputs of which are connected to the corresponding lateral inputs of the unit shift registers 10, all outputs of the shift register 12 is connected to the outputs of the unit shift register 10, and fault inputs of all shift registers 12 are United and connected to the fault input of the shift register 10, the outputs of the last digits of which are the outputs of the device and connected to the inputs of a logic gate OR 2, the output of which is connected to the second control input of the control unit 5, the first, second, third, fourth and fifth outputs of which are connected respectively to the control inputs of the blocks memory address selection 6 and the coefficients of associativity signs 7, to the second input of the logic elements And 8 and the control input of the address register 3, to the control inputs of analog-to-digital Converter 4 and the buffer register 9 to the vertical inputs of the address register 3 and unit shift registers 10.

Unit logic elements And 8, as shown in Fig.2, contains the logical elements And 11, the number of which is equal to the number of recognized classes of k images, and the first inputs of the logic elements And 11 through the input unit logic elements And 8 are connected to the corresponding information input unit shear the case is 10 and to the respective outputs Q 1-Qkmemory block coefficients associativity signs 7, where Q1corresponds to the low order data word of the memory block of coefficients associativity signs 6, a Qksenior category. The second inputs of the logic elements And 11 of block logic elements And 8 are connected to the joint second unit logic elements And 8 and to the third control output of the control unit 5, and outputs of logic elements And 11 of block logic elements And 8 through the respective outputs of the block of logic elements And 8 are connected to the corresponding lateral inputs of the unit shift registers 10.

The unit shift register 10, as shown in Fig.2, as in the known device, contains the k m-bit shift registers 12, where m corresponds to the threshold of recognition, and information inputs of the first discharge, shear and combined waste inputs shift register 12 is connected to the corresponding information, shear and fault inputs of the unit shift register 10, and all outputs of the shift register 12 is connected to the outputs of the unit shift registers 10. Below the threshold of detection in the proposed device the same way as in the known device, refers to the minimum number of positive tests m the membership values of the checked characteristics of a certain class education is, upon reaching a decision toiletries scanned the combination of features of a given class of images. This term is widely used in scientific and technical literature, for example in the work of Kozlov, Y. M. "Adaptation and learning in robotics" (M.: Nauka, 1990) on page 221, and the article Thelen, A., Kogan, A. and others "identity. How it's done" (magazine "Computer", No. 10, 1999).

The control unit, as shown in Fig.3, contains the logical element AND-NOT 13, delay element 14, the trigger start / stop 15, the clock 16, the logical elements 17, 18, block the formation and distribution of control signals, the logical element OR 20, and the first input of the logical element AND-NOT 13 connected to the first input of the control unit 5, and the output of the logical element AND-NOT 13 connected to the fifth output control unit 5 and to the installation log trigger start / stop 15, the fault input of which is connected to the output of logic element OR 20, the first trigger output start / stop 15 is connected to the first input of the logical element And 17, and the inverted output trigger start / stop 15 is connected to the input of the delay element, the output of which is connected to the second input of the logical element AND-NOT 13, the second input of logic element And 17 connected to the output of clock 16 and p is pout to the input of logic element And 18, the second input is connected to the second input of the control unit 5, the output of the logic element And 17 are connected to the input of the control unit and the distribution of control signals 19, the first, second, third, fourth and fifth outputs of which are connected respectively to the first, fourth, second, and third outputs of the control unit 5 and to the first input of logic element OR 20, the second input is connected to the output of the logical element And 18.

In Fig.4 timing diagrams "a", "b", "c", "d", "e", "f", "g", "h" and "k" represent the processes of formation and receipt of signals respectively from the output of clock 16, the control input device, the output of the logical element AND-NOT 13, the output of logic element And 17, at the first, second, third, fourth and fifth outputs of the block of formation and distribution of control signals 19.

The proposed device operates as follows.

The start device is fed to the control input of the control unit 5 of a start signal, which resets the address register 3 and all shift registers 12 of the unit shift registers 10. According to the combined address generated from the code at the output of the address register 3 and code at the output of shift register 10, the signal is read, coming from the first output control unit 5 to the control input is Loka memory address selection 6, address code of the first sign is supplied with the outputs of the least significant bits of the memory block selection address 6 to the inputs of the buffer register 9, the address inputs multi-channel switch 1 and the high-order bits of the address of the memory block of coefficients associativity signs 7 to select the first information channel device and select the appropriate page of the memory block of coefficients associativity signs 7. Next, the control signal from the fourth output control unit 5 to the control inputs of analog-to-digital Converter 4 and the buffer register 9, the information input from the output of the memory block selection address 6 in the buffer register 9 and the conversion of the analog signal of the first characteristic into a digital code, which is supplied with outputs of analog-to-digital Converter 4 to the address inputs of the least significant bits of the memory block of coefficients associativity signs 7. According to the combined address generated from the code addresses a characteristic of the output youngest of information bits of the memory block selection address 6 and the digital code output from the analog-to-digital Converter 4, the signal read from the second output control unit 5 to the control input of the memory block of coefficients associativity signs 7, class codes of the images corresponding to the digital value of the first at the Naka come to the information inputs of the unit shift registers 10 and the first unit logic elements And 8. Next to the control input of the address register 3 and the integrated second input unit logic elements And 8 from the third output control unit 5 receives the control signal entered to the address register 3 and the signal recording-shift for shift registers 12 of the unit shift register 10, the information inputs of the first places which has a single code received from the memory block coefficients associativity signs 7. The signal recording-shift on the shift input of shift register 12 is formed by a logical element And 11 of block logic elements And 8 when the match is at its inputs a single code from a memory block of coefficients associativity signs 7 and the signal from the third output control unit 5. On a signal recording-shift single class codes images via the data inputs of the first shift register 12 of the unit shift registers 10 are entered into the shift registers 12. In this case, the number of each shift register 12 of the unit shift registers 10 represents the number of information digits of the memory block of coefficients associativity signs 7, starting at the LSB, and accordingly the number of classes of images. This completes the procedure I check the value of the first sign on the line for all classes of images. Further, similar in overall address generated from the code at the output of the address register 3 and code situation at the output of shift register 10, the signal is read, coming from the first output control unit 5 to the control input of the memory block selection address 6, the composite code that contains the address of the next and previous sign of recognition comes from the output of the memory block selection address 6 on all inputs buffer register 9. Moreover, the code output from the least significant bits of the memory block selection address 6 corresponding to the address of the next sign, was also fed to the address inputs of the multi-channel switch 1 and the high-order bits of the address of the memory block of coefficients associativity signs 7 to select the next information channel device and select the appropriate page of the memory block of coefficients associativity signs 7. The signals of the control unit 5 through a multichannel switch 1 to the information channel analog-to-digital Converter 4 is connected news channel that sign of recognition, whose order of priority above the rest (see table 1), and the address inputs of the senior ranks. memory block coefficients associativity signs 7 enters address code to select the appropriate page of the memory block of coefficients associativity signs 7 for values of the s and class codes selected on the basis of the priority order of sign recognition. After analog-to-digital conversion characteristic value, entry code address of the next sign in the buffer register 9 and read from a memory block of coefficients associativity signs 7 class codes images similar to the previous codes classes of images inserted into the corresponding shift registers 12 of the unit shift registers 10. When this compound code addresses of respondents and the subsequent characteristic from the output buffer register 9 will be entered into the address register 3. Identification of the class of the image produced by the final state of the last shift register 12 of the unit shift registers 10 (see Fig.2). The presence of a single code in the last bit shift register 12 of the unit shift registers 10 shows toiletries investigated signs of recognition class of images, corresponding to the sequence number of this shift register.

To illustrate the principle of the proposed device in tables 1-3 are examples of the recognition of two classes of images Q1and Q2according to the principle of "two of three".

Table 1 shows the order of priority of selection of attributes with regard to the accuracy of the set of signs to each image. In particular, the assessment of the probability that the first sign of reliable evidence about the class of images Q1, is defined as P1=.7. Accordingly, for the second and third signs: P2=0.9, and P3=0.8. For a class of images Q2estimating probabilities are respectively: P1=0.8 5, P1=0.75, P3=0.95. The binary codes of the addresses of the channels in which are recorded the signs, starting with the first, respectively: "00", "01" and "10".

Table 1
The number sign123
The reliability of the identification image characteristic for the class of Q10.70.90.8
The reliability of the identification image characteristic for the class of Q10.850.750.95
The channel address register sign000110
Order Prioritet the particular characteristics for each class of images
Q1231
Q2312
Table 2Table 3
time
discharge
t1t2time
discharge
t1t2t3
r600r6000
r500r5000
r400 r4001
r300r3000
r201r2010
r100r1001
R2200R22000
R2100R21011
R12 01R12001
R1111R11111

In tables 2 and 3 "r1" - "r6" represent the values of the bits in the register of addresses, starting with the youngest, "R11" - "R12" - value bits of the first shift register unit shift registers corresponding to the class of images Q1starting at the LSB, a "R21" - "R22", respectively, the values of the second shift register.

In the presented example we consider two variants of recognition of the image of Q1. In table 2, when the detection occurs without interruption, in table 3, when admitted failure in the second step of the recognition in favour of the class of images Q2. To consider the General case in the examples, the detection starts with the first sign. As can be seen from the examples, if the process goes smoothly, that in the proposed device, it is completed in two clock cycles. For device-prototype recognition in all cases is for three steps, that is, after checking all the signs of RA is cognition.

To illustrate the principle of the proposed device in the table 4 presents the contents of the memory block selection address. In table gray values of unused addresses for the specified sample, and the symbol "X" in the columns "a6" - "a1" signal about the need to complete the recognition process when selecting the appropriate value of the address of the memory block selection address. Cells (see columns a6 - a1 table 4) memory block selection addresses contain address information channels of the device by priority, taking into account the prehistory of the survey characteristics.

Table 4
the value of the address of the memory block selection addressthe contents of the cells of the memory block selection address
r1r5r4r3r2r1R22R21R12R11a6a5a4a3a2a1
0000000000000001
0000000001------
0000000010----- -
0000000011------
0000000100------
..............................----/td> --
0000001110------
0000001111------
000001000000 0110
0000010001000110
0000010010------
0000010011- -----
0000010100000111
0000010101000111

r6 1
Table 4
the value of the address of the memory block selection addressthe contents of the cells of the memory block selection address
r5r4r3r2r1R22R21R12R11a6a5a4a3a2a1
0000010110------
..............................---- --
0000011111------
0000100000001001
0000100001001 011
0000100010------
0000100100001011
000010010100 1001
0000100110------
..............................------
0000101111-/td> -----
0000110000001101
0000110001001110
000011001 0------
0000110100001101
0000110101001110
00001101 10------
..............................------
0000111111------
0001000/td> 000------
..............................------
0001001111------
000100000------
..............................------
0001011111------
0001/td> 100000011011
0001100001011011
0001100010------
00 01100011------
0001100100011011
0001100101011011
0 001100110------
..............................------
0001101011-----
0001101100XXXXXX
0001101101011011
0001101110---- --
0001101111011011
0001110000011110
0001110001011 110

...
Continuation of table 4
the value of the address of the memory block selection addressthe contents of the cells of the memory block selection address
r6r5r4r3r2r1R22R21R12R11a6a5a4a3a2a1
0001110010------
0 001110100011110
0001110101011110
0001110110------
0001110111011110
0001111000------
..............................----- -
0001111110------
0001111111011110
0110110000XXXX XX
0110110001XXXXXX
0110110010------
0110110011XXX XXX
0110110100XXXXXX
0110110101XXXXXX
0110110110-- ----
0110110111XXXXXX
0110111000------
..............................-/td> -----
0110111011------
0110111111XXXXXX
011110000 0XXXXXX
0111100001XXXXXX
0111100010XXXXXX
01111000 11XXXXXX
0111100100XXXXXX
0111100101XXXXXX
0111100 110------
0111100111XXXXXX
0111101000------
...........................------
0111101011------
0111101111XXXXXX
10011 10000XXXXXX
1001110001XXXXXX
1001110010------
1001 110011XXXXXX
1001110100XXXXXX
1001110101XXXXXX
100 1110110------
..............................------
1001111110------
10/td> 01111111XXXXXX

The control unit 5, a block diagram is shown in Fig.3, operates as follows.

In the initial state, the trigger start / stop 15 is reset to the first input of logic element And 17 has a negative potential, and the pulses from the output of clock 16, presented at the timing diagram "a" of Fig.4, is fed to the output of the logical element And 17. The first input of the logical element AND-NOT 13 also has a negative potential and the second input is a positive potential that is supplied with the inverted output of the trigger start / stop 15. When applying to the first input of the logical element AND-NOT 13 a start signal, which is supplied in the form of a pulse of positive polarity, represented by timing diagram "b" of Fig.4, the output of the logical element AND-NOT 13 is formed by a pulse of negative polarity as shown in the timing diagram "c" of Fig.4, the trigger vs the ka-stop 15 is switched to one state so, as shown in the timing diagram "d" of Fig.4. With the inverted output of the trigger start / stop 15 signal of negative polarity is supplied through the delay element 14 to the second input of the logical element AND-NOT 13, the output of which is formed a negative pulse of the required duration, which is supplied to the fifth output control unit 5 to reset the address register 3 and unit shift registers 10. This is depicted in timing diagram "c" of Fig.4. Further, the pulses from the output of clock 16 is fed to the input of block formation and distribution of control signals 19, which produces consistently on the first, fourth, second, and third outputs of the control unit 5 signals read from the memory block selection address 6, as shown in the timing diagram "e" of Fig.4, the trigger signal analog-to-digital Converter 4 and entering the information into the buffer register 9 shown in figure "f" in Fig.4, the signals read from the memory block coefficients associativity signs 7 shown in figure "g" in Fig.4, and the signals entering the address in the address register 3 and recording-shift data in the unit shift registers 10, shown on diagram "h" of Fig.4. When all inputs are logic element OR 20 single signal, which is formed either by the end of the scan line is the conduct of all signs of recognition at the fifth output of the power generation and distribution control signals 19, or at the output of the logical element And 18, upon receipt at its both inputs of the individual signals received from the second control input U2control unit LSI output of clock 16. Further, the outputs of the logic element OR 20 enters the fault input trigger start / stop 15 to transfer control unit 5 to its original state. This signal is represented in the diagram "k" of Fig.4 in the form of a pulse of negative polarity.

To assess the performance of the proposed device for example, devices operating on the principle of "two of three" will calculate the probability of failure of its (Rtotalwhen analysing any one of the three characteristics according to the following formula:

where P1, P2 and P3, respectively estimates of the probability of failure of the facilities of the first, second and third signs raspoznavaniya image.

If we assume that P1=0.01, P2=0.02, and P3=0.03, Ptotal=0.0578. This suggests that the percentage of operations recognition, in which you must use all three features, is approximately 6%. This means that for the given example the probability of failures in the performance of the proposed device in only 6% of the total number of operations recognition will work with the device performance of the prototype and use recognition all three signs. In the remaining 94% of the proposed device will work with increased productivity through the use of recognition of the two signs. Thus, a numerical evaluation of the performance increases will be approximately 33.3%.

The positive effect of the proposed technical solution, in comparison with the known, obtained through the use of the situational approach in choosing the sequence of signs of recognition and introduction to device recognition logic element OR register address of memory block selection address and the buffer register.

The proposed device can be implemented on the basis of the available serial integrated circuits, such as shift registers - based chips CIR, the control unit and the unit logic elements And on the basis of a series of chips To 155, the buffer register and the address register on the chip CIE, and blocks of memory - chip series CRRR.

Examples of implementation units of the device represented in scientific and technical literature. Schematic of multi-channel switch 1, an analog-to-digital Converter 4 presents, for example, in the reference manual Analog and digital integrated circuits", authors: S. Jakubowski Century, Barkanov N. A. and other (- M.: Radio and communication, 1984), schema element OR 2, the address register 3, blocks of memories 6 and 7, the buffer register 9, is the ways And 11 of block logic elements And 8 and the shift registers 12 of the unit shift registers 10 - in the directory "Application of integrated circuits in electronic computing", authors: P. Danilov Century, Alcova S. A. and others (- M.: Radio and communication, 1986), the circuit control unit 5 in the book of Anatoli I. N., Goryacheva Century. And. and Mansurov B. M. microelectronic circuits digital devices - M.: Radio and communication, 1990. - 416 p), and also in the book of etudes E. P. "Digital circuit" (St. Petersburg: publishing house "St. Petersburg", 2000. - 528). The principle page addressing is described in several references, for example in the book of Zilker B. I. Orlov, S. A., "computer Organization and systems" (- M, St-Petersburg: Piter, 2006. - 668). The use of a logic element OR 2, the address register 3, an additional memory block selection address 6 and the buffer register 10 in the proposed device leads to changes in the connection of the outputs of the unit shift register 10 to the address digits of the memory block selection address 6 as shown in Fig.1, and does not alter the typical circuit implementation of the memory block of coefficients associativity signs 7 and analog-to-digital Converter 4, is represented in the known device and the above-mentioned literature.

The proposed device can also be used for quick recognition of traffic situations for active transport security when there are many road traffic is Reznikov recognition with arbitrary nature of changes in values.

Device for pattern recognition, containing a multi-line switchboard, information the input of which is connected to the information input characteristics of the device, analog-to-digital Converter, an information input of which is connected to the output of the multi-channel switch, the memory block of coefficients associativity of signs, whose address inputs of the least significant bits are connected to the output of the analog-to-digital Converter, and the address inputs high-order bits are connected to the address inputs of the multi-channel switch, the unit logic elements And in which the first and second inputs of the logic elements And connected to the respective first and second inputs of the logical elements And the outputs of logic elements And are the outputs of logical block elements And, the unit shift registers in which information inputs of the first shift register connected to the corresponding information input unit shift registers, the shift inputs of shift registers connected to the corresponding lateral inputs of the unit shift registers, control unit, second, third and fourth outputs of which are connected respectively to the control input of the memory block of coefficients associativity of signs, to the second input of the logic element And to the control input of the analog-qi the world of the Converter, a first control unit connected to the control input of the outputs of the memory block of coefficients associativity signs connected to the corresponding information input unit shift registers and to the respective first inputs of logical block elements And whose outputs are connected to the corresponding lateral inputs of the unit shift registers, characterized in that it includes: a logic element OR an address register, the memory block selection address buffer register, and the outputs of the address register is connected to the address inputs of the high-order bits of the memory block selection addresses, the address inputs of the least significant bits of which are connected to the outputs of the unit shift registers, all outputs of the memory block address selection is connected to the inputs of the buffer register and the outputs of the least significant bits of the memory block selection address corresponding to the address of the next sign, also connected to the address inputs of the multi-channel switch and to the address inputs of the high-order bits of the memory block of coefficients associativity characteristics, the control input of buffer register connected to the control input of the analog-to-digital Converter and to the fourth output control unit, and outputs a buffer register connected to the inputs of the address register, the fault input of which is connected to the fault input of the block add the trade register and the fifth output control unit, and the control input of the address register connected to the second input of the logic elements And to the third output of the control unit, the first output of which is connected to the control input of the memory block address selection, all the outputs of the shift registers are connected to the outputs of the unit shift registers, and fault inputs of all shift registers are combined and connected to the fault input of the shift register, the outputs of the last digits of which are the outputs of the device and connected to the inputs of a logic gate OR the output of which is connected to the second control input of the control unit.



 

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EFFECT: automation and high efficiency of detecting trace amounts of controlled substances on hands, high sensitivity and reliability of detecting trace amounts of substances coupled with biometric verification of a person from hand shape.

FIELD: information technology.

SUBSTANCE: method of authenticating a bank account holder during a remote banking service using biometric properties of the face of the bank account holder is characterised by that when opening a bank account and/or issuing a bank card, a photograph of the account holder is taken and then stored in electronic form in the database of the bank and the bank card memory, and when conducting account transactions using a computer, a mobile telephone, an ATM, a point-of-sale terminal an image of the face of the person conducting a transaction via a web camera, an optical scanner, installed on the used hardware, is transmitted to the database of the bank, wherein the computer of the bank compares the obtained image with the image stored in the database of the bank, and authorises the transaction if the images are identical, or bars the transaction if the images do not match, and the card is blocked by the ATM at the instruction of the card issuer.

EFFECT: high reliability of authenticating a bank account holder.

FIELD: physics.

SUBSTANCE: invention relates to classification of biomolecular data. For this, classification system (100) is used. System input receives multiple attributes (102) of the sample to be classified and multiple appropriate error estimates (104). Statistical module (106) associates probability distribution density functions (108) with said attributes. Note here that appropriate probability distribution density functions depend upon error estimates. Replication module (110) generates multiple disturbed dummy treatments (112). Note here that attributes are arbitrarily disturbed in compliance with apt probability distribution density functions. Classifier (114) classifies disturbed dummy treatments on the basis of disturbed attributes. Analyser (118) classifies the sample to be classified proceeding from the analysis of classified dummy treatments (116) to produce classification (120) of samples.

EFFECT: higher reliability.

13 cl, 6 dwg

FIELD: information technology.

SUBSTANCE: method of searching for copyright infringements on an image, executed on a computer system, involves calculating a descriptor for an image N1, situated in a memory unit N1; calculating a descriptor for an image N2, situated in a memory unit N2; comparing the values of the descriptors of images N1 and N2; if said values are equal, images N1 and N2 are compared, after which the comparison results are displayed on an information display device.

EFFECT: high accuracy, quality and speed of searching for identical or confusingly similar images.

13 cl, 5 dwg

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to classification of image data and more specifically to classification of image data based on a model for adapting to an object in the image data. The system comprises a segmentation unit (110) for segmenting the image data by adapting the model to the object in the image data and a classification unit (120) for assigning a class to the image data based on the model adapted to the object in the image data, thereby classifying the image data, wherein the classification unit (120) comprises an attribute unit (122) for computing a value of an attribute of the model based on the model adapted to the object in the image data, and wherein the assigned class is based on the computed value of the attribute. Thus, the system (100) of the invention is capable of classifying image data without any user input. All inputs required for classifying the image data 10 constitute a model for adapting to an object in the image data. However, a person skilled in the art will understand that in some versions of the system (100), a limited number of user inputs may be enabled to let the user influence and control the system and the classification process.

EFFECT: enabling classification of image data without any data input by the user.

13 cl, 8 dwg

FIELD: information technology.

SUBSTANCE: method is realised by inserting an additional feature - the degree measure of the angle αMi - into the signal pattern at each interval thereof, and use thereof along with labels as an identifier in a two-dimensional feature space during identification increases the accuracy of identification and enables quantitative estimation of its value when the analysed signal is compared with a reference signal.

EFFECT: high accuracy of identifying signals with equal labels owing to better utilisation of information which characterises the form of change of the signal in the vicinity of the label.

4 dwg, 3 tbl

FIELD: information technology.

SUBSTANCE: associative recognition device comprises P units for calculating an activation function and P groups of units for generating membership function values, wherein each of the P groups of units for generating membership function values includes K units for generating membership function values, inputs of each of which are connected to inputs of like units of membership function values of each of the other groups from the P groups of units for generating membership function values and are inputs of the associative recognition device, wherein the device also includes P groups of multipliers by weight coefficients, each having K units of multipliers by weight coefficients, inputs of each of which are connected to outputs of corresponding units for generating membership function values from P groups of units for generating membership function values, and the outputs are connected to corresponding inputs of P units for selecting the maximum signal, and outputs of each of the P units for selecting the maximum signal are connected to the input of the corresponding unit for calculating the activation function from the P units for calculating the activation function.

EFFECT: broader functional capabilities of the device, high accuracy of recognition when identifying objects with separate weakly or partially distorted regions.

1 dwg

FIELD: information technology.

SUBSTANCE: disclosed is a method of performing video authentication of a user, which comprises steps of: receiving a user-provided authentication photograph; capturing a continuous video image of the user in real time over a certain period of time using a video capturing device at a user client; performing real-time decomposition of the video image and obtaining a series of video data frames; selecting from the series of video data frames a specific number of video data frames and generating at least one contrast image for video authentication of the user based on the specific number of video data frames; comparing the authentication photograph with the contrast image and making a decision on the user video authentication result according to the comparison result.

EFFECT: preventing falsification of an authentication photograph performed using a virtual camera.

10 cl, 2 dwg

FIELD: automated recognition of symbols.

SUBSTANCE: method includes following stages: tuning, forming symbols models, recognition, recording background model together with background of read image, separating model of registered background from elementary image of background, combining for each position of symbol of model of letters and/or digits with elementary displaying of appropriate background, forming of combined models, comparison of unknown symbols to combined models, recognition of each unknown symbol as appropriate symbol, combined model of which is combined with it best in accordance to "template comparison" technology.

EFFECT: higher efficiency.

10 cl, 10 dwg

FIELD: optical recognition of symbols.

SUBSTANCE: method includes dividing image on areas, finding areas with hand-written symbols, using structural and sign classifiers for recognition of symbols, use of structure classifier as main recognition tool, selecting best suiting symbol of several variants.. recognition of symbol includes recognition of symbol by at least one additional sign classifier of crossed symbols, performing concurrent comparison to crossed symbol and at least one common symbol like the latter, and identification of symbol as crossed one in case of better compliance to signs of crossed symbols.

EFFECT: higher efficiency.

1 dwg

FIELD: identification devices.

SUBSTANCE: device has photographic image of a person and microprocessor, which has processor, memory, connected to processor and containing authentication data, and interface means, connected to said processor to organize communication with external device. Said photographic image has specially concealed information, contents of which when combined with said authentication data provides for authentication of said photographic image, and said microprocessor is made with possible realization of at least a portion of said authentication.

EFFECT: higher efficiency.

5 cl, 4 dwg

FIELD: identity recognition devices.

SUBSTANCE: device has in case in form of small suitcase, a computer, which is compatible to operation systems meant for using programs of scientific identification. Computer is connected to display and keyboard, it can be connected to printer external relatively to case, and presumes presence of remote connection to processing center, responsible for identification. Device additionally has fingerprint reader connected to computer and digital camera connected to computer.

EFFECT: higher speed of operation, higher reliability, broader functional capabilities.

5 cl, 3 dwg

FIELD: polygraphy.

SUBSTANCE: method includes conversion of recognized and standard images to digital form, their digital processing by determining coordinates, comparison and determining of match of recognized and standard contours. Determining of coordinates of line of characteristic contour of recognized image of symbol is performed using appropriate standard graphic image by finding value of coordinates X, Y, angle β of position of optical center of text symbols by superposition along area of printed area of digital images - in straight contrast of standard on appropriate recognized in reversed contrast.

EFFECT: higher reliability.

2 cl, 1 dwg

FIELD: coherent optics, Fourier optics.

SUBSTANCE: method for recognition of images in optical-digital correlators includes procedures for input of amplitude distributions of standard and compared objects into correlator, transformation of these distributions to synthesized phase distributions, receiving correlation between them, registration of received recognition signal and estimation of recognition result, distributions of standard and compared objects, related to arbitrary type objects, are unambiguously matched with phase random distributions Ψst(x,y), Ψ(x,y), synthesized from distributions of standard and compared objects and starting phase distribution Ψo(x,y), utilized further during recognition in optical-digital correlator instead of real objects.

EFFECT: increased trustworthiness of recognition of images of arbitrary class objects.

7 dwg

FIELD: technology for encoding and recognition of papillary patterns, possible utilization in automated biometric informational systems for identification of personality.

SUBSTANCE: method includes generation of three passports, including an additional statistical one and determinate one. Successive execution of comparison procedures of given papillary patterns received from papillary pattern indicator with passports makes it possible to shorten total duration of recognition procedure due to taking a decision about recognition of papillary patter at early stages while satisfying recognition clarity criterions.

EFFECT: increased trustworthiness and speed of recognition of papillary pattern images due to prevented influence of rotation and shifting of compared papillary patterns, automatic consideration of systematic and random errors, decreased duration of recognition procedure.

5 cl

FIELD: technologies for encoding and recognizing papillary patterns, possible utilization in automated biometrical information systems for identification of personality.

SUBSTANCE: method includes stage of generation of papillary pattern passport with further placement of the latter into computer memory, and stage of comparison of given papillary pattern to passport of papillary patterns, which utilization procedure for comparing two sets of values of electric parameters with arbitrary number of characteristic points, which is performed by full search of sets of characteristic parameters of all characteristic points. In process of full search of sets of coordinates and characteristic parameters, values of electric parameters are selected, matching in two sets, on basis of numbers of coincidences a signal is generated about match of compared sets of electric parameter values.

EFFECT: shorter time and increased trustworthiness of recognition of papillary patterns; prevented influence from rotation and shifting of papillary patterns, increased stability of characteristics and decreased length of papillary pattern passport.

6 cl

FIELD: engineering of equipment, limiting access to system being protected, possible use for preventing unsanctioned access to system by random individuals.

SUBSTANCE: method includes determining coordinates of certain specifics of papillary pattern of user and on basis of difference of coordinates of produced image of print and one stored in database, positive or negative decision is produced about access of user to system.

EFFECT: increased level of protection of system.

2 dwg

Monitoring method // 2282895

FIELD: method for monitoring marks, made on printed documents.

SUBSTANCE: method includes making a digital image of front side of document by determining content of one-color and multi-color components of image pixels, content of color component of each pixel is compared to range from upper to lower thresholds for appropriate pixel of acceptable unmarked document and appropriate abnormal pixel is generated, if value of pixel is outside interval between upper and lower thresholds, then presence of mark different from dirt is detected, if abnormal pixels produced as a result satisfy previously set conditions.

EFFECT: provision of possible determining of some or other forms of distortion of document.

3 cl, 6 dwg

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