Degenerative voltage stabiliser

FIELD: electricity.

SUBSTANCE: voltage stabiliser includes first and second transistors connected by emitters to a common bus, first and second resistors connected by first outputs to the common bus, third transistor connected by emitter to second output of the first resistor, third resistor connected by first output to connection point of first transistor base and third transistor collector, fourth transistor connected by collector to output terminal, fourth resistor connected by first output connection point of second output of third resistor and fourth transistor emitter, second transistor collector and base connected to second output of fourth resistor, fifth resistor connected by first output to output terminal and by second output to connection point of fourth transistor base and second output of second resistor, fifth and sixth transistors connected by emitters to power bus and by bases to sixth transistor collector, seventh transistor connected by collector to power bus, eighth transistor connected by emitter to output terminal, current source inserted between power bus and connection point of eighth transistor base and first and fifth transistor collectors, sixth resistor inserted between second and third transistor bases, eighth transistor collector connected to sixth transistor collector, seventh transistor base connected to eighth transistor base, seventh transistor emitter connected to output terminal.

EFFECT: output voltage of stable temperature, reduced minimum difference of stabiliser input/output voltage.

4 dwg

 

The device relates to the field of electrical engineering and can be used as a secondary source of power.

Known voltage regulators (SN) with compensation-parametric channels [Starchenko E.I. voltage regulators with compensation-parametric channels: monograph.- Mine: GOU VPO "law", 2009. (RES)], with a relatively low temperature stability.

The closest technical solution adopted for the prototype, is the voltage regulator (SN), is shown in figure 1 [Path of the Russian Federation. The voltage regulator / Iverilog, Daandine, Ehistoric. - Publ. 10.07.2000, bull. No. 19.]. The main disadvantage of the prototype can be attributed to the increased value of the minimum difference voltage "input-output" (equal to three times the value of the voltage base-emitter voltage) and the need to use a composite regulatory element two identical high current transistors are connected in series.

The task to be solved by the invention, is to provide the claimed technical effect of improving the temperature stability of the output voltage and reducing the minimum difference voltage "input-output".

To achieve the claimed technical result in the scheme of the prototype, containing the first and second transis the ora, the connected emitters to a common bus, the first and second resistors connected to the first output to the shared bus, the third transistor, an emitter connected to the second output of the first resistor, the third resistor, the first terminal connected to the connection point of the first base to the collector of the third transistor, the fourth transistor, a collector connected to the output terminal, the fourth resistor, the first terminal connected to the connection point of the second output of the third resistor to the emitter of the fourth transistor, the base and the collector of the second transistor is connected to the second output of the fourth resistor, a fifth resistor connected to the first output to the output terminal, and the second - to-point connection the base of the fourth transistor with the second output of the second resistor, the fifth and sixth transistors connected emitters of the power bus, and databases - to the collector of the sixth transistor, the seventh transistor, a collector connected to the power bus, the eighth transistor, the emitter connected to the output terminal, a current source connected between the power bus and the connection point of the base of the eighth transistor to the collectors of the first and fifth transistors, entered the sixth resistor connected between the bases of the second and third transistors, the collector of the eighth transistor is connected to the collector of the sixth transistor, the base of the seventh is resistor connected to the base of the eighth transistor, the emitter of the seventh transistor is connected to the output terminal.

The outline of the prototype is shown in figure 1, the inventive device in figure 2.

Declare SN (figure 2) contains the first and second transistors 1 and 2, connected emitters to a common bus, the first and second resistors 3 and 4, connected to the first output to the shared bus, the third transistor 5, the emitter connected to the second output of the resistor 3, the third resistor 6 connected to the first output to the connection point of the base of the transistor 1 and the collector of the transistor 5, the fourth transistor 7, a collector connected to the output terminal, the fourth resistor 8 connected to the first output to the connection point of the second output resistor 6 with the emitter of the transistor 7, the base and collector of transistor 2 is connected the second output of the resistor 8, the fifth resistor 9 connected to the first output to the output terminal, and the second to the connection point of the base of the transistor 7 to the second output of the resistor 4, 10 fifth and sixth transistors 11 connected emitters of the power bus, and databases - to the collector of the transistor 11, the seventh transistor 12, the collector connected to the power bus, the eighth transistor 13, an emitter connected to the output terminal, the current source 14 connected between the power bus and the connection point of the base of the transistor 13 with the collectors of the transistors 1 and 10, the sixth resistor 15 connected between bases Tran is Vtorov 2 and 5, the collector of transistor 13 is connected to the collector of the transistor 11, the base of transistor 12 is connected to the base of transistor 13, the emitter of transistor 12 is connected to the output terminal.

The operation of the claimed device (figure 2). in many respects similar to the circuit of the prototype. Transistors 10-13 play the role of a composite regulatory element (re)covered by the feedback current load. The role of the current sensor is played by the transistor 13, the area of the emitter of which is in N1times smaller than the area of the emitter of the transistor 12. So we can assume that the collector current of the transistor 13 in N1times smaller than the collector current of transistor 12, and proportional to the current load.

It can be shown that the resulting transmission coefficient re current βis defined by the following expression:

βΣ=ΔIHΔIBXΣ=β1+11-β1β2N2(N1+1)(N2+β2+1),(1)

where ΔIHand ΔIBX∑-increment, respectively, the output and the input current integral ER; β1and β2- transfer coefficients of the current, respectively, of transistors 13 (12) 11 (10); N2- transfer ratio current follower transistors 10 and 11. Condition settings, where βturns into infinity:

β1β2N2=(N1+1)(N2+β2+1),(2)

which for N2=1 and β>>1 is type-N1+1=β1.

A significant difference between the claimed device is the introduction of the resistor 15 in the reference voltage based on the width of the forbidden band of silicon, combined with the power of the error signal (items 1-9). The base current of the transistor 5 creates the resistor 15, the voltage drop whose influence on the output voltage affects mainly at low temperatures, since the dependence of β (the ratio of current) of the transistor temperature T is expressed as follows:

β= β0(TT0)32,(3)

where β0- gain value β at ambient temperature T0. Thus, the presence of an additional temperature dependence allows to compensate for the component of the temperature drift of the output voltage of the second order.

Figure 3 presents a graph showing the change of the output voltage of the claimed SN when the temperature changes, and figure 4 - simulation results of the prototype. From the simulation results we can conclude the following: the absolute change of the output voltage of the claimed SN at least seven times smaller than the prototype, and the relative temperature drift is about four times smaller.

It is obvious that the minimum voltage difference input-output scheme of the prototype is 3UEBand in the diagram of the inventive CH-2UEBand output impedance in the circuit claimed SN can also accept a null value.

Thus, analysis, and data circuit simulation confirm that achieves the claimed technical result is a reduction in the pace of the temperature coefficient of the output voltage.

Voltage stabilizer, containing the first and second transistors connected emitters to a common bus, the first and second resistors connected to the first output to the shared bus, the third transistor, an emitter connected to the second output of the first resistor, the third resistor, the first terminal connected to the connection point of the first base to the collector of the third transistor, the fourth transistor, a collector connected to the output terminal, the fourth resistor, the first terminal connected to the connection point of the second output of the third resistor to the emitter of the fourth transistor, the base and the collector of the second transistor is connected to the second output of the fourth resistor, a fifth resistor connected to the first output to output terminal, and the second to the connection point of the base of the fourth transistor with the second output of the second resistor, the fifth and sixth transistors connected emitters of the power bus, and databases - to the collector of the sixth transistor, the seventh transistor, a collector connected to the power bus, the eighth transistor, the emitter connected to the output terminal, a current source connected between the power bus and the connection point of the base of the eighth transistor to the collectors of the first and fifth transistors, characterized in that the device entered the sixth resistor connected between the bases of the second and third Tr is Nestorov, the collector of the eighth transistor is connected to the collector of the sixth transistor, the base of the seventh transistor is connected to the base of the eighth transistor, the emitter of the seventh transistor is connected to the output terminal.



 

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