Method for automatic synchronisation of reception and processing of data stream on start symbol and apparatus for realising said method

FIELD: information technology.

SUBSTANCE: apparatus includes a shift register, a deserialiser, a start symbol register, comparator units, a shift value register, a multiplexer, an OR logic element and a data processing unit.

EFFECT: low power consumption and high efficiency.

2 cl, 2 dwg

 

The invention relates to the field of computer technology, namely high-speed serial data interfaces that use to synchronize the receiver and transmitter of the starting characters.

Currently known methods and devices for processing serial data stream containing the register bit shift data and the validation block content that register the presence of a predetermined starting sequence. They are not suitable for use in high-speed serial interfaces, where the maximum frequency of operation of the data processing unit and energy minimization.

The closest to the technical essence and the achieved technical result is a method of receiving and processing a data flow, including the preservation received from the receiver data and checking their match with a pre-specified sequence, through a device containing a shift register, connected to the receiver serial transmission of binary data, and units of comparison (US Patent No. 4166271, CL G06F 7/02, published. 1979).

The disadvantage of the described method and device is the low productivity caused by the inability of parallel processing of data by shifting the data in each cycle is only one digit.

The objective of the invention is to create a device that provides the possibility of parallel processing of data.

The technical result from the use of the invention is to reduce energy consumption and increase productivity by providing the possibility of parallel processing of data.

This technical result is achieved in that in the method of synchronization of receiving and processing a data flow, including the preservation received from the receiver data and checking their match with a pre-specified sequence, verify the availability and the possible location of the start character in the input shift register, when the detection of the start symbol calculates the amount of shift and fix it, and then constantly shift all received from the data receiver at a fixed value by means of the device containing the shift register, connected to the receiver serial transmission of binary data and units of comparison, according to the invention is further provided with deserializers, multiplexer, the register value of the shift element "logical OR" and register the start character, while the shift register is made in the form of a set of serially connected buffers that have carried the only digits, and Deserializer connected to the receiver serial transmission of binary data and the buffer shift register, the bits of the register, the start symbol is connected to the units of comparison, which is connected to the element of "logical OR" and the register value of the shift, when this latter is connected to the multiplexer, connected to the buffer shift register, and element "logical OR" and the multiplexer is configured to connect to the data processing unit.

The invention is illustrated by drawings, where figure 1 shows a General diagram of the device, figure 2 - layout of the starting character in the buffers Deserializer and shift register.

Way synchronization of reception and processing of the data stream start symbol is as follows.

To synchronize Deserializer with the data processing unit carry out the shift from Deserializer data. Coming from buffer Deserializer data is placed in series connected between the buffer shift register for intermediate storage. On each step of the data from the buffer Deserializer served in the first buffer while the data from the first buffer overwrite in the second buffer, and so on. The number of bits in each of the intermediate buffer is chosen equal to the number of digits in b the area of Deserializer. The total width of the intermediate buffers must be equal to the length of the start symbol. On each step of checking the availability of the buffers start character through blocks comparison. This check is done by iterating through all of the options for the location of the start symbol. As soon as the buffer is known in advance of the start symbol, produce a variant definition of its location. Based on this, calculate the number of bits required to shift from Deserializer data. The offset recorded in the register. This register controls the multiplexer, which make the selection of one of shift options. The shift is produced by combining consecutive bits in the intermediate buffers. After fixing the magnitude of the shift register all data coming from Deserializer until the next reset signal before processing by the receiver shift on recorded in this register value. The appearance in the buffers of the start symbol is a signal to start operation of the data processing unit. After that, the synchronization process of receiving and processing data flow is completed.

The above method is implemented by the device auto-synchronization of the reception and processing of the data stream for a starting character.

The device consists of d is of serializer 1 buffer 2, with the digits 3, 4, 5, 6. Buffer 2 Deserializer connected to the buffer 7 shift register having bits 8, 9, 10, 11, which in turn is connected to the buffer 12 shift register having bits 13, 14, 15, 16. The buffer 2 Deserializer and buffers 7 and 12 are connected with four blocks comparison, 17, 18, 19, 20. The total width of the blocks correspond to the comparison to the width of the buffer 2 Deserializer. The Comparer 17 get the data from the buffers 7 and 12. The Comparer 18 - the low-order 3 data buffer 2 data buffer 7 and the three senior level 14, 15, 16 data from the buffer 12. The Comparer 19 - two minor category 3, 4 data buffer 2 data buffer 7 and two senior level 15, 16 data from the buffer 12. The Comparer 20 - three Junior level 3, 4, 5 data buffer 2 data buffer 7 and one high-order 16 data from the buffer 12. Also, for each block comparison, 17, 18, 19, 20 connected to the output of the register, the start symbol 21. Units of comparison, 17, 18, 19, 20 are connected with a logical OR element 22 and the register value of the shift 23. The register value of the shift 23 is connected to the multiplexer 24 to which is also connected to buffer 2 Deserializer (grades 3, 4 and 5) and the buffer 7 (bits 8, 9, 10, 11). The multiplexer 24 and the logical element OR 22 is connected to the data processing unit 25.

The device auto-synchronization of the reception and processing of the data stream for a starting character works with edusim way.

Deserializer 1 accepts a serial data stream. The width of the buffers 7, 12 shift register corresponds to the width of the buffer 2 Deserializer 1. The number of buffers 7, 12 shift register is determined by the length of the starting symbol that you want to recognize. The total width of the buffers 7, 12 standing after buffer 2 Deserializer 1, should be allowed to put in them starting character entirely. For simplicity, consider the case of buffer 2 Deserializer 1 width 4 bits and the start character length of 8 bits. Such a starting character is present, for example, in the interface Space Wire - this is an 8-bit character NULL 01110100, which must recognize the receiver interface Space Wire before beginning processing of the data stream.

On each step the data is copied from the buffer 2 buffer 7, from the buffer 7 the buffer 12. On each step of also using the block comparison, 17, 18, 19 and 20 is checked whether the buffers 2, 7 and 12 specified starting character. After detection by using one of the blocks comparison of the start symbol, a sample of which is in register start character 21, the block number is recorded in the register shift values 23. A new entry in this register will be possible only after the connection.

Using a multiplexer 24, a control signal which is the output of the register value of the shift 23, from buffers 2 and 7 otbiraetsya bits who will get into the data processing unit 25 on each step. Thus is the sync reception and processing of the data stream by determining the amount of shift of the start symbol.

1. Way synchronization of receiving and processing a data flow, including the preservation received from the receiver data and checking their match with a pre-specified sequence, characterized in that conduct testing for the presence and the possible location of the start character in the input shift register, when the detection of the start symbol calculates the amount of shift and fix it, and then constantly shift all received from the data receiver at a fixed value.

2. The device for implementing the method containing the shift register, connected to the receiver serial transmission of binary data and the blocks of the comparison, wherein the device is further provided with Deserializer, a multiplexer, a register value of the shift element "logical OR" and register the start character, while the shift register is made in the form of a set of serially connected buffers with multiple discharges, and Deserializer connected to the receiver serial transmission of binary data and Boo the EPAM shift register, the bits of the register, the start symbol is connected to the units of comparison, which is connected to the element of "logical OR" and the register value of the shift, when this latter is connected to the multiplexer, connected to the buffer shift register, and element "logical OR" and the multiplexer is configured to connect to the data processing unit.



 

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