# Device for conversion from polynomial system of residue classes to position code

FIELD: information technology.

SUBSTANCE: device has a device start input, a group of shift registers, a synchronisation unit, a device output, three-input AND element units, a modulo 2 adder, a group of data inputs, a group of control inputs of the device, a group of orthogonal base computing units, each having memory units, a modulo adder, a register, an index-to-element converter and a multiplier.

EFFECT: high rate of conversion.

2 dwg, 2 tbl

The invention relates to computing, and in particular to modular setprocessor (JV)operating in polynomial system classes deductions (PSCW) and is able to maintain a healthy state when an error occurs due to the reconfiguration of the structure.

A device for conversion of a polynomial system classes deductions in the position code (Patent No. 2409840, G06F 11/07, published on 20.01.2011, bull. No. 2), which contains the starting device, a group of shift registers, synchronization unit, output devices, the group of blocks calculation of orthogonal bases, blocks trehshipovyh elements And, modulo two, the group of information inputs, a group of control inputs, while the group of blocks calculation of orthogonal bases contains the first block of memory, a multiplier, a second memory block, the second multiplier, register, output register.

The disadvantage of this device is the low rate of conversion from the code PSCW in the position code.

The technical result of the invention is to increase the conversion speed of the code PSCW in the position code by reducing calculation time orthogonal bases modular code

This technical result is achieved due to input into the design of the block of calculation of orthogonal bases of modulo and preobrazovala what I "index -
element instead of the first multiplier modulo p_{i}(z)used in the prototype.

A device for conversion of a polynomial system classes deductions in the position code containing the input device is started, a group of shift registers, synchronization unit, output devices, blocks And elements, the group of information inputs, and the input of the start device is connected to the input of the start of the synchronization unit, the output of which is connected to the enable inputs of shift of the shift registers of the group of information inputs of which are the corresponding information input device groups, the output of the i-th shift register group is connected with the first input element And the i-th group (i=1, 2, ..., n), and the device contains the group of blocks calculation of orthogonal bases, modulo two control inputs of the device, and outputs the synchronization unit connected to the first input blocks calculation of orthogonal bases, the second input of which is connected to the control inputs of the device, the output of the i-th block of the calculation of orthogonal bases connected to the second input elements And the i-th block, the third inputs of which are connected with the respective managing logon group, the outputs of the elements And are connected with the inputs of the modulo two, the output of which is an output device. Thus according to the invention the POC calculation of orthogonal bases contains the state clock inputs, n control inputs, the first and second memory blocks, multiplier, adder modulo register, inverter index-item, and the state clock inputs connected to the first and second memory blocks and to register, n control inputs connected to the first and second memory blocks, the output of the first memory block connected to the first input of the modulo, the output of the second memory block is connected to the second input of the multiplier, the output of the adder module is connected to the input of the register, the first register is connected to the input of the inverter index-item, the inverter output index element connected to the first input of the multiplier, to the second input of the multiplier connected to the output of the second memory block, the second output register connected to the second input of the adder module, the output of the multiplier is the output of the block.

To translate from code PSCW in the position code used Chinese theorem on residues (WHO), according to which

where B_{i}(z) - orthogonal basis of the i-th base,

An orthogonal basis is defined as

where m_{i}(z) - orthogonal basis weight of the i-th base.

The use of m_{i}(z) can enforce conditions

.

Convert expression (2) to the form

Substituting the equality (3) in expression (1), get the

where- return value is the Foundation of the p_{j}(z) modulo p_{i}(z); k is the number of information bases; r is the number of control grounds; k+r=n.

To increase the speed of calculation of the orthogonal basis B_{i}(z) is assumed to refuse to perform multiplicative procedure (4) calculate the weight of m_{i}(z) and go to the index view, which reduces the calculation of m_{i}(z) in the form of a set of additive operations.

For effective implementation of the operations of multiplicative type (multiplication, division, exponentiation) is characterized by the use of theory of indices. The number of i_{A}which solution comparison

is called the index number of a and is denoted by i_{A}=indA. A primitive root g is called a basis of the index.

It is known that the index J of the works of art are simple integers A_{1}And_{2}, ..., A_{k}modulo p is equal to the sum of the indices of the factors modulo p-1, ie,

where i_{1}, i_{2}, ..., i_{k}- the indices of the positive numbers A_{1}And_{2}, ..., A_{k}modulo p in the integral code g.

Thus, the obvious possibility of reducing the multiplication of two operands a and b for modulating the R to the operation of summation indices i_{
A}, i_{B}these operands when a primitive root g modulo p-1.

The structure of the device shown in figure 1. The device has an input 1 of the device's launch, a group of shift registers 2, the synchronization unit 3, output 4 devices, the group of blocks 5 calculation of orthogonal bases, blocks 6 trehshipovyh elements And the adder 7 modulo two, the group of information inputs 8, a group of control inputs 9 of the device.

Input 1 start device is connected to the input of the start of the synchronization unit 3, the output of which is connected to the enable inputs of shift of the shift register group 2, information inputs which are relevant informational inputs, 8 groups of devices, the output of the i-th shift register group 2 connected to the first input element And the i-th group (i=1, 2, ..., n) blocks 6 trehshipovyh elements I. the Outputs of the synchronization unit 3 is also connected to the first input unit 5 calculation of orthogonal bases, the second input of which is connected to the control inputs of the device 9, the output of the i-th block of the calculation orthogonal bases 5 is connected to the second input elements And the i-th unit 6, the third inputs of which are connected with the respective managing input group 9, the outputs of the elements And unit 6 is connected to the inputs of the adder 7 modulo two, the output of which is the output device 4.

To increase the speed of calculation of ortog the national basis in blocks of 5 calculation of orthogonal bases instead of the multiplier modulo p_{
i}(z) (where i=1, 2, ... n)used in the prototype set modulowherethe inverter index-item.

The unit of calculation of orthogonal bases contains the state clock inputs 10, n control inputs 11, the first memory block 12, modulo 13, a register 14, the inverter index-element 15, the second memory block 16, the multiplier 17, the output 18 of the block. The block structure shown in figure 2.

The state clock inputs 10 is connected to the state clock inputs of the first memory block 12, the second memory unit 16, a register 14, and the control input 11 is connected to the address inputs of the first 12 of the memory block and the second memory block 16. The first input of the modulo 13 is connected to the output of the first memory block 12, and the second input of the adder module is connected to the second input register 14. The input of the register 14 is connected to the output of the adder modulo 13. The input of the Converter index element 15 is connected to the first output of the register 14, and the output connected to the first input of the multiplier 17, the second input is connected to the output of the second memory block 16. The output of multiplier 17 is the output 18 of the block of calculation of orthogonal bases.

The number presented in the code PSCW, A(z)=(α_{1}(z), α_{2}(z), ..., α_{n}(z)), through a group of information inputs 8 is recorded in shift registers 2 groups, and deductions for each of the grounds PSCW adosada in its register 2.
The operation of the device occurs in cycles. In each step the contents of register 2 is shifted to the right (towards the least significant bits) for one digit. The algorithm of operation of the device can be represented in the form

where n is the number of bases PSCW;

the degree of the i-th base PSCW;

- the value of the g-th category of the i-th base PSCW;

- converted value of the i-th orthogonal basis.

From the expression (7) shows that the device implements the operation of the sequential summation works recalculated orthogonal basesassignment of residue of α_{i}(z), is represented in binary code.

The unit of calculation of orthogonal bases 5 operates as follows. When first receiving the synchronization signal from the synchronization unit 3 inputs 10 of the first memory block 12 to the first input of the modulo 13 is served first index valuethat added up to zero and is input to the register 14. With the advent of the second synchronization signal at the input 10 is obtained from the second output register 14 is applied to a second input of the modulo 13, at the first input of which receives the second index valuewith the release of the first memory block 12.

After n-1 tact with the register 14 is the value of the index weight orthogonal basis of m_{i}(z), according to

Andare determined by the value of signal c of the j-th control input 11, according to the condition

The values of the signals on the control inputs 11, is determined from the condition

The calculated value of the index γ_{i}weight of orthogonal basis is fed to the input of the inverter index-item 15. It is designed to convert binary code index γ_{i}in binary code weight m_{i}(z). Thus, this Converter is the index of the element 15 may be implemented on the basis of codeprivate.

The obtained value of m_{i}(z) weight orthogonal basis for the i-th base is fed to the first input of the multiplier 17, and to the second input of the latter is supplied with the output of the second memory block 16

where l∉U_{OTC}; U_{OTC}many failed reason during the operation of the computing system PSCW; g=0, 1, ..., deg p_{i}(z)-1.

The constants z^{g}P^{*}(z) is stored in the second memory block 16 and is selected according to the signals on the control inputs 11.

From the output of the multiplier 17 snime the Xia

which goes to the output 18 of the block of calculation of orthogonal bases.

If during the operation of the computing system PSCW fail b-s based on the control inputs 9, a signal will appear

This signal is fed to the control inputs of 11 units 5 calculation of orthogonal bases. Running this signal from the first unit 12 to the memory index valuesand modulo 13 (n-2) quantum calculates the index value γ_{i}according to (8). When this.

Under control of signals received from the control inputs 11, and state clock inputs 10, from the second memory block 16 receives the values defined by expression (11). The multiplier 17 implements the expression (12), where

Simultaneously, the values (y_{1}, ..., y_{b-1}, y_{b}, y_{b+1}, ..., y_{n})=(1, ..., 1, 0, 1, ..., 1) served on the third inputs of the 6 elements And 6 blocks. Zero signal y_{b}=0 produces the closure elements And the b-th block 6. Thus, the values of α_{b}(z)·B_{b}(z) to obtain the final result according to not participate, as to the adder 7 and they are not served.

Consider the example

It is necessary to calculate the value of orthogonal bases PSCW with the bases of p_{1}(z)=z+1; p_{2}(z)=z^{2}+z+1 p_{
3}(z)=z^{4}+z^{3}+z^{2}+z+1, p_{4}(z)=z^{4}+z^{3}+1, p_{5}(z)=z^{4}+z+1.

According to (14) and taking into account that failed there is no defined values of P_{i}(z)

P_{1}(z)=p_{2}(z)p_{3}(z)p_{4}(z)p_{5}(z)=z^{14}+z^{13}+z^{12}+z^{11}+z^{10}+z^{9}+z^{8}+z^{7}+z^{6}+z^{5}+z^{4}+z^{3}+z^{2}+z+1;

P_{2}(z)=p_{1}(z)p_{3}(z)p_{4}(z)p_{5}(z)=z^{13}+z^{12}+z^{10}+z^{9}+z^{7}+z^{6}+z^{4}+z^{3}+z+1;

P_{3}(z)=p_{1}(z)p_{2}(z)p_{4}(z)p_{5}(z)=z^{11}+z^{10}+z^{6}+z^{5}+z+1;

P_{4}(z)=p_{1}(z)p_{2}(z)p_{3}(z)p_{5}(z)=z^{11}+z^{10}+z^{9}+z^{8}+z^{6}+z^{4}+z^{3}+1;

P_{5}(z)=p_{1}(z)p_{2}(z)p_{3}(z)p_{4}(z)=z^{11}+z^{8}+z^{7}+z^{5}+z^{3}+z^{2}+z+1;

To fulfill thecalculate the weights of the orthogonal bases. Get m_{1}(z)=1; m_{2}(z)=z; m_{3}(z)=z^{3}+z; m_{4}(z)=z^{3}; m_{5}(z)=z.

We determine the values of m_{1}(z). Then

m_{1}(z)=1; m_{2}(z)=z^{2}(z+1)mod(z^{2}+z+1)=z;

m_{3}(z)=[(z^{3}+z)(z^{3}+1)(z^{2}+1)(z^{3}+z^{2}+1)]mod(z^{4}+z^{3}+z^{2}+z+1)=z^{3}+z;

m_{4}(z)=[z^{5}(z^{3}+z+1)(z^{3}+z^{2}+z+1)]mod(z^{4}+z^{3}+1)=z^{3};

m_{5}(z)=[(z^{3}+z^{2}+)(z^{
3}+z)(z^{2}+z)(z^{3}+z^{2})]mod(z^{4}+z+1)=z.

Consider the work of the group of blocks calculation of orthogonal bases 5 block functioning modulo p_{5}(z)=z^{4}+z+1. Imagine all the reasons PSCW as elements of the field generated by the module p_{5}(z)=z^{4}+z+1

Then have

p_{1}(z)mod p_{5}(z)=(z+1)mod(z^{4}+z+1)=z+1

p_{2}(z)mod p_{5}(z)=(z^{2}+z+1)mod(z^{4}+z+1)=z^{2}+z+1

p_{3}(z)mod p_{5}(z)=(z^{4}+z^{3}+z^{2}+z+1)mod(z^{4}+z+1)=z^{3}+z^{2}

p_{4}(z)mod p_{5}(z)=(z^{4}+z^{3}+1)mod(z^{4}+z+1)=z^{3}+z

Table 1 presents the correspondence of the values of the grounds and used indexes

Table 1

Base | The field element | Multiplicative inverse element | The index return |

p_{1}(z) | z+1 | z^{3}+z^{2}+z | 11 |

p_{2}(z) | z^{2}+z+1 | z^{2}+z | 5 |

p_{3}(z) | z^{3}+z^{2} | z^{}
+z | 9 |

p_{4}(z) | z^{3}+z | z^{3}+z^{2} | 6 |

Since all channels are in a healthy state, control input, a signal will appear (y_{1}, y_{2}, y_{3}, y_{4}, y_{5})=(1, 1, 1, 1, 1), which goes to the control inputs 11 calculation unit orthogonal basis 5 when receiving the first signal.

Upon receipt of the first signal input 10 output of the first memory block 12 is given a value of. Thus, the degree of the polynomial p_{5}(z) is equal to deg p_{5}(z)=4, the adder 13 works modulo M=2^{4}-1=15. Received the value ofaccording to the first input of the adder 13 to the module is folded by zero. The result is written to the register 14.

Upon receipt of the second signal input 10 output of the first memory block 12 to the first input of the adder 13 to the module returns the value of. This value is modulo 15, with the resultreceived on the second input of the adder 13 register 14. The result of the operation

recorded in the register 14.

Upon receipt of the third signal input 10 output of the first memory block 12 on p is pout input of the adder 13 to the module returns the value of . This value is added to the previous result received by the second input of the adder 13 and the register 14. The result of the operation (1+9) mod 15=10 is recorded in the register 14.

Upon receipt of the fourth signal input 10 output of the first memory block 12 to the first input of the adder 13 to the module is given the value of. This value is added to the previous result received by the second input of the adder 13 to the module from the register 4. The result is the index value γ_{5}=(10+6) mod 15=1 for weight m_{5}(z) orthogonal basis B_{5}(z).

Received the value from the first output of the register 14 is fed to the input of the inverter index-item 15. This Converter converts the input index code into binary code element according to table 2.

Table 2 | |||

The compliance index and the value of the element | |||

Index | Input code | Binary code | |

0 | 0000 | 1 | 0001 |

1 | 0001 | z | 0010 |

2 | 0010 | z^{2} | 0100 |

3 | 0011 | z^{3} | 1000 |

4 | 0100 | z+1 | 0011 |

5 | 0101 | z^{2}+z | 0110 |

6 | 0110 | z^{3}+z^{2} | 1100 |

7 | 0111 | z^{3}+z+1 | 1011 |

8 | 1000 | z^{2}+1 | 0101 |

9 | 1001 | z^{3}+z | 1010 |

10 | 1010 | z^{2}+z+1 | 0111 |

11 | 1011 | z^{3}+z^{2}+z | 1110 |

12 | 1100 | z^{3}+z^{2}+z+1 | 1111 |

13 | 1101 | z^{3}+1 | 1101 |

14 | 1110 | z^{3}+1 | 1001 |

Then the inverter output index element 15 is removed, the value of m_{5}(z)=z=0010. The value obtained from the output of the Converter 15 is supplied to the first input of the multiplier 17, the second input of which is supplied value

P_{5}(z)=p_{1}(z)p_{2}(z)p_{3}(z)p_{4}(z)=z^{11}+z^{8}+z^{7}+z^{5}+z^{3}+z^{2}+z+1

with the release of the second memory block 16. This value is determined by the signal on the control input 11

(y_{1}, y_{2}, y_{3}, y_{4}, y_{5})=(1, 1, 1, 1, 1).

In the result, the values of the orthogonal basis is equal to

B_{5}(z)=m_{5}(z)P_{5}(z)=z^{l2}+z^{9}+z^{8}+z^{6}+z^{4}+z^{3}+z^{2}+z.

The rest of the blocks 5 are similar.

Carry out a comparative analysis of the speed of calculation of orthogonal bases in the prototype and the proposed device.

In the prototype to calculate the weight of orthogonal basis requires (n-1) mind is ogeni module. When using a Raman-type multiplying this time will be

where T_{AA}is the execution time of the multiplication of L-bit operands;

T_{sum}the operation of addition; L - bit width of the multiplier.

In the proposed device for calculating the weight of orthogonal basis requires (n-1) modulo addition and conversion "index-item". The last operation can be implemented using the serial connection of the encoder and decoder, then the evaluation of the weight of orthogonal basis will be determined

where T_{CD}- the response time of encoder; T_{DC}- the response time of the decoder.

The analysis of expressions (15) and (16) shows that replacing the multiplicative operation for obtaining the weight of m_{i}(z) the additive can improve the calculation speed of the orthogonal basis.

The device for converting of the polynomial system classes deductions in the position code containing the input device is started, a group of shift registers, synchronization unit, output devices, blocks And elements, the group of information inputs, and the input of the start device is connected to the input of the start of the synchronization unit, the output of which is connected to the enable inputs of shift of the shift register group in formazione inputs which are the corresponding information input device groups, the output of the i-th shift register group is connected with the first input element And the i-th group (i=1, 2, ..., n), and the device contains a group of blocks calculation of orthogonal bases, modulo two control inputs of the device, and outputs the synchronization unit connected to the first input blocks calculation of orthogonal bases, the second input of which is connected to the control inputs of the device, the output of the i-th block of the calculation of orthogonal bases connected to the second input elements And the i-th block, the third inputs of which are connected with the respective managing logon group, the outputs of the elements And connected with the inputs of the modulo two, the output of which is an output device, wherein the block of calculation of orthogonal bases contains the state clock inputs, n control inputs, the first and second memory blocks, multiplier, adder modulo register, inverter index-item, and the state clock inputs connected to the first and second memory block and to register, n control inputs connected to the first and second memory blocks, the output of the first memory block connected to the first input of the modulo, the output of the second memory block is connected to the second input of the multiplier, the output of the adder module is connected to the input register, the first register is connected to the input of the inverter index-element, the output is transformed into the La index element connected to the first input of the multiplier, to the second input of the multiplier connected to the output of the second memory block, the second output register connected to the second input of the adder module, the output of the multiplier is the output of the block.

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