# Method of facilitating multiplication of two numbers in modular-position presentation format with floating point on universal multi-core processors

FIELD: information technology.

SUBSTANCE: method is realised on a universal multi-core computer, having g k-bit cores, each facilitating a system of f operations which include algebraic multiplication and algebraic addition of numbers presented in position integer data formats. When facilitating multiplication operations, each number, multiplier and multiplicand, is presented in a modular-position format with a floating point in form of a (1+k+q·n)-element vector.

EFFECT: high rate of computation by replacing the operation of multiplying t-bit position mantissas of multiplicands with n concurrently executed operations of multiplying q-bit character positions of numbers in a residue number system.

The invention relates to computing, and is intended to perform the operation of multiplication of numbers represented in modular-point format floating-point universal multi-core processors.

Well-known iterative method for the multiplication of numbers represented in one of the positional binary formats floating point defined by IEEE-754. In this way the multiplication consists of a sequence of plies stacked mantis factors that are executed sequentially, adding order and addition modulo two signs of the cofactors. The sequence of plies stacked mantis factors as follows. When shifts the mantissa multiplier vacated bits are filled with zeros. If the first bit t bit position of the mantissa multiplier equal to one, then the rst term is the mantissa mnimogo, otherwise the rst term is equal to zero. If the second bit of the mantissa multiplier equal to one, then the second term is the mantissa mnimogo, shifted one digit to the left, otherwise the second term is zero. To the sum of the first and the second term is added to the mantissa mnimogo, shifted by two digits to the left, if the second bit of the mantissa multiplier equal to one, otherwise the added zero. Then to the resulting amount is added mantis mnimogo, shifted by three digits to the left, if the third bit of the mantissa multiplier equal to one, otherwise the added zero. And so on up to t-th digit of the mantissa multiplier, to the accrued amount is added to the mantissa mnimogo, shifted by v bits to the left, if the t-th bit of the mantissa multiplier equal to one, otherwise the added zero. In the end, the cumulative sum is the desired product of mantis factors. Next is the addition of the offset positional-order cofactors, thereby it turns out the order of the result. The sign of the result is determined by adding modulo two the signs of the cofactors.

The disadvantage of the iterative method of multiplying the positional binary floating-point numbers is that, first, by multiplying mantis is t-1 operations of summation of the t-bit operands. If we accept that the operation of summing the t-bit operands is performed for the t clock cycles, then the total execution time of the multiplication of mantis positional operands of the floating point will be t·(t-1) clock cycles. Secondly, the process of forming the sum is a serial process.

The technical result of the application of the method of managing the operation of multiplication of two numbers in modular-positional format floating-point universal multi-core processors is the appreciation is the speed of calculation by replacing the multiplication by t-bit positional mantis factors n parallel operations performed by multiplying the q-bit znakomity numbers in the number system of residual classes,
and q≈t/n. If you take the time summation pair of t-bit numbers t clock cycles of the processor, and during summation pair of q-bit numbers q clock cycles of the processor, provided that the number of computational cores, universal multi-core processor is not less than n, and the multiplication operation of the q-bit numbers can be done by q-1 addition operations q-bit numbers, the maximum acceleration of computing S is:

Description how to perform the operation of multiplication of two numbers in modular-positional format floating-point universal multi-core processors: an implementation of the method is carried out by applying the set of electrical, neural or other signals to control devices, each computing core multi-core processor universal purpose, which, in accordance with these signals form the control commands for operating devices of the respective cores.

In the positional binary formats floating point IEEE-754 any material the number seems to be three-element set:

[M,e,S|M∈[0,2),e∈[e_{min}e_{max}],S∈{0,1}], | (1) |

where M is a rational mantissa, e is the order number, e_{min}=2-2^{w-1}and e_{max}=2^{w-1}-1, s is the sign of the number.

The magnitude of the numbers recorded in this format, is expressed by the formula -1^{s}·M·2^{e}. Machine representations of numbers of the form (1) are (w+t+1) - bit binary vectors 〈sr_{w}...r_{2}r_{1}d_{t}...d_{2}d_{1}〉, where discharges c d_{1}for d_{t}dedicated to the representation of a rational binary mantis M=d_{t}·d_{t-1}...d_{2}d_{1}the bits with r_{1}, r_{w}are allocated to the binary representation of the integer-order e written in the form of excess E=r_{w}r_{w-1}...r_{2}r_{1}=e+e_{max}the category of s expresses the sign of the number.

We define the integer mantissa M'=d_{t}d_{t-1}...d_{2}d_{1}as t-bit nonnegative integer binary number, such that M=M'·2^{1-t}. Define moved the order of λ as a binary integer signed integer, such that λ=e-t+1, where e is a w-bit magnitude of the number represented in binary format (1).

Set n positive integer q-bit basis system of residual classes R_{1},R_{2},...,R_{n}such that ∀i_{1},i_{2}∈{l,2,...,n},i_{1}≠i

Integer mantissa M'=d_{t}d_{t-1}...d_{2}d_{1}to convert to a system of residual

class with the specified reason R_{1},R_{2},...,R_{n}thereby modular mantissa_{1},m_{2},...,m_{n}〉:

where m_{i}∈[0,p_{i}-1], i=1,2,...,n - q-bit numbers (modular bits) modular mantissa_{1},R_{2},...,R_{n},_{i}.

Thus, the floating point of the form (1) can be converted to the next modular-positional format:

where (m_{1},m_{2},...,m_{n}is a set of znakomity (modular bits) modular mantissa

The range of values of modular mantis_{1},m_{2},...,m_{n}〉 in the system of residual classes with the bases of p_{1},R_{2},...,R_{n}the interval of_{1}.d_{t-1}...d_{2}d_{1}can be represented in the system of residual classes a set of n mutually independent q-bit znakomity 〈m_{1},m_{2},...,m_{n}〉, with q≈t/n (for the case if all bases R_{1},R_{2},...,R_{n}q-bit).

Examples of positional conversion is of floating-point numbers in modular-positional format: let the numbers presented in 10-bit binary format of the form (1),
which under the offset arrangement E is given four bits (the maximum order of e_{max}=2^{4-1}-1=7, respectively, e=e-7), under the fractional part of the mantissa is five bits (i.e. t=6, and the integer part of d_{6}rational mantissa M is not explicitly written) and under the sign of the number - one bit. Let to represent modular mantis in modular-positional format [〈m_{1},m_{2},...,m_{n}〉,λ,s] used three reasons: p_{1}=3=2^{2}-1, p_{2}=7=2^{3}-1, p_{3}=31=2^{5}-l.

Example 1: you want to convert the number X=[1.5,-1,0]=-1°·1.5·2^{-1}represented in binary format [M,e,s], modular-positional format [〈m_{1},m_{2},...,m_{n}〉,λ,s]**.**

With account taken of the characteristics of the binary format [M,e,s], X will be recorded in computer memory as a binary vector 〈0011010000〉. For his conversion to modular-positional format (2) you must perform the following steps:

1. Highlight the part of a number, X: number sign s=0, the fractional part of the rational mantissa d_{5}...d_{2}d_{1}=10000_{2}shifted (redundant) order E=0110_{2}=6.

2. To recover the integer part of d_{6}the mantissa M=d_{6}.d_{5}...d_{2}d_{1}: d_{6}=1, because E>0, hence M=1.10000_{2}.

3. To determine the order of e: e=e-e_{max}=6-7=-1, because F>0.

4. To determine displaced positional order λ and alocale the ing the mantissa M':λ=e-t+1=-1-6+1=-6,M'=d_{
6}d_{5}...d_{2}d_{1}=110000_{2}=48.

5. Find modular mantissa_{1},m_{2},m_{3}〉:_{3},|48|_{7},|48|_{31}〉=〈0,6,17〉.

The result is a number X represented in modular-point format floating-point: X=[〈0,6,17〉,-6,0]=-1^{0}·〈0,6,17〉·2^{-6}.

Example 2: you want to convert the number X=[0.625-6,1]=-1^{1}·0.625·2^{-6}from binary format [M,e,s] modular-positional format [〈m_{1},m_{2},...,m_{n}〉,λ,s].

With account taken of the characteristics of the binary format [M,e,s], X will be recorded in computer memory as a binary vector 〈1000010100〉. For his conversion to modular-positional format (2) you must perform the following steps:

1. Highlight the part of a number, X: number sign s=1, the fractional part of d_{5}...d_{2}d_{1}=10100_{2}shifted the order of E=0000_{2}=0.

2. To recover the integer part of d_{6}the mantissa M=d_{6}·d_{5}...d_{2}d_{1}: d_{6}=0, since E=0, hence M=0.10100_{2}.

3. To determine the order of e: e=e_{min}=2-2^{4-1}=-6, since E=0.

4. To determine the moved order λ and the integer mantissa M': λ=e-t+1=-6-6+1=-11, M'=d_{6}d_{5}...d_{2}d_{
=0101002=20.}

5. Find modular mantissa_{1},m_{2},m_{3}〉:_{3},|20|_{7},|20|_{31}〉=(2, 6, 20). The result is a number X represented in modular-point format floating-point: X=[〈2, 6, 20〉,-11,1]=-1^{1}·〈2, 6, 20〉·2^{-11}.

Let A=[〈_{A},S_{A}], B=[〈_{B},S_{B}] - the numbers presented in modular-point format floating-point, where_{A},S_{A}],_{B},S_{B}] - modular mantissa of the numbers a and b, respectively. Then the method of multiplication C=A·In numbers a and b, presented in modular-point format floating point (2), on the universal k-bit processor containing g cores, is defined as follows.

1. The multiplier A=[〈_{A},S_{A}] and the multiplicand B=[〈_{B},S_{B}]presented in modular-point format floating-point load in the universal k-bit processor, containing g cores, as follows:

1.1. If the number g of computing cores exceeds the number n of basis p_{1},R_{2},...,R_{n}the system of residual classes used to represent modular is mantis

in the first nucleus of the universal multi-core processor load q-bit binary representation of the first znakomity

the basis of the system of residual classes pi, the width q of which does not exceed the size of the k bit of grid processor;

in parallel with this, the second core universal multi-core processor load q-bit binary representation of the second znakomity_{2}the width q of which does not exceed the size of the k bit of grid processor; etc.;

in parallel with this, in the n-th core universal multi-core processor load q-bit binary representation of the n-th znakomity_{n}the width q of which does not exceed the size of the k bit of grid processor;

in parallel with this, in the (n+1)-th core universal multi-core processor load k-bit binary magnitude λ_{A}and λ_{B}and marks s_{A}and s_{B}numbers a and b, respectively.

1.2. If the number n of basis p_{1}p_{2},...,p_{n}the system of residual classes used to represent modular mantis

q - bit binary representation of the first znakomity_{1}load in the first nucleus of the universal multi-core processor;

in parallel with this, the q-bit binary representation of the second znakomity_{2}download the second core universal multi-core processor; etc.;

in parallel with this, the q-bit binary representation (g-1)-th znakomity_{g-1}download (g-1)-th core universal multi-core processor;

q - bit binary representation of g's znakomity_{g}load in the first nucleus of the universal multi-core processor;

q - bit binary representation of (g+1)-th znakomity_{g+1}download the second core universal multi-core processor;

and so on until you have downloaded n s of znakomity

in parallel with this, the k-bit binary magnitude λ_{And}and λ_{B}and marks s_{A}and s_{B}numbers a and b, respectively, are loaded into the g-oe core universal multi-core processor.

2. After the multiplier A=[〈_{A},S_{A}] and the multiplicand B=[〈_{B},S_{B}]presented in modular-point format floating point is th,
loaded in a universal k-bit processor, containing g cores, the operation of their multiplication is as follows:

2.1. If the number g of computing cores exceeds the number n of basis p_{1}p_{2},...;p_{n}the system of residual classes used to represent modular mantis

- in the first computer processor core executes the operation of integer multiplication_{
1}q-bit binary representations of znakomity

in parallel with this, the second computing core processor runs_{2}q-bit binary representations of znakomity

in parallel with this, the n-th computing processor core executes the multiplication operation_{n}q-bit binary representations of znakomity

pair is in parallel with this,
in the (n+1)-th computing core processor is the addition of binary orders of magnitude λ_{A}and λ_{B}and the addition modulo two s_{C}=|s_{A}+s_{B}|_{2}marks s_{A}and S_{B}numbers a and b, respectively.

2.2. If the number n of basis p_{1}p_{2},...,p_{n}the system of residual classes used to represent modular mantis_{j}znakomity

**and****,**i=0,1,...,w_{1}-1, then:

in the first computing core processor sequentially performs the operations of multiplication_{i·(g-1)+1}, i=0,1,...,w_{1}-1, g-razryadnikh binary representations of all w_{1}downloaded it znakomity_{1}-1 modular mantis

is the greatest integer not exceeding

in parallel with this, the second computing core processor consistently performsthe multiplication

the modules p_{i·(g-1)+2}, i=0,1,...,w_{2}-1, q-bit binary representations of all w_{2}downloaded it znakomity_{2}-1**,**modular mantis

- in parallel, in (g-l)-M computing core processor sequentially performs the operations of multiplication_{(i+1)·(g-1)}, i=0,1,..., w_{g-1}-1, q-bit binary representations of all W_{g-1}downloaded it znakomity_{g-1}-1 modular mantis

in parallel with this, in g-m computing core processor is the addition of binary orders of magnitude λ_{A}and λ_{B}and the addition modulo two s_{C}=|s_{A}+s_{B}|_{2}marks s_{A}and s_{B}
numbers a and b, respectively.

As a result of performing these operations is obtained the product

Example: it is necessary to perform a multiplication operation C=A·In modular-point format floating-point universal processor containing four 5-bit calc the positive nucleus.
To represent mantis operands are specified, the following 5-bit base system of residual classes: p_{1}=3=2^{2}-1, p_{2}=7=2^{3}-1, R_{3},=31=2^{5}-1, P=p_{1}·p_{2}·p_{3}=65l - piece bases (the upper limit of the allowable range view of modular mantis). The factors specified in modular-positional format as follows: A=[〈2,4,11〉,-4,1], B=[〈2,3,17〉,2,0].

1. The multiplier A=[〈2,4,11〉,-4,1] and the multiplicand B=[〈2,3,17〉,2,0] download universal 5-bit processor with four computing cores, as follows:

in the first kernel is loaded the first znakomitsya_{1}=3;

in parallel with this, the second kernel loadable second znakomitsya_{2}=7;

in parallel with this, in the third nucleus downloadable third znakomitsya_{3}=31;

in parallel with this, the fourth core universal multi-core processor loaded 5-bit binary magnitude λ_{A}=-4 and λ_{B}=2, and marks s_{A}=1 and s_{B}*=*0*.*

2. As the number of acyclically processor cores exceeds the number of bases of p_{
1},R_{2},...,p_{n}the system of residual classes used to represent modular

mantis

- in the first computer processor core operation

integer multiplication modulo p_{1}:

in parallel with this, the second computing processor core operation integer multiplication modulo p_{2}:

in parallel with this, the third computing processor core operation integer multiplication modulo p_{3}:

in parallel with this, the fourth computing core processor running add the binary orders of magnitude λ_{A}and λ_{B}and the addition modulo two s_{C}=|s_{A}+s_{B}|_{2}marks s_{A}and s_{B}numbers a and b, respectively: λ_{C}=λ_{A}+λ_{B}=-4+2=-2, s_{C}=|s_{A}+s_{B}|_{2}=|1+0|_{2}=1.

In the result the result C=[〈1,5,1〉, of-2.1] modular-point format floating-point corresponding to the positional number -1^{1}·187·2^{-2}.

If taken during the addition of a pair of the q-bit residue q quanta of the universal processor containing g k-bit cores, and q≤k, then the calculation works t-bit mantics of floating point numbers a and b, at t≈q·n in the limiting case (when_{i}, i=1,2,...,n) no described method is q·(q -1) cycles, whereas the time multiplying the iterative method is equal to t·(t-1)≈q·n·(q·n-1) clock cycles. To calculate the magnitudes and signs of the operands will need k cycles (k-1 tact to sum orders, and 1 stroke for summation signs), and their calculation will be carried out in parallel with calculation of znakomity modular mantis, so the time to compute orders of magnitude and signs of the result of multiplying the floating-point operands is ignored. Thus, while the multiplication of floating point numbers on the basis of the described method in

The way organizations perform the operation of multiplication of two numbers in modular-positional format floating-point universal multi-core processors, namely, that:

universal multi-core solver contains g k-bit cores, each of which provides a system of f operations, which include operations algebraic multiplication and algebraic addition on numbers represented in positional integer data formats;

when organizing the operations of multiplying each number, the multiplier and the multiplicand, is presented in modular-point format floating-point in the form (1+k+q·n) - element vector, where:

the first left digit of s is a senior rank in the format of a number, and is given by the sign of the number, and if s=0 then the number is positive, if s=1 then the number is negative;

following the first discharge s number k of bits allocated for storage of positional order of numbers representing a binary integer number of λ with the sign of s_{λ}varying finite floating-point numbers in the range λ_{min}≤λ≤λ_{max}and the resulting conversion of the number of positional floating-point format by the expression λ=e-t+1, where e defines what elicina numbers in binary positional notation a floating-point expression (-1^{
s}·M·2^{e}) if 0≤M<2, which is rational t-bit mantissa of a number in binary positional floating-point format, λ_{min}=2-2^{k-1}, λ_{max}=2^{k-1}-2 if s_{λ}=0 the order of λ is positive, and if s_{λ}=1 order λ is negative;

following the (k+1) discharge q·n bits, with q≤k, are assigned to represent the mantissa of the number of_{1}, R_{2}, ..., p_{n}, n is the number of znakomity mantissa, q - bit width of each znakomitsya; moreover, each i-th znakomitsya, where 1≤i≤n, appears to be a non-negative integer number m_{i}in binary positional notation; the value of m_{i}each i-th znakomitsya is determined by the expression^{t-1}M - the diet is supplemented flax t-bit mantissa of a number in binary positional floating-point format,_{i};

the range of modular mantissa

values of the order of λ and mantissa_{1},m_{2},...,m_{n}〉] are respectively in the following ranges: 2-2^{k-1}≤λ≤2^{k-1}-2, 〈0_{1},0_{2},...,0_{n}〉≤_{1}-1) (p_{2}-1),...,(p_{n}-1)〉;

values of the order of λ and mantissa^{k-1}≤λ≤2^{k-1}-2, 〈0_{1},0_{2},...,0_{n}〉≤_{1}-1) (p_{2}-1),...,(p_{n}-1)〉;

the value of positive infinity is represented in modular-positional format as follows: s=0, λ=λ_{max}+1=2^{k-1}-1,

the value is negative infinity is represented in modular-positional format as follows: s=1, λ=λ_{max}+1=2^{k-1}-1,

for positive non-numeric values (NaN) in modular-positional format [s,λ,〈m_{1},m_{2},...,m_{n}〉], when s=0, the value of the positional order of λ is determined by the expression λ=λ_{max}+1=2^{k-1}-1, and the values of the mantissa_{1},1_{2},...,1_{n}〉≤_{1}-1) (p_{2}-1),...,(p_{n}-1)〉;

for negative non-numeric values (NaN) in modular-positional format, when s=1, the value of the positional order of λ is determined by the expression λ=λ_{max}+1=2^{k-1}-1, and the values of the mantissa_{1},1_{2},...,1_{n}〉≤_{1}-1) (p_{2}-1),...,(p_{n}-1)〉;

values in modular-positional format, there is the following positional value of the order λ=λ_{
min}-1=1-2^{k-1}when changing the values of the modular mantissa in the range 〈1_{1},1_{2},...,1_{n}〉 ≤_{1}-1) (p_{2}-1),...,(p_{n}-1)〉, are for advanced coding exceptional situations that may arise in the calculation process, namely: loss of order and full order;

the signal processor multiplier

provided that g≥n+1, i.e. if the number of computational poison the p processor exceeds the number of bases of the system of residual classes,
used to represent modular mantis

in the first nucleus of the universal multi-core processor load q-bit binary representation of the first znakomity_{1};

in parallel, the second core universal multi-core processor load q-bit binary representation of the second znakomity_{2}; in parallel, in the third ÷ n-th core universal multi-core processor load q-bit binary representation of third ÷ n's znakomity_{3}÷p_{n};

in parallel, in the (n+1)-th core universal multi-core processor load k-bit binary magnitude λ_{A}and λ_{B}and marks s_{A}and s_{B}numbers a and b, respectively;

provided that g<n+1, i.e. if the number of bases of the system of residual classes used to represent modular mantis

q-bit binary representation of the first znakomity_{1}load in the first nucleus of the universal multi-core processor;

in parallel, the q-bit binary representation of the second znakomity_{2}download the second core universal multi-core processor;

in parallel, similarly loaded q-bit binary representation of third ÷(q-1)-th znakomity_{3}÷p_{g-1}in the third ÷(g-1)-th core universal multi-core processor;

q-bit binary representation of g's znakomity_{g}load in the first nucleus of the universal multi-core processor;

similarly, the q-bit binary representation of (g+1)-th znakomity_{g+1}download the second core universal multi-core processor;

the cyclic process the download continues until you have downloaded n s of znakomitsya

in parallel, the k-bit binary magnitude λ_{A}and λ_{B}and marks s_{A}and s_{B}numbers a and b, respectively, are loaded into the g-oe core universal multi-core processor;

after multiplier

floating point loaded in a universal k-bit processor, containing g-cores, the operation of their multiplication is as follows:

provided that g≥n+1, i.e. if the number of computing cores exceeds the number of bases of the system of residual classes used to represent modular mantis

in the first computer processor core executes the operation of integer multiplication_{1}q-bit binary representations of znakomity

in parallel, the second computing processor core in a similar way is the multiplication operation_{2}q-bit binary representations of znakomity

in parallel with this, in the third ÷ n-th computing core processor works in a similar manner the multiplication operation_{3}÷p_{n}q-bit binary representations of the EIT is oposici

in parallel with this, in the (n+1)-th computing core processor is the addition of binary orders of magnitude λ_{A}and λ_{B}and the addition modulo two s_{C}=|s_{A}+s_{B}|_{2}marks s_{A}and s_{B}numbers a and b, respectively;

provided that g<n+1, i.e. if the number of bases of the system of residual classes used to represent modular mantis_{j}znakomity_{j}-1, then:

in the first computer processor core for all i=0,1,...,w_{1}-1 sequentially performs the operations of multiplication_{i·(g-1)+1}, q-bit binary representations of all w_{1}downloaded it znakomity

in parallel, the second computing processor core in the same way for all i=0,1,...,w_{2}-1 sequentially performs the operations of multiplication_{i·(g-1)+2}, q-bit binary representations of all w_{2}downloaded it znakomity

in parallel with this the m in the third ÷(g-1)-M computing processor core in the same way consistently for all i=0,1,...,w_{
3}-1÷i=0,1,...,w_{g-1}-1 performs a multiplication operation_{i·(g-1)+3}÷p_{(i+1)·(g-1)}q-bit binary representations of all w_{3}÷w_{g-1}downloaded znakomity

in parallel, in g-m computing core processor is the addition of binary orders of magnitude λ_{A}and λ_{B}and takinogawa modulo two s_{
C}=|s_{A}+s_{B}|_{2}marks s_{A}and s_{B}numbers a and b, respectively;

as a result of performing these operations is obtained the product of

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3 cl, 6 dwg, 3 tbl

FIELD: information technology.

SUBSTANCE: device for generating remainder on arbitrary modulus of a number has first and second registers, a group of AND elements, a unit of half-adders and a delay element, where the device also includes (K-1) half-adders, to whose second data inputs a modulus code is transmitted, and a number code "1" is transmitted to the first data input of the first half-adder and the second data input of the group of AND elements, the output of the i-th half-adder is connected to the second data input of the group of AND elements and with shift of one bit towards the most significant bits to the first data input of the i+1 half-adder, where i=1,…,K-2, the K-1 output of the half-adder is connected to the second data input of the group of AND elements.

EFFECT: cutting the size of equipment.

2 dwg

FIELD: information technologies.

SUBSTANCE: invention may be used in digital computing devices, and also in devices to generate elements of end fields and in cryptographic applications. The device comprises summators, multipliers, inverters and multiplexors.

EFFECT: expanded range of input number values.

1 dwg

FIELD: computers.

SUBSTANCE: device has N blocks for calculating remainders, each of which has N devices for calculating remainders from bases of modular notation scale, including multiplication blocks, module adders of 3N numbers and tabular calculators.

EFFECT: higher speed of operation.

5 dwg, 1 ex

FIELD: computer science.

SUBSTANCE: device has harmonic signal generator, controlled phase changers, means for measuring phase of harmonic signal, phase changers for fixed phase values, transformers of binary number code to unary in accordance to first and second sub-modules, coder and table calculation means.

EFFECT: lower costs.

3 dwg

FIELD: computer science, possible use for engineering of signals processing microprocessors, and of digital filters.

SUBSTANCE: device uses neural-network technologies and polynomial residuals system, wherein as system base minimal polynomials p_{i}(z), where input=1,2,...,n, are utilized, determined in expanded Galois fields GF(2^{V}), while device has clock counter, two blocks for calculating sums of paired results of multiplication by arbitrary base, error correction block, modular adder and block for calculating sums of paired results of multiplication based on control base.

EFFECT: decreased hardware requirements, improved speed of operations.

2 dwg, 3 tbl

FIELD: automatics and computer science, possible use for engineering of computing structures functioning in modular computation system.

SUBSTANCE: device has encoder, controlled phase shifter, harmonic signal generator, phase shifters for fixed phase value, device for measuring the phase of harmonic signal, multiplexer, commutator, amplitude detector and harmonic signal amplifier.

EFFECT: simplified construction of device.

3 dwg

FIELD: computer science, in particular, modular neuron-computer means.

SUBSTANCE: network has input layer of neurons, neuron network of end ring for determining number rank, neuron network of end ring for calculating remainder at base n+1, n-neuron networks of end ring for calculating scaled number, neuron network for calculating difference in numbers between input remainders and base remainder.

EFFECT: decreased volume of equipment, increased speed of numbers rounding and expanded functional capabilities.

1 dwg

FIELD: cryptographic method and chip-card for encoding information, methods for creating electronic signatures.

SUBSTANCE: at least one calculation step is performed, providing for realization of E operation of modular exponentiation in accordance to formula E=x^{d}(mod p·q), where d and mod p·q are components of a secret key, while parallel represent first simple multiplier, q is second simple multiplier, d is level coefficient, and x represents base, while operation E of modular exponentiation is performed in accordance to Chinese theorem about remainders.

EFFECT: decreased amount of computing operations and machine time costs during simultaneous increase of level of data protection from unsanctioned access.

4 cl

FIELD: computer science, possible use in computing devices functioning in system of remainder classes, and also communication equipment for transferring information in remainder classes system codes.

SUBSTANCE: device contains a group of constant memorizing devices, a group of registers, discharge-parallel modulus adder.

EFFECT: decreased volume of equipment and increased speed of operation when transforming a number from remainder classes system to positional code.

1 dwg

FIELD: computer engineering, possible use in digital computing devices, and also in devices for forming elements of finite fields.

SUBSTANCE: device contains adders, inverters, multipliers, multiplexer.

EFFECT: expanded functional capabilities due to expanded range of input number values.

1 dwg

FIELD: computer engineering, possible use in digital computing devices, and also in devices for forming finite field elements.

SUBSTANCE: device contains multiplier, adders, inverters, constant multipliers, multiplexer.

EFFECT: expanded functional capabilities.

1 dwg

FIELD: computer engineering, possible use in digital computing devices for forming code series, creation of which is based on finite fields theory.

SUBSTANCE: device contains block for forming partial remainders, modulus multiplexers, modulus adders.

EFFECT: expanded functional capabilities due to creation of remainders by double modulus, by calculating partial remainders from polynomial powers with their following addition in acc to coefficients of polynomial powers.

3 dwg