Semiconductor device and method of its manufacturing

FIELD: electricity.

SUBSTANCE: semiconductor device comprises a thin-film transistor comprising a gate bus, the first insulating film, an oxide-semiconductor layer in the form of an island, the second insulating film, a source bus, a drain electrode and a passivating film, and also a contact site, comprising the first connection element, made of the same conducting film as the gate bus, the second connecting element made from the same conducting film as the source bus and the drain electrode, and the third connection element formed on the second connection element. The second connection element contacts with the first connection element in the first window provided in the first and second insulating films, the third connection element contacts with the second connection element in the second window provided in the passivating film, and the second connection element covers the end surfaces of the first insulating film and the second insulating film in the first window, but does not cover the end surface of the passivating film in the second window. As a result the conical shape of the contact hole of the contact site may be controlled with high accuracy.

EFFECT: reduced damage of a mask.

17 cl, 14 dwg

 

The technical FIELD

The present invention relates to a semiconductor device containing a thin-film transistor, and method of its manufacture.

The LEVEL of TECHNOLOGY

In General liquid crystal display device or an organic electroluminescent (EL) display device has an active matrix, includes: a substrate on which thin-film transistor (thin film transistor; hereinafter “TFT”) is formed as a switching element for each pixel (hereinafter “TFT substrate”); protivopolojno, on which are formed a counter-electrode, color filters, etc.; and an optical modulation layer, for example, a liquid crystal layer provided between the TFT substrate and protivopoloznoj.

On the TFT substrate are formed a lot of tire source, many tires shutter and many TFT, located, respectively, at the intersections between them, pixel electrodes for applying voltage to the optical modulation layer, such as a liquid crystal layer, bus storage capacitor and the storage capacitor electrodes, etc. in Addition, in the terminal portion of the TFT substrate provided with a pad to ensure appropriate bus connections of the source and tires shutter with the input contacts of the control circuit. Control the second scheme can be performed on the TFT substrate or on a substrate (circuit Board).

The design of the TFT substrate is described, for example, in Patent document 1. Below with reference to the drawings describes the design of the TFT substrate described in Patent document 1.

Fig. 12(a) is a schematic view in section, on which in General shows a TFT substrate, and Fig. 12(b) is an enlarged view in section, showing one pixel of the TFT substrate. Fig. 13 is a view in section of a TFT and the contact pads of the semiconductor device shown in Fig. 12.

As shown in Fig. 12(a), a TFT substrate includes many tires shutter 2016 and many tire source 2017. Each area 2021, surrounded by these tyres in 2016 and 2017, defines the boundary of the "pixel". In the area 2040 TFT substrate outside the area (display area)in which the generated pixels, provides many connecting elements 2041 to ensure proper connection of multiple tires shutter 2016 and tire 2017 source with the control scheme. Each connecting element 2041 forms a contact pad for providing connection to the external interconnects. In the present description, the region 2040 TFT substrate, which provides many pads, called "staging area of the electrodes.

As shown in Fig. 12(b) and Fig. 13, provides a pixel electrode 2020, however, h is usually used to close each area 2021, defines the boundary of the pixel. In addition, in each region 2021 TFT is formed. The TFT includes a gate electrode G, an insulating film shutter 2025 and 2026, closing the gate electrode G of the semiconductor layer 2019, located on the insulating film shutter 2026, and the source electrode S and drain electrode D, in that order connected with both end parts of the semiconductor layer 2019. TFT is covered with a passivating film 2028. Between the passivating film 2028 and a pixel electrode formed 2020 interlayer insulating film 2029. The source electrode S of the TFT is connected with the bus 2017 source, and the gate electrode G is connected to the bus shutter 2016. The drain electrode D is connected with the pixel electrode 2020 in the contact hole 2030.

In addition, the parallel bus shutter 2016 is formed by the storage capacitor bus 2018. Tire storage capacitor 2018 is connected with a storage capacitor. When this storage capacitor is composed of a storage capacitor electrode 2018b, which is made of the same conductive film as the electrode of the drain electrode of the storage capacitor a, which is made of the same conductive film as the gate electrode, and an insulating film shutter 2026 placed between them.

On the connecting element 2041 passing from each bus shutter 2016 or bus source is 2017, insulating film shutter 2025 and 2026 and piscivorous film 2028 are not formed, but is formed a connecting bus 2044 in order to come into contact with the top surface of the coupling element 2041. This provides electrical connection between the connecting element 2041 and connecting bus 2044.

As shown in Fig. 13, in the liquid crystal display device has a TFT substrate 2013 is positioned so that it opposes the 2014 substrate on which are formed a counter-electrode and color filters, while between them is placed a liquid crystal layer 2015.

When manufacturing such a TFT substrate region 2021, which should be the pixels (also called "pixel sites") and contact pads preferably are formed using a single process in order to reduce the increase in the number of masks and the number of stages.

With the aim of producing the above-mentioned TFT substrate must be corroding the parts of the insulating films of the gate 2025 and 2026 and a passivating film 2028, which are located in the area of the electrode 2040, and plots insulating film shutter 2025 and a passivating film 2028, which are located in areas in which to form storage capacitors. In Patent document 1 describes the formation of the interlayer insulating plait the key 2029 by using the organic insulating film and by using it as a mask, mytravelguide insulating film 2025 and 2026 and piscivorous film 2028.

On the other hand, in recent years, it was proposed to form an active layer of a TFT by using a film of an oxide semiconductor such as zinc oxide, instead of the film of silicon semiconductor. Such a TFT is called "oxide semiconductor TFT. The oxide semiconductor has a higher mobility of carriers than amorphous silicon. Therefore, the oxide semiconductor TFT can operate faster than amorphous-silicon TFT. In addition, the oxide semiconductor film is formed by using a simpler process than the film of polycrystalline silicon and, therefore, also applicable to devices that require a large area.

However, in the process of manufacturing oxide semiconductor TFT having the structure with the lower gate, the electron-carriers can occur due to oxygen defects at the stage of heat treatment or something similar, for example, giving a lower resistance. There is also a problem, which is that the underlying oxide semiconductor film is susceptible to damage during etching of the electrodes of the source/drain and the step of forming the interlayer insulating film.

On the other hand, was proposed structure (protection channel), which provides the W protective film channel with the to close region of the semiconductor layer in which to form the channel (channel formation). In the manufacturing process of TFT in the formation of electrodes and source/drain after the formation of the protective film channel in the semiconductor layer protective film channel function as an etching stopper when performing etching for forming electrodes and source/drain. As a result of this can be reduced the damage which may be received by the region of the channel formation during etching.

In Patent document 2 describes the design of the pixel areas a TFT substrate having a TFT type protection channel. However, the TFT in the Patent document 2 is formed using a silicon film.

Fig. 14 is a view in section, showing a portion of the TFT substrate described in Patent document 2. Each pixel of the TFT substrate provides a thin-film transistor 1141 and storage capacitor 1142. In the thin-film transistor 1141 are formed bus shutter 1102, an insulating film shutter 1104, the semiconductor layer 1113, having a region forming a channel protective film channel 1108, Itokawa region 1118, a drain region 1117 and the drain electrode 1121 and bus source 1122. Thin-film transistor 1141 covered with a passivating film 1127, and the passivating film 1127 include arrivalsa pixel electrode 1131. In the contact hole, which is formed on the passivating film 1127, a pixel electrode 1131 is connected with the drain electrode 1121. Storage capacitor 1142 consists of an insulating film shutter 1104 and a passivating film 1127 placed between the electrodes as a dielectric, the electrodes are bus capacitor 1151, which is formed from the same conductive film as the bus shutter 1102 and a pixel electrode 1131.

In the present description, the insulating film which is formed between the channel formation and the electrode of the source/drain semiconductor layer, called "protective film channel" or "stop etch", and any insulating film covering the TFT, or thin film, which is formed on the electrode of the source/gate in the case of the structure with the lower shutter, called "passivating layer" simply to distinguish them.

Although not shown, the contact platform in the TFT-substrate-bus shutter 1102 may be electrically connected to the external interconnects provided on the passivating film 1127, in the contact hole, which is formed in the passivating film and 1127 insulating film shutter 1104 over the bus shutter 1102.

In the aforementioned method of manufacturing the semiconductor device performs the etching DL the formation of a protective film channel 1108, the etching for forming electrodes and source/drain 1121 and 1122 and the etching for forming contact openings in the passivating film 1127 (Fig. 7 - 9 the Patent document 2). It is assumed that the contact hole in the contact area is formed by providing simultaneous etching of the passivating film and 1127 insulating film shutter 1104 when the etching of the passivating film 1127.

In patent document 3 using grayscale masks available in the method of manufacturing a TFT substrate having a TFT type protection channel, and it is necessary to reduce the number of masks. However, the method of Patent document 3 involves a complex manufacturing process and can reduce the suitability for mass production. In addition, because between the gate electrode and the electrodes of the source/drain is formed by only one layer of insulating film, there is a possibility that between these electrodes may short circuit.

The LIST of BIBLIOGRAPHIC REFERENCES

PATENT LITERATURE

[Patent document 1]: lined publication of the Japan patent No. 2008-170664

[Patent document 2]: lined publication of the Japan patent No. 2009-157354

[Patent document 3]: lined publication of the Japan patent No. 2007-258675

The INVENTION

TECHNICAL PROBLEM

In ways, opican the x in Patent documents 1 and 2, on the contact area of the TFT substrate, the insulating film shutter and pisciverous the film should vytravlivaetsya at the same time. The authors of the invention in the course of the study it was found that the application of such methods to the TFT substrate having the oxide semiconductor TFT, will lead to the next problem.

In General, the oxide semiconductor TFT as an insulating film speed or passivating film is often used oxide film such as a film of SiO2. This is because when the oxide semiconductor layer arise oxygen defects, these oxygen defects can be corrected by oxygen contained in the oxide film.

In accordance with the Patent document 1, for manufacturing a TFT substrate (Fig. 12, Fig. 13), the interlayer insulating film 2029 is formed using an organic insulating film, and when it is used as a mask is etched portion of the insulating film shutter 2025 and 2026 and a passivating film 2028, which is located in the area of the electrode 2040, resulting in the contact hole is formed in the contact space. If material or an insulating film shutter 2025 and 2026, or a passivating film 2028 is used SiO2that will take a long time etching, since SiO2has a very low RMSE is ity etching. As a result of this organic insulating film (interlayer insulating film) 2029 serving as the mask may be damaged.

In patent document 2, a contact hole on the pad presumably formed using resistol mask by providing simultaneous etching of the passivating film and 1127 insulating film shutter 1104. In this case, if the material or passivating film 1127, either the insulating film of the gate 1104 is used SiO2very low rate of etching of SiO2can lead to the possibility that at the stage of etching resista mask may be damaged, thereby preventing removal resistol mask. In addition, the low etching rate hinders the formation of the desired conical shape on the surface of the walls of the contact holes on the pad so that the surface can become almost perpendicular to the substrate. In such cases, there is also the problem, which is that any tire that is formed in the contact hole of the contact pad can probably be broken.

Therefore, it is usually at the stage of etching when forming the source electrode or the gate electrode mask for etching may be corrupted or because of non-optimized tapered pin is TVersity disorders can occur tires, thus possibly resulting in reduced reliability of the TFT substrate.

The present invention is made considering the above circumstances, and its main task when forming contact holes in the contact area of the semiconductor device having oxide semiconductor TFT and the contact area to provide a connection electrode of the TFT with the external interconnect, is to reduce the damage of the mask and the control cone forms the wall surface of the contact hole with high accuracy.

SOLUTION

A semiconductor device in accordance with the present invention is a semiconductor device, comprising: a substrate; a thin-film transistor formed on the substrate; and a contact pad for electrical connection of the thin-film transistor with the external interconnect, and the thin-film transistor includes: bus shutter provided on the substrate; a first insulating film formed on the bus shutter; the oxide semiconductor layer in the shape of the island, formed on the first insulating film, and in the oxide semiconductor layer in the shape of the island has a channel region, and there are Itokawa region and a drain region located at opposite sides of the channel region; a second isolate the second film, provided in contact with the oxide semiconductor layer; bus source provided on the second insulating film and electrically connected to stokovoj region; a drain electrode provided on the second insulating film and electrically connected with the drainage area; and piscivorous film provided on the bus the source and the drain electrode and covering the thin film transistor, and the contact pad includes: a first coupling element, made of the same conductive film as the bus shutter; a second coupling element formed on the first connecting element and made of the same conductive film as the bus of the source and the drain electrode; and the third coupling element formed on the second connecting element, and in the first window provided in the first insulating film and the second insulating film, the second coupling element is in contact with the first connecting element; the second window provided in the passivating film, the third coupling element is in contact with the second connecting element; and a second connecting member covers the end surface of the first insulating film and the second insulating film in the first window, but does not cover the end surface passivating film in which the PR box.

In a preferred embodiment, the second window is located inside the first box, when viewed from a direction normal to the substrate surface.

May be further include a pixel electrode, electrically connected with the drain electrode, and the third coupling element may be made of the same conductive film as the pixel electrode.

The preferred implementation further comprises a storage capacitor formed on the substrate, and the storage capacitor includes: bus storage capacitor, made of the same conductive film as the bus gate; a first insulating film covering the storage capacitor bus; a semiconductor layer for forming the storage capacitor, and the semiconductor layer is made of the same oxide semiconductor film, and the oxide semiconductor layer; and a storage capacitor electrode provided on the semiconductor layer for forming the storage capacitor, the storage capacitor electrode is in contact with the semiconductor layer for forming the storage capacitor in the window formed in the second the insulating film.

In a preferred embodiment, the electrode cumulative to the of henstra is a part of the drain electrode; and a pixel electrode in contact with the electrode of the storage capacitor in the window formed in the passivating film.

In a preferred embodiment, the storage capacitor electrode is a part of the pixel electrode.

May be further include coupling element, the gate-source for electrical connection of the bus speed and bus source, with the connecting element, the gate-source bus source may come into contact with the tire of the shutter in the first window provided in the first insulating film and the second insulating film.

Between the passivating film and the pixel electrode may be further included organic insulating film.

Preferably, at least one of the films - the first insulating film and a passivating film contains SiO2.

The first insulating film may have a multilayer structure comprising a film of SiO2and the SiNx film, and the film of SiO2is the top layer of the multilayered structure and is in contact with the bottom surface of the oxide semiconductor layer.

Piscivorous film may have a multilayer structure comprising a film of SiO2and the SiNx film, and the film of SiO2is the lower layer of the multilayer structure.

In a preferred embodiment, assests the tion, at least the first insulating film and the oxide semiconductor layer is provided between the upper surface and side wall of the tire valve and the tire source and between the upper surface and side wall of the tire valve and the drain electrode.

May additionally be provided with a second insulating film between the upper surface and side wall of the tire valve and the tire source and between the upper surface and side wall of the tire valve and the drain electrode.

Within the surface of the oxide semiconductor layer, the second insulating film may cover the entirety of the upper surface and the side wall except for the area of origin and area of flow and may be in contact with the top surface of the first insulating film near the side wall oxide semiconductor layer.

The width of the oxide semiconductor layer along the direction of the width of the channel may be greater than the width of the tires of the shutter in the direction along the width of the channel.

A method of manufacturing a semiconductor device in accordance with the present invention is a method of manufacturing any of the above described semiconductor device, comprising: (A) the step of forming a conductive film for bus gate on a substrate and forming a pattern of a conductive film for forming tires shutter p is pout of the connecting element; (C) a step of forming a first insulating film on the bus speed and the first connecting element; (C) a step of forming on the first insulating film oxide semiconductor layer, which should become the active layer of the thin-film transistor; (D) a step of forming a second insulating film covering the oxide semiconductor layer and the first insulating film; (E) a step of etching the first and second insulating films by using the oxide semiconductor layer as an etching stopper for forming the second insulating window film to form a contact source and open to form a contact flow thus that the oxide semiconductor layer is left unprotected from exposure through the Windows, and forming a first window in the second insulating film and the first insulating film so that the surface of the first conductive element is left unprotected from exposure through the first window; (F) a step of forming a conductive film for the electrode and source/drain of the second insulating film and forming a pattern of a conductive film for forming tires of the source, which is in contact with the oxide semiconductor layer within the window for the formation of the contact of the source, the drain electrode which is in contact with the oxide semiconductor with the OEM within the window for the formation of the drain contact, and the second connecting element, which is in contact with the first connecting element within the first window; (G) a step of forming a passivating film on the bus the source, the drain electrode and the second connecting element; (H) a step of forming a second window in the passivating film so that the second coupling element is left unprotected from exposure through the second window; and (I) the step of forming the third coupling element in the passivating film, and the third coupling element is in contact with the second connecting element within the second window.

Step (H) may include the step of forming a passivating film window for influencing the drain electrode; and step (I) may be a step of forming a transparent conductive film on the passivating film and the deposition of a transparent conductive film for formation of the third coupling element and the pixel electrode, and a pixel electrode in contact with the drain electrode within the window to expose the drain electrode.

USEFUL EFFECTS of the INVENTION

In accordance with the present invention, when forming a contact window in the pad of the semiconductor device having oxide semiconductor TFT and the contact area to ensure connectivity ele is trudov with the external interconnect, damage to the mask can be reduced by reducing the time of etching, while the cone shape of the wall surface of the contact hole can be controlled with high accuracy. As a result, the reliability of the semiconductor device can be improved.

In addition, the above-mentioned semiconductor device can be manufactured in a simple way without complicating the manufacturing.

BRIEF DESCRIPTION of DRAWINGS

[Fig. 1] (a)-(f) are phased in section, showing an example of a method of manufacturing a semiconductor device in accordance with embodiment 1 of the present invention.

[Fig. 2] the Horizontal projection of a semiconductor device in accordance with embodiment 1 of the present invention, in which (a) is a horizontal projection of pixel areas 101 of the semiconductor device; and (b)-(d) represent the horizontal projection of the gate electrode, the source electrode and the coupling element, the gate-source semiconductor device, respectively.

[Fig. 3] (a) is a view in section along the line I-I'shown in Fig. 2(a) and along the line II-II'shown in Fig. 2(b) or along the line III-III'shown in Fig. 2(C). (b) is a view in section along the line IV-IV'shown in Fig. 2(d).

[Fig. 4] (a)-() are phased in section, which shows an example of a method of manufacturing a semiconductor device in accordance with embodiment 2 of the present invention.

[Fig. 5] the Horizontal projection of a semiconductor device in accordance with embodiment 2 of the present invention, where (a) represents the horizontal projection of pixel pads 201 of the semiconductor device, and (b) - (d) represent the horizontal projection of the gate electrode, the source electrode and the coupling element, the gate-source semiconductor device, respectively.

[Fig. 6] (a) is a view in section along the line I-I'shown in Fig. 5(a) and along the line II-II'shown in Fig. 5(b) or along the line III-III'shown in Fig. 5(C). (b) is a view in section along the line IV-IV'shown in Fig. 5(d).

[Fig. 7] (a)-(C) are phased in section, showing an example of a method of manufacturing a semiconductor device in accordance with embodiment 3 of the present invention.

[Fig. 8] the Enlarged view in section, illustrating the contact area in the case in which the violation occurred in the connecting element 23C in the semiconductor device Options for implementation 3.

[Fig. 9] a View in section, illustrating the construction of another semiconductor device with the availa able scientific C with embodiment 3 of the present invention.

[Fig. 10] a View in section, illustrating the construction of another semiconductor device in accordance with embodiment 3 of the present invention.

[Fig. 11] (a)-(C) are phased in section, showing an example of a method of manufacturing a semiconductor device in accordance with embodiment 4 of the present invention.

[Fig. 12] (a) is a schematic view in section, showing a conventional TFT substrate in General, and (b) is an enlarged horizontal projection showing one pixel in the TFT substrate shown in (a).

[Fig. 13] in the context of TFT and pads conventional TFT substrate shown in Fig. 12.

[Fig. 14] a View in section, showing part of a conventional TFT substrate.

DESCRIPTION of embodiments

(An implementation option 1)

Below with reference to drawings, describes a method of manufacturing a semiconductor device in accordance with embodiment 1 of the present invention.

The semiconductor device of this variant implementation may include a TFT substrate on which is formed of at least one oxide semiconductor TFT, and, generally speaking, includes a display device, a TFT substrate of an electronic device, etc.

This pic is b manufacturing a TFT substrate of the liquid crystal display device, which contains the oxide semiconductor TFT as switching elements, will be described as an example. The TFT substrate has a display area that contains many of the pixel areas and the area of the electrode, which is formed in a region outside the display area. In the present invention, the oxide semiconductor TFT and storage capacitor are formed on each pixel area of the display area, and many of the pads is formed in the area of electrode placement.

Fig. 1(a)-(f) are schematic phased species in the section for a description of the method of manufacturing a semiconductor device in accordance with the present embodiment.

First, as shown in Fig. 1(a), the bus shutter 3A is formed in a region (region forming a TFT) And the substrate 1, in which the TFT should be formed; tire storage capacitor 3b is formed in a region (region forming a storage capacitor), which should form a storage capacitor; and a connecting element 3C tires shutter is formed in a region (region forming contact pads), which should form the contact area of the gate/source.

It should be noted that the area of forming the TFT and the area of the formation, however, is sustained fashion capacitor To be placed on each pixel area 101, which is within the display area, while the area of the formation of contact pads is located With in some area outside the display area, for example in the area of the electrode 102, which is located on the outer edge of substrate 1. Usually many of the pads of the source and pads shutter should be formed in the area of the electrode 102; however, in this paper, we show only the area of the formation With one of the contact pads of the shutter or source.

Bus shutter 3A, bus storage capacitor 3b and the connecting element 3 are formed by forming a metal film (for example, films of Ti/Al/Ti) on the substrate 1 by a sputtering method or a similar method with the subsequent formation of the pattern of the metal film. Forming a pattern of the metal film is performed by forming resistol mask using known photolithography and removing part which is not covered resistol mask. After that resista mask is removed from the substrate 1.

Next, as shown in Fig. 1(b), the insulating film 5 is formed so as to cover the bus shutter 3A, bus storage capacitor 3b and the connecting element 3C. Then, the oxide semiconductor layer in the form of island 7a, which should be the channel layer of the TFT, FD is formed in a region forming a TFT And, and the oxide semiconductor layer in the form of island 7b is formed in a region forming a storage capacitor C.

In the present embodiment, the method of chemical vapour deposition (CVD) as an insulating film 5 is formed, for example, a film of SiO2having a thickness of about 400 nm. It should be noted that the insulating film 5 can represent, for example, a single layer film of SiO2or have a multilayer structure, which has a bottom layer of SiNx film and the upper layer of the film of SiO2. In the case of a single layer film of SiO2the film thickness of SiO2is preferably not less than 300 nm and not more than 500 nm. If she has a multilayer structure composed of a SiNx film (lower layer) and the film of SiO2(the top layer), the thickness of the SiNx film is preferably not less than 200 nm and not more than 500 nm, and the thickness of the film of SiO2is preferably not less than 20 nm and not more than 150 nm.

Oxide semiconductor layer 7a, 7b can be formed as follows. First, by spraying on an insulating film 5 formed film semiconductor In-Ga-Zn-O (IGZO), having a thickness of, for example, not less than 30 nm and not more than 300 nm. Thereafter, using photolithography is formed resista mask covering the specified region of the IGZO film. Further, part of the IGZO film that not p is covered resistol mask, removed liquid etching. After this is removed resista mask. This creates an oxide semiconductor layer 7a, 7b in the form of an island. It should be noted that the oxide semiconductor layer 7a, 7b may be formed using an oxide semiconductor film other than the IGZO film.

Next, as shown in Fig. 1(C), an insulating film 9 is deposited on the entire surface of the substrate 1 and then patterned insulating film 9.

Specifically, first, for example, a film of SiO2(thickness: for example, about 150 nm) is formed as an insulating film 9 on the insulating film 5 and the oxide semiconductor layer 7a, 7b by using the CVD method.

The insulating film 9 preferably includes an oxide film, such as SiOy. Using the oxide film allows for the emergence of oxygen defects in the oxide semiconductor layer 7a, 7b to eliminate oxygen defects with oxygen contained in the oxide film, so the oxidation defects in the oxide semiconductor layer 7a, 7b can be reduced more effectively. Although as an insulating film 9 is used a single layer film of SiO2, the insulating film 9 may have a multilayer structure having a layer of film of SiO2and the top layer of SiNx film. The thickness (or a common the thickness of the respective layers in the case of a multilayer structure) of the insulating film 9 is preferably not less than 50 nm and not more than 200 nm. If it is 50 nm or more, the surface of the oxide semiconductor layer 7a can be protected more reliably on the steps of forming a pattern of electrodes and source/drain etc. on the other hand, if it exceeds 200 nm, more significant the difference between the levels arising from the source electrode and the drain electrode, can cause rupture of tires, etc.

Thereafter, using photolithography is formed resista mask covering a specified area of the insulating film 9. Further, part of the insulating film which is not covered resistol mask, liquid removed by etching. At this stage, the etching conditions should be selected so that in the formation of contact pads was carried out With the etching, not only the insulating film 9, and the underlying insulating film 5, and that the oxide semiconductor layer 7a, 7b under the insulating film 9 is not etched in the formation of a TFT and region forming a storage capacitor C. as a gas for etching is used, CF4/O2(cost: 475 cubic centimeters per minute/25 cubic centimeters per minute), and dry etching is carried out in the chamber at the set temperature of the substrate 1 at 60°C. the Degree of vacuum in the chamber is 15 MT (~2000 PA). Power is 1000 W, and the etching time is 7 minutes.

p> This results in the formation of a TFT And mytravelguide plots insulating film 9, which should be the contact source and drain contact, through which are two Windows 11as and 11ad, through which the oxide semiconductor layer 7a is left unprotected from exposure. The insulating film 9 covers the region of the oxide semiconductor layer 7a, which must be on the channel, and performs the function of a protective film channel 9a. In the formation of a storage capacitor In the etched area of the insulating film 9, which is located above the oxide semiconductor layer 7b which forms the window 11b, leaving unprotected from exposure to the oxide semiconductor layer 7b. In the formation of contact sites With consistently mytravelguide plot insulating film 9, which is located above the connecting element 3C, and the underlying insulating film 5, so that there is a window 11C, leaving unprotected from the effects of the connecting element 3C. The diameter of the window 11C is, for example, 20 μm.

At this stage, the etching conditions are preferably selected in accordance with the material of the insulating films 5 and 9, etc. so that the insulating film 5 and the insulating film 9 mytravelguide when using an oxide semiconductor is about layer 7a, 7b as an etching stopper. This results in the formation of contact pads With an insulating film 5 and the insulating film 9 mytravelguide at the same time (simultaneous etching GI/ES), while in region forming a TFT and region forming a storage capacitor In etched only the insulating film 9. The etching conditions include, in the case of using dry etching the type of gas for etching, the temperature of the substrate 1, the degree of vacuum in the vacuum, etc. when using a liquid etching includes the type of provide the Etchant, etching time, etc.

Next, as shown in Fig. 1(d), over the entire surface of the substrate 1 is formed a conductive film. In the present embodiment, a metal film, for example, a film of Ti/Al/Ti, is formed, for example, by spraying. After that patterned metal film, for example, by using photolithography.

This results in the formation of a TFT And on the inner side Windows 11as and 11ad and on the insulating film 9 are formed bus source 13as and the drain electrode 13ad so that they, respectively, in contact with the areas located on opposite sides of the field oxide semiconductor layer 7a, which should be the area of the channel. The drain electrode 13ad passes over the bus is capitalinos capacitor 3b and area of the storage capacitor and In contact with the oxide semiconductor layer 7b through the window 11b. The plot of the drain electrode 13ad, which is in contact with the oxide semiconductor layer 7b can also function as an electrode of the storage capacitor. In addition, in the formation of contact pads With the connecting member 13C which is electrically connected with the connecting element 3C, is formed on the inner side of the window 11C and on the insulating film 9.

In the present description, the area of the oxide semiconductor layer 7a, which is in contact with the bus source 13as, is called an "area source", while the area that is in contact with the drain electrode 13ad, called "drain region". In addition, the region of the oxide semiconductor layer 7a, which is located on the bus shutter 3A and is placed between the source and drain region, is called a "channel region".

Thus, the oxide semiconductor TFT is formed in a region forming a TFT And storage capacitor Cs is formed in a region forming a storage capacitor C. it Should be noted that the oxide semiconductor layer 7b, it is highly likely, due to dry damage will become a conductor. In this case, the storage capacitor Cs is formed by the storage capacitor bus 3b and the drain electrode 13ad and the oxide semiconductor layer 7b as electrodes and an insulating film 5 in cachestatistics.

After that, as shown in Fig. 1(e), piscivorous film 15 is deposited on the entire surface of the substrate 1 so as to cover the oxide semiconductor TFT and storage capacitor Cs. In the present embodiment, as a passivating film 15 by the CVD method is formed of an oxide film such as a film of SiO2(thickness: for example, about 265 nm). It should be noted that piscivorous film 15 can represent, for example, a single layer film of SiO2or have a multilayer structure having a layer of film of SiO2and the top layer of SiNx film. In the case of a single layer film of SiO2the film thickness of SiO2is preferably not less than 50 nm and not more than 300 nm. In the case of a multilayer structure of the film SiO2(lower layer) and the SiNx film (upper layer), the film thickness of SiO2is preferably not less than 50 nm and not more than 150 nm, and the thickness of the SiNx film is preferably not less than 50 nm and not more than 200 nm.

Next, using photolithography patterned passivating film 15. This results in the formation of a storage capacitor In through piscivorous film 15 is formed window 17b, leaving unprotected exposure to the drain electrode 13ad. Box 17b is formed on the cumulative capacitor Cs. In addition, in the formation of the contact area of the DKI With through piscivorous film 15 is formed window 17c, leaving unprotected from the effects of the connecting member 13C. As shown in the drawing, the window 11C and the window 17c can have almost the same width; however, when viewed from a direction normal to the surface of the substrate 1, box 17c preferably smaller in size than the window 11C, and is located within the holes 11C. In the result box 11C and 17c are deposited so as to be superimposed on each other, when viewed from a direction normal to the surface of the substrate, so that the contact hole in the contact area can be formed Windows 11S and 17c.

Next, as shown in Fig. 1(f), a passivating film 15 and in the Windows 17b and 17c is formed of a transparent conductive film, and a patterned transparent conductive film. In the result, there are formed a pixel electrode 19, which is in contact with the exposed surface of the drain electrode 13ad, and the connecting element 19 (C), which is in contact with the exposed surface of the connecting element 13C. Each pixel electrode 19 must be deposited separately for the respective pixel.

In the present embodiment, the transparent conductive film is applied, for example, by spraying. As the transparent conductive film is used, for example, a film of indium and tin oxides (ITO) (thickness: from 50 to 200 nm). Then the form is : the picture of the ITO film by using a known photolithography.

Although in Fig. 1 to simplify shows one pixel electrode 19, one storage capacitor Cs and one thin-film transistor TFT, the TFT substrate usually has a lot of pixel areas 101, so that the pixel electrode 19, the storage capacitor Cs and the thin-film transistor TFT is placed for each of the multiple pixel areas 101. In addition, in the area of the electrode 102 is formed the same number of pads as tire source 13as and tires shutter 3A.

Although not shown, there may be cases in which the connecting element is a gate-source for the connection bus source bus shutter is formed in the area of the electrode 102. In such cases, when forming the window 11C in the pad preferably, the insulating film 9 and the insulating film 5 on the bus shutter was etched simultaneously to form the window, leaving unprotected from the effects of bus shutter (or connecting member). With the formation of the tire source in this window is created connecting element, the gate-source and bus source bus shutter in direct contact.

Fig. 2 and Fig. 3 are diagrams which schematically shows the semiconductor device of the present invention. Fig. 2(a) represents the horizontal projection of the pixel is loshadki 101 of the semiconductor device, while Fig. 2(b) - (d) represent the horizontal projection of the gate electrode, the source electrode and the coupling element, the gate-source in the area of the electrode 102 of the semiconductor device, respectively. Fig. 3(a) is a view in section along the line I-I'shown in Fig. 2(a) and along the line II-II'shown in Fig. 2(b) or along the line III-III'shown in Fig. 2(C). Fig. 3(b) is a view in section along the line IV-IV'shown in Fig. 2(d).

As can be seen from these drawings, each pixel area 101 are formed bus source 13as, passing in the direction along the row of pixels, and the bus shutter 3A and the storage capacitor bus 3b, passing in the direction along a column of pixels.

Near the point where it is crossed bus source 13as and bus shutter 3A is formed of a thin-film transistor TFT and the storage capacitor Cs is formed above the storage capacitor bus 3b.

Oxide semiconductor layer 7a TFT is connected with the bus source 13as and the drain electrode 13ad, respectively, through the window 11as and 11ad insulating film 9. In addition, the drain electrode 13ad goes over the tire storage capacitor 3b and is connected to the pixel electrode 19 in box 17b passivating film 15 above the accumulating capacitor Cs.

Oxide semiconductor layer 7b savings conden atora Cs is connected with the electrode of the storage capacitor (which in this case is the drain electrode 13ad) in the window 11b insulating film 9 and is connected with the pixel electrode 19 in box 17b passivating film 15. When viewed from a direction normal to the surface of the substrate 1, box 17b is located in the window 11b.

The contact area of the gate pad and source of the connection element 3 is connected with the connecting element 13C in box 11C, which is created by the simultaneous etching of the insulating film 5 and the insulating film 9, and is connected with the connecting element 19s in the box 17c passivating film 15. In the present embodiment, because the window 17c is formed in the passivating film 15 after the formation of the connecting element 3 in box 11C, the connecting member 3 covers the end surface of the insulating films 5 and 9 in box 11C (on the surface of the wall box 11C), but does not cover the end surface passivating film 15 in the box 17c (on the surface of the wall box 17c). When viewed from a direction normal to the surface of the substrate 1, box 17c is located in box 11C.

In the connecting element, the gate-source coupling element 3d bus gate directly connected to a bus source 13as in box 11d, which is created by the simultaneous etching of the insulating film 5 and the insulating film 9. Bus source 13as covered with a passivating film 15.

The semiconductor device of the present invention, which is created as described above with reference to Fig. 1, gives the following benefits is compared with the traditional methods.

In the traditional method described in Patent document 1, first etched only protective film channel, and after the formation of electrodes and source/drain etched piscivorous film. Therefore, the contact hole formed in the pad, is formed by simultaneously etching the insulating film shutter and a passivating film (simultaneous etching GI/Pass). However, when using this method, as described above, the etching time is very long, if the insulating film shutter and piscivorous film formed using SiO2and the surface resistol film used as a mask for etching, may be corrupted in such a way that resista film may not be removed properly from the substrate.

In another approach, in the method described in Patent document 2, is formed piscivorous film having a multilayer structure with a top layer of the organic insulating film and the lower layer of the inorganic insulating film, an inorganic insulating film and an insulating film shutter mytravelguide using organic insulating film as a mask, through which is formed a contact hole pads (simultaneous etching GI/Pass). Moreover, when and what the use of this method, the etching time is very long in case if the inorganic insulating film shutter and piscivorous film formed using SiO2. Therefore, during etching the surface of the organic insulating film used as a mask, may be damaged.

On the other hand, in the present embodiment, the contact hole of the contact pad is formed in two separate phases. In particular, the etching of the insulating film 5, which should be an insulating film of the gate, and an insulating film 9 for forming the protective film channel (limiter etching) can be performed simultaneously, thereby forming the window 11S (simultaneous etching GI/ES). Then, after forming the electrodes of the source/drain, separately from the above-mentioned simultaneous etching GI/ES etched piscivorous film 15 for forming the window 17c in the passivating film 15 (etching Pass). Generally speaking, the thickness of the passivating film 15 is greater than the thickness of the insulating film 9 for forming the protective film channel. So while etching GI/ES of this variant implementation compared to traditional simultaneous etching GI/Pass, at which the insulating film shutter and piscivorous film mytravelguide at the same time, the total thickness of the film to be etched (vytravlivaetsya films) may be reduced.

More t the th, using traditional methods, it may be difficult to control the cone shape of the contact holes. In traditional methods conical shape of the contact hole of the contact pad is controlled on the basis of the etched while etching GI/Pass. On the other hand, in accordance with the present embodiment, control is based on the etching conditions in the etching, mainly, exclusively passivating film 15 (etching Pass). Generally speaking, if you have the same material vytravlivaetsya film, less attention should be paid to the damage caused by the mask for etching (resistol film), which means that the selection of etching conditions is simplified because vytravlivaetsya film thinner. Therefore, in accordance with the present embodiment, if vytravlivaetsya film can be made thinner than in conventional methods, it is possible to control the taper shape of the wall surface of the contact hole with a higher precision.

In particular, if and insulating film shutter and piscivorous film have a multilayer structure (for example, a two-layer structure), traditional methods will need to be corroding four layer film, which greatly complicates the control cone shape. This version is sushestvennee even in such cases, a tapered shape can be controlled by etching the two layers of film, which are piscivorous film, thereby greatly improving the controllability of the conical shape.

Thus, in accordance with the present embodiment, it is more reliable to the surface of the wall of the contact hole was tilted relative to the normal to the substrate at a given angle (cone angle), so that the violation of any bus formed over the contact hole can be prevented. Therefore, ensures electrical connection between the bus source or bus gate on the pad and the input section of the control scheme.

In addition, traditionally in the connecting element, the gate-source bus speed and bus source electrically connected through the transparent conductive film for forming the pixel electrodes (for example, Fig. 4 of Patent document 4). This led to the problem, consisting in the fact that if the surface of the wall of the contact hole of the connecting element, the gate-source insufficiently inclined relative to the normal to the substrate, bus source constituting the surface of the wall, and a transparent conductive film formed on the surface of the wall may not be electrically connected.

On the other hand, in accordance with the present embodiment, an insulating film (insulating film for the thief) 5 and the insulating film 9 mytravelguide at the same time, and, therefore, may be formed of such a connecting element, the gate-source that the connecting element 3d bus speed and bus source 13as direct contact. Therefore, even if the surface of the wall of the contact hole is almost naklonnoi, regardless of the conical shape of the wall surface of the contact hole bus shutter 3A and bus source 13as can electrically connect with greater reliability.

In addition, this version of the implementation also provides the following advantage as compared with the structure described in Patent document 3.

In the construction described in Patent document 3, the pattern of the gate electrode, the insulating film of the gate and the oxide semiconductor layer is formed using the same mask. The side walls of these layers are covered by an insulating film which functions as the etching stopper. In this design only the insulating film serving as the etching stopper, is provided between the side wall of the gate electrode and the source electrode, which leads to the possibility of a short circuit between the electrodes. On the other hand, in accordance with the present embodiment, the insulating film 5, which should be an insulating film of the gate-oxide semiconductor layer 7a and an isolating p is a child of 9, performs the function of a stopper of etching, longer than the bus shutter 3A in the direction along the length of the channel, the side wall of the tire shutter 3A is covered with the insulating film 5, the oxide semiconductor layer 7a, an insulating film 9. Therefore, at least two layers of insulating film (i.e., the insulating film 5 and the insulating film 9) exists between the upper surface and side wall of the tire shutter 3A and bus source 13as and between the upper surface and side wall of the tire shutter 3A and the source electrode 13ad. In the result, the above-mentioned short circuit can be prevented. Moreover, even in cases where the insulating film 5 provided with a hole, especially in the area of the insulating film 5, which is located between the bus shutter 3A and the electrode of the source/drain 13as, 13ad, the insulating film 9 can cover it, thereby preventing the occurrence between point defect.

In the present embodiment, it is preferable that at least one film - insulating film 5, the insulating film 9 and a passivating film 15 containing SiO2. In the result of any of these films, the oxygen will be supplied to the oxide semiconductor layer 7a, which should become the active layer of the TFT, allowing oxygen defects in the oxide poluprovodnikovom 7a, can be further reduced. As a result, the oxide semiconductor layer 7a can be prevented low resistance due to oxygen defects, allowing leakage currents and hysteresis can be reduced. In particular, it will be more effective if the surface of any of these insulating films, which is located from the side of the oxide semiconductor layer 7a (i.e., the upper surface of the insulating film 5, the lower surface of the insulating film 9 and the lower surface of the passivating film 15)is made of SiO2.

In addition, it is preferable that the insulating film 9 comprising a protective film channel 9a, covers the entire upper surface (except for the areas of source/drain) and the entire side surface of the oxide semiconductor layer 7a in the form of an island. When using this design at the stage of forming a pattern for forming electrodes and source/drain shown in Fig. 1(d), the emergence of oxygen defects in the channel region of the oxide semiconductor layer 7a and the surrounding area due to reactions oxidation-reduction can be prevented. As a result, the oxide semiconductor layer 7a can be prevented low resistance due to oxygen defects, allowing leakage currents and hysteresis can be reduced. the moreover, preferably, the insulating film 9 was longer than the oxide semiconductor layer 7a in the direction of the width of the channel and in contact with the top surface of the insulating film 5 located in the vicinity of the side wall oxide semiconductor layer 7a. In the result, the insulating film 9 with greater reliability will protect not only the upper surface but also the side wall oxide semiconductor layer 7a.

Oxide semiconductor layer 7a, 7b of this variant implementation is preferably, for example, a layer of a semiconductor-type Zn-O (ZnO), type semiconductor In-Ga-Zn-O (IGZO) or semiconductor-type Zn-Ti-O (ZTO).

(An implementation option 2)

Below with reference to drawings, describes a method of manufacturing a semiconductor device in accordance with embodiment 2 of the present invention. Present an implementation option differs from Option exercise 1 so that as the electrode of the storage capacitor instead of the source electrode is used pixel electrode.

Fig. 4(a) - (f) are schematic phased species in the section for a description of the method of manufacturing a semiconductor device of the present variant implementation. For simplicity, the elements similar to that shown in Fig. 1, will be denoted by the same Ref who CNAME positions, and their descriptions will be omitted.

First, as shown in Fig. 4(a), the bus shutter 3A is formed in a region forming a TFT And the substrate 1, in which the TFT should be formed; tire storage capacitor 3b is formed in a region forming a storage capacitor, which must form a storage capacitor; and a connecting element 3C tires shutter is formed in a region forming a contact pad With which to form the contact shutter/source. Methods of forming and materials tires 3A and 3b and the connecting element 3C is similar to the methods and materials described above with reference to Fig. 1(a).

Next, as shown in Fig. 4(b), the insulating film 5 is formed so as to cover the bus shutter 3A, bus storage capacitor 3b and the connecting element 3C. Then, the oxide semiconductor layer in the form of island 7a, which should be the channel layer of the TFT, is formed in a region forming a TFT, oxide semiconductor layer in the form of island 7b is formed in a region forming a storage capacitor C. the formation Methods and materials of the insulating film 5 and the oxide semiconductor layer 7a, 7b are similar to the methods and materials described above with reference to Fig. 1(b).

Next, as shown in Fig. 4(C), over the entire surface of the substrate 1 is deposited and airbusa film 9, and then patterned insulating film 9. This results in the formation of a TFT And mytravelguide plots insulating film 9, which should be the contact source and drain contact, through which are two Windows 11as and 11ad, leaving unprotected from exposure to the oxide semiconductor layer 7a. The insulating film 9 covers the region of the oxide semiconductor layer 7a, which must be on the channel, and performs the function of a protective film channel 9a. In the formation of a storage capacitor In the etched area of the insulating film 9 located above the oxide semiconductor layer 7b which forms the window 11b, leaving unprotected from exposure to the oxide semiconductor layer 7b. In the formation of contact sites With consistently mytravelguide plot insulating film 9, which is located above the connecting element 3C, and the underlying insulating film 5, and thereby create a window 11C, leaving unprotected from the effects of the connecting element 3C. Methods of forming material and method of etching an insulating film 9 is similar to the methods and materials described above with reference to Fig. 1(C).

Next, as shown in Fig. 4(d), after the deposition of the conductive film on the entire surface of the substrate 1 is formed her R is sunok. This results in the formation of a TFT And on the inner side Windows 11as and 11ad and on the insulating film 9 are formed bus source 23as and the drain electrode 23ad in order properly to come in contact with areas that are located on opposite sides of the field oxide semiconductor layer 7a, which should become a channel region. The drain electrode 23ad in the present embodiment has a structure in the form of the island, covering an area oxide semiconductor layer 7a, and does not extend into the area of forming the storage capacitor In contrast to the case for 1. In the formation of contact pads on the inner side of the window 11C and on the insulating film 9 is formed in the connecting element 23C, which is in contact with the connecting element 3C. In the present embodiment, by using the phase etching also removes the plot conductive film, which is located on the surface of the oxide semiconductor layer 7b in the formation of a storage capacitor In (i.e., inside the hole 11b). Thus in the formation of a TFT And is formed oxide semiconductor TFT. Material and methods of forming the conductive film of a similar material and method described above with reference to Fig. 1(d).

After that, as shown in Fig. 4(e), for all p the surface of the substrate 1 is applied piscivorous film 25. Then a figure passivating film 25 with steps of photolithography, etching liquid and removal/cleaning of the resist. This results in the formation of a TFT And a passivating film 25 is formed window 27A, leaving unprotected from the effects of the electrode surface runoff 23ad. In addition, in the formation of a storage capacitor is formed In a box 27b, leaving unprotected exposure to the surface of the oxide semiconductor layer 7b. In addition, in the formation of contact pads is formed With a window 27, leaving unprotected from the effects of the connecting element 23C. Material, formation method, and the method of etching the passivating film 25 a similar material and method described above with reference to Fig. 1(e).

After that, as described in Fig. 4(f), a transparent conductive film (for example, ITO film) is formed on the passivating film 25 and on the inner side of the Windows 27A, 27b and 27C, and the patterned transparent conductive film. In the result, there are formed a pixel electrode 29, which is in contact with the open surface of the drain electrode 23ad and the oxide semiconductor layer 7b and the connecting element 29s, which is in contact with the open surface of the coupling element 23C.

In the present embodiment, this step is formed a storage capacitor Cs in the formation of a storage capacitor C. Storage capacitor Cs is formed by the storage capacitor bus 3b and the oxide semiconductor layer 7b and the pixel electrode 29 as electrodes and the insulating film 5 as a dielectric.

Fig. 5 and Fig. 6 are diagrams which schematically shows the semiconductor device of the present invention. Fig. 5(a) represents the horizontal projection of pixel pads 201 of the semiconductor device, while Fig. 5(b) - (d) represent the horizontal projection of the gate electrode, the source electrode and the coupling element, the gate-source in the area of the electrode 202 of the semiconductor device, respectively. Fig. 6(a) is a view in section along the line I-I'shown in Fig. 5(a) and along the line II-II'shown in Fig. 5(b) or along the line III-III'shown in Fig. 5(C). Fig. 6(b) is a view in section along the line IV-IV'shown in Fig. 5(d).

As can be seen from these drawings, each pixel area 201 are formed bus source 23as passing in the direction along the row of pixels, and the bus shutter 3A and the storage capacitor bus 3b, passing in the direction along a column of pixels. Near the point where it is crossed bus source 23as and bus shutter 3A is formed of a thin-film transistor TFT. Oxide semiconductor layer 7a TFT is connected with a bus source 23as and the drain electrode 23ad, accordingly, in the Windows 11as and 11ad insulating film 9. The drain electrode 23ad electrically connected with the pixel electrode 29 in the window 27A passivating film 25.

On the bus storage capacitor 3b is formed storage capacitor Cs. Oxide semiconductor layer 7b storage capacitor Cs is connected with the pixel electrode 29 in the contact hole, which is formed by the window 11b insulating film 9 and the window 27b passivating film 25. Therefore, the pixel electrode 29 also function as an electrode of the storage capacitor. When viewed from a direction normal to the surface of the substrate 1 box 27b is located in the window 11b.

The contact area of the gate pad and source of the connection element 3 is connected with the connecting element 23C in box 11C, which is created by the simultaneous etching of the insulating film 5 and the insulating film 9. The connecting element 23C is connected with the connecting element 29s in the box 27C passivating film 25. In the present embodiment, as in Embodiment 1, the window 27 is formed in the passivating film 25 after forming the coupling element 23C in box 11C so that the connecting element 23C covers the end surface of the insulating films 5 and 9 in box 11C (on the surface of the wall box 11C), but does not cover the end of the second surface of the passivating film 25 in the box 27C (on the surface of the wall box 27C). When viewed from a direction normal to the surface of the substrate 1 box 27C is located in box 11C.

In the present embodiment, in the area of the electrode 202 of the substrate 1 can also be formed by coupling the gate-source. In the connecting element, the gate-source coupling element 3d bus gate directly connected to a bus source 23as in box 11C, which is created by the simultaneous etching of the insulating film 5 and the insulating film 9. Bus source 23as is covered with a passivating film 25.

In accordance with the present embodiment, the contact hole of the contact pad is formed by etching the insulating film 5, which should be an insulating film of the gate, and an insulating film 9 for forming the protective film channel (etching stopper) (simultaneous etching GI/ES) and etching of the passivating film 25 (etching Pass). Therefore, the etching time can be greatly reduced compared to traditional methods, in which an insulating film shutter and piscivorous film mytravelguide at the same time. Therefore, similarly to Variant implementation 1 damage mask for etching can be reduced. In addition, the conical shape of the wall surface of the contact hole can be controlled with higher accuracy. The AOC is e, in the connecting element, the gate-source coupling element 3d bus speed and bus source 23as can be connected in such a way that the connecting element 3d bus speed and bus source 23as can electrically connect with greater reliability regardless of the conical shape of the wall surface of the contact hole of the connecting element, the gate-source.

In addition, this version of the implementation in contrast to the case for 1 offers the following advantages. In embodiment 1, the structure of the drain electrode in the form of the island extends to the storage capacitor Cs to be used as the electrode of the storage capacitor. On the other hand, in the present embodiment, the drain electrode is not formed on the storage capacitor Cs. This design is implemented because the oxide semiconductor layer 7b in the formation of a storage capacitor To function as an etching stopper in the step of forming the conductive pattern film for forming tire source 23as, the drain electrode 23ad and the coupling element 23C (Fig. 4(d)).

Usually when you use a drain electrode as an electrode of the storage capacitor, as in the case of Option exercise 1, it is necessary to provide some margin to ensure that the CSOs, to the drain electrode and the storage capacitor bus overlap. Therefore, taken as such design that any of the following or bus storage capacitor or the drain electrode has a large flat shape. For example, in the Embodiment 1 is adopted such a construction, in which the width of the tire storage capacitor exceeds the width of the overlying drain electrode. And the drain electrode and the storage capacitor electrode made of a metal film or something like that, and increase their flat shape will be the cause of low intensity.

In addition, in the present embodiment, it is necessary to provide some margin to ensure that the tire storage capacitor 3b overlap with the oxide semiconductor layer 7b and the pixel electrode 29. For this reason, the oxide semiconductor layer 7b and the pixel electrode 29 are performed so that they had greater width than the width of the tire storage capacitor 3b. However, as the oxide semiconductor layer 7b, and the pixel electrode 29 are transparent and, therefore, will not be a cause of low intensity, even if they are made larger configuration. Thus, the aperture ratio can be increased compared to Option osushestvleniya.

(An implementation option 3)

Below with reference to drawings, describes a method of manufacturing a semiconductor device in accordance with embodiment 3 of the present invention. This version of the implementation differs from the above described embodiments by the fact that between the passivating film and the pixel electrode is formed of an organic insulating film.

Fig. 7(a) - (C) are phased in section for a description of the method of manufacturing a semiconductor device of the present variant implementation. For simplicity, the elements similar to that shown in Fig. 4 will be denoted by the same reference positions and their descriptions will be omitted.

First, as shown in Fig. 7(a), using a method similar to that used in the Embodiment 2 (Fig. 4(a) - (d)), on the substrate 1 are formed bus shutter 3A, the storage capacitor bus 3b, the connecting element 3C, the insulating film 5, the oxide semiconductor layer 7a, 7b, the insulating film 9, the tire source 23as, the drain electrode 23ad and the connecting element 23C.

Next, as shown in Fig. 7(b), on the surface of the substrate 1 in this order are formed piscivorous film 25 and the organic insulating film 36. As a passivating film 25, for example, using a CVD method is formed hydroxy who owned the film, having a thickness from 50 nm to 300 nm. The organic insulating film 36 is formed, for example, applying the acrylic resin film of a thickness of not less than 1 μm and not more than 4 μm. Preferably, by using the organic insulating film 36, the surface of the substrate 1 was planarity.

Next, after forming a pattern of an organic insulating film 36 by using photolithography, patterned passivating film 25 by dry etching using the organic insulating film 36 as a mask. This results in the formation of a TFT And through piscivorous film 25 and the organic insulating film 36 is formed window 37A, leaving unprotected exposure to the drain electrode 23ad. In addition, in the formation of a storage capacitor is formed In a box 37b, leaving unprotected from exposure to the oxide semiconductor layer 7b. In addition, in the formation of contact pads is formed With a window s, leaving unprotected from the effects of the connecting element 23C.

After that, as shown in Fig. 7(C), a transparent conductive film (for example, ITO film) is formed on the passivating film 25 and the Windows 37A, 37b and C, and patterned transparent conductive film. Thus are formed a pixel electrode 29, which is in contact with the open surface of electr is Yes drain 23ad and the oxide semiconductor layer 7b, and the connecting element 29s, which is in contact with the open surface of the coupling element 23C. The pixel electrode 29 also function as an electrode of the storage capacitor Cs. This creates the semiconductor device of this variant implementation.

The horizontal projection of the semiconductor device of this variant implementation is similar to the horizontal projection of the semiconductor device Option exercise 2 described above with reference to Fig. 5. However, the window 27A, 27b and 27C passivating film 25 shown in Fig. 5, should be viewed as a window 37A, 37b and C passivating film 25 and the organic insulating film 36 of this variant implementation. In addition, a view in section of the coupling element, the gate-source in the present embodiment, a similar view in section of the coupling element, the gate-source Option exercise 2 shown in Fig. 6(b).

In accordance with the present embodiment, the contact hole of the contact pad is formed by etching the insulating film 5, which should be an insulating film of the gate, and an insulating film 9 for forming the protective film channel (etching stopper) (simultaneous etching GI/ES) and etching the organic insulating film 36 (trawley the Pass). Therefore, the etching time can be greatly reduced compared to traditional methods, in which an insulating film shutter and piscivorous film mytravelguide at the same time. Therefore, similarly to the above-described variants of the implementation of the damage to the mask for etching can be reduced. In addition, the conical shape of the wall surface of the contact hole can be controlled with higher accuracy. In addition, in the connection element, the gate-source coupling element 3d bus speed and bus source 23as can electrically connect with greater reliability. In addition, as in Embodiment 2, there may be some margin to ensure overlap the storage capacitor bus 3b, the oxide semiconductor layer 7b and the pixel electrode 29 without reducing the aperture.

This version of the implementation also provides the advantage that, if violated coupling element 23C in the contact hole of the contact pads, the electrical connection between the bus shutter 3 and the connecting element 29s can be created with greater reliability.

Fig. 8 is an enlarged view in section, illustrating the contact area in the case in which the violation occurred in the connecting element 23C. As shown in the drawing, in the case in which the PR surface wall box 11C, formed insulating film 5 and the insulating film 9, does not have a desired tapered shape (e.g., the surface of the wall box 11C almost perpendicular to the surface of the substrate 1), a violation may occur in the connecting element 23C formed inside the box 11C. If the connecting element 23C is broken, piscivorous film 25 is deposited only on the broken coupling element 23C by a CVD method or a similar method. On the other hand, since the organic insulating film 36 should be applied in such a way as to cover the surface of the wall box 11C, any gap resulting from the violation, will be closed, due to which you will receive a window s with a smoother surface. As a result of this coupling element 29s, deposited in the box s, is unlikely to be broken. As a result, as shown in the drawing, even if the connecting element 23C violation occurs, the connecting element 29s and bus shutter 3 can electrically be connected via the connecting element 23C.

It is believed that even if the passivating film is provided an organic insulating film, as in the method described in Patent document 1, the advantage that described with reference to Fig. 8, will not be obtained if the inorganic insulating film and an insulating film shutter with avivausa at the same time (simultaneous etching Pass/GI). As noted earlier, in the oxide semiconductor TFT film SiO2preferably used as the insulating film of the gate protective film channel and a passivating film. This is because as the film SiO2has a lower etching rate than the SiNx film, this makes it difficult to control the surface condition or cone shape of the organic insulating film, which is a mask for etching during the simultaneous etching Pass/GI.

The design of the semiconductor device of this variant implementation is not limited to the construction described above with reference to Fig. 7. Fig. 9 and Fig. 10 are views in section, showing other examples of the semiconductor device of this variant implementation.

In the example shown in Fig. 7, a passivating film 25 is formed of the organic insulating film 36. However, as shown in Fig. 9, the organic insulating film 36 may be formed instead on the passivating film 15 of a semiconductor device of a Variant of implementation 1. The horizontal projection of the semiconductor device shown in Fig. 9, similar to the horizontal projection of the semiconductor device Options implement 1 shown in Fig. 2. However, the window 17b and 17c passivating film 15 shows the ow in Fig. 2, should be viewed as open passivating film 15 and the organic insulating film 36 of this variant implementation. In addition, a view in section of the coupling element, the gate-source a similar view in section of the coupling element, the gate-source Variant implement 1 shown in Fig. 3(b). Semiconductor device shown in Fig. 9, produces the same effects as an implementation Option 1. In addition, as described above with reference to Fig. 8, even if the connecting element 13C violation occurs, the contact area can be ensured electrical connection between the tyres.

In the example shown in Fig. 7, piscivorous film 25 and the organic insulating film 36 is formed also in a region forming a contact area S. However, as shown in Fig. 10, piscivorous film 25 and the organic insulating film 36 does not necessarily have to be formed in the formation of contact pads C. also in the case where the organic insulating film 36 is formed on the passivating film 15, as shown in Fig. 9, piscivorous film 15 and the organic insulating film 36 does not necessarily have to be formed in the formation of contact pads C.

(An implementation option 4)

Below with reference to drawings, describes a method of manufacturing the semiconductor is of nikolovo device in accordance with embodiment 4 of the present invention. This version of the implementation differs from the above embodiments that as an insulating film shutter is formed of a multilayer film having a lower layer of SiNx film and the upper layer of the film of SiO2and that as a passivating film is formed of a multilayer film having a lower layer of the film of SiO2and the top layer of SiNx film.

Fig. 11(a)-(C) are phased in section for a description of the method of manufacturing a semiconductor device of the present variant implementation. For simplicity, the elements similar to that shown in Fig. 4 will be denoted by the same reference positions and their descriptions will be omitted.

First, as shown in Fig. 11(a), on the substrate 1 are formed bus shutter 3A, bus storage capacitor 3b and the connecting element 3C. The method of forming tires shutter 3A, bus storage capacitor 3b and the connecting element 3C is similar to the method described above with reference to Fig. 1(a).

Next, as shown in Fig. 11(b), in this order, is formed SiNx film 5L and film SiO25U thus, to cover the bus shutter 3A, bus storage capacitor 3b and the connecting element 3, thereby forming the insulating film 5. After that, the insulating film 5 is formed oxide semiconductor is the first layer 7a, 7b.

When the CVD method is formed SiNx film 5L, having a thickness of, for example, not less than 200 nm and not more than 500 nm, and a film of SiO25U, having a thickness of, for example, not less than 20 nm and not more than 150 nm. Oxide semiconductor layer 7a, 7b is created by formation of the IGZO film having a thickness of, for example, not less than 30 nm and not more than 300 nm, by a sputtering method and forming her figure. The method for forming the oxide semiconductor layer 7a, 7b is similar to the method described above with reference to Fig. 1(b).

Further, although not shown, on the surface of the substrate 1 is deposited insulating film 9 in the manner described above with reference to Fig. 1(C). After that, in the formation of a TFT And an insulating film 9 is formed a window for forming the contact of the source and the window for forming the drain contact; and forming a storage capacitor In the insulating film 9 is formed a window, leaving unprotected from exposure to the oxide semiconductor layer 7b. However, in the formation of contact pads for forming window mytravelguide insulating film 9 and the insulating film 5. Next, using the method described above with reference to Fig. 4(d), an insulating film 9 and in the window insulating film 9 is formed of a metal film, and is formed her pattern for forming tire source 23as, the drain electrode 23ad and soy is intellego element 23C.

After that, as shown in Fig. 11(C), in that order on the surface of the substrate 1 are formed film of SiO225L and the SiNx film 25U, thereby forming piscivorous film 25. In the present embodiment, CVD is used for forming a film of SiO225L, having a thickness of, for example, not less than 50 nm and not more than 150 nm, and the film of SiNx 25U, having a thickness of, for example, not less than 50 nm and not more than 200 nm.

Next, using the stages of photolithography, liquid etching and removal of resist/cleaning patterned passivating film 25. This results in the formation of a TFT And a passivating film 25 is formed window 27A, leaving unprotected exposure to the drain electrode 23ad. In addition, in the formation of a storage capacitor is formed In a box 27b, leaving unprotected from exposure to the oxide semiconductor layer 7b. However, in the formation of contact pads is formed With a window 27, leaving unprotected from the effects of the connecting element 23C.

Thereafter, although not shown, as described above with reference to Fig. 4(f), a transparent conductive film (for example, ITO film) is formed on the passivating film 25 and the Windows 27A, 27b and 27C, and the patterned transparent conductive film. In the result, there are formed a pixel electrode 29, which sapric is on with an open surface drain electrode 23ad and the oxide semiconductor layer 7b, and the connecting element 29s, which is in contact with the open surface of the coupling element 23C.

The horizontal projection of the semiconductor device of this variant implementation is similar to the horizontal projection of the semiconductor device Option exercise 2 described above with reference to Fig. 5. In addition, a view in section of the coupling element, the gate-source in the present embodiment, a similar view in section of the coupling element, the gate-source Option exercise 2 shown in Fig. 6(b).

In accordance with this embodiment, it is achieved effects similar to the effects of Option exercise 2. In addition, the use of a multi-layered film consisting of a film of SiO2and the SiNx film as the insulating film (insulating film shutter) 5 and a passivating film 25 gives the following advantage.

In the oxide semiconductor TFT using a single layer of SiNx film as an insulating film shutter and a passivating film there is a possibility that the oxygen content in the oxide semiconductor layer can be reduced, since the heat treatment is carried out at a time when the oxide semiconductor layer is in contact with the SiNx during the manufacturing process. In addition, the oxide semiconductor SL the nd susceptible to damage by the plasma during the formation of the SiNx film. In the result, the characteristics of the oxide semiconductor TFT may deteriorate. On the other hand, when using a single layer film of SiO2as an insulating film shutter and a passivating film of the above-mentioned problems can be avoided, but the film SiO2it is necessary to make thick, to reach the breakdown voltage of the source-gate, since the film of SiO2has a lower dielectric constant than the SiNx film. It can lower the activation current of the TFT.

On the other hand, when using a multi-layered film consisting of a film of SiO2and the SiNx film as the insulating film shutter and a passivating film, even if they are thinner than the insulating film speed or piscivorous film consisting only of the film SiO2can be reached , a sufficient breakdown voltage. Therefore, the current down turn on the TFT connected with the insulating film shutter and a passivating film can be prevented. In addition, each multilayer film due to the deposition of the film of SiO2as a film that is in contact with the oxide semiconductor layer, or which is nearest to the oxide semiconductor layer, it is possible to prevent decrease of the oxygen content in the oxide semiconductor layer due to SiNx and to prevent damage to the plasma arsenomolybdate layer during the formation of the SiNx film.

An insulating film 5 of this option may not have any multilayer structure comprising a film of SiO2and the SiNx film, in which the top layer of a multilayer structure, i.e. the layer that comes into contact with the lower surface of the oxide semiconductor layer is a film of SiO2. Similarly piscivorous film 25 may have any multilayer structure comprising a film of SiO2and the SiNx film, in which the top layer of a multilayer structure, i.e. the layer closest to the side of the oxide semiconductor layer is a film of SiO2. Although the insulating film 5, and piscivorous film 25 have a multilayer structure in the example shown in Fig. 11, the above effect can be obtained, provided that only one of them has the above-mentioned multi-layered structure. However, a more significant effect can be obtained in cases where both films 5 and 25 have the above-mentioned multilayer structure.

In traditional methods, the etching of the passivating film and the insulating film shutter is carried out simultaneously (simultaneous etching Pass/GI). Therefore, if these films are multilayer films, as mentioned above, the SiNx film/SiO2/SiO2/SiNx was etched simultaneously. In other words, three layers (SiNx/SiO2/SiNx) which differ from each other by etching speeds were etched simultaneously. This greatly complicates the control of the taper during the etching process. Since the SiNx film is several times higher speed dry etching than the film of SiO2the etching of these multilayer films may cause a shift of the SiNx film, thereby causing zetoobraznoj form. In addition, if the organic insulating film provided on the passivating film, as in Patent document 1, the damage to the surface of the organic insulating film serving as a mask for etching, it would also be a need to control, which makes the control of the taper during the simultaneous etching Pass/GI almost impossible.

On the other hand, in accordance with the present embodiment, etching is performed only for two layers of SiO2/SiNx during the simultaneous etching ES/GI and SiNx/SiO2for passivating film (etching Pass), so the control of the taper can be achieved with higher accuracy than in the conventional method of etching the three layers of SiNx/SiO2/SiNx.

It should be noted that, as described in the Embodiment 3, the organic insulating film may be provided between the passivating film 25 and the pixel electrode 29 also in the semiconductor device of this variant implementation. And in this case, apart from the simultaneous Tr the effect of insulating films 5 and 9, the etching of the passivating film (SiNx/SiO 2) 25 can be performed by using an organic insulating film as a mask for etching (etching Pass). This can be controlled by the cone shape of the window in the passivating film 25 while preventing damage to the surface of the organic insulating film.

In the example shown in Fig. 11, a multilayer film composed of SiNx film and the film of SiO2used as the insulating film 5 and a passivating film 25 of the semiconductor device Option exercise 2. However, a multilayer film consisting of SiO2and SiNx can be used as an insulating film 5 and a passivating film 15 of a semiconductor device of a Variant of implementation 1. The result achieved effects similar to the above. In other words, without deteriorating the controllability of the conical shape can be prevented from deterioration of characteristics of the TFT. And in this case, the organic insulating film, such as described in Embodiment 3 may be provided between the passivating film 15 and the pixel electrode 19.

INDUSTRIAL APPLICABILITY

The present invention is widely applicable to devices containing thin-film transistors, such as: card, for example, the active matrix substrate; a display device, for example, recommittal the practical display device, organic electroluminescent (EL) display device and organic electroluminescent display device; forming of images, for example, devices on the basis of the image sensor; and an electronic device, for example, input images, and device fingerprint. In particular, it is suitably applicable to a large-sized liquid crystal display devices, etc.

The REFERENCE LIST of ITEMS

1 substrate

3A bus shutter

3b storage capacitor

3C coupling element

3d coupling element

5, the insulating film (insulating film shutter)

5L lower layer insulating film shutter

5U of the upper layer insulating film of the gate

7a, 7b oxide semiconductor layer (active layer)

9, the insulating film (protective film, the etching stopper)

11as, 11ad, 11b, 11c, 11d, 17b, 17c, 27a, 27b, 27c, 37a, 37b, 37c window

13as, 23as bus source

13ad, 23ad the drain electrode

13C, 23C, 19s, 29s coupling element

15, 25 piscivorous film

19, 29 pixel electrode

36 organic insulating film

25L bottom layer passivating film

25U top layer of a passivating film

101, 102 area of a single pixel in the display area

102, 202 area electrode

1. Semiconductor in trojstvo, contains:
substrate; a thin-film transistor formed on the substrate; and a contact pad for electrical connection of the thin-film transistor with external interconnects,
moreover, the thin-film transistor includes:
bus shutter provided on the substrate;
the first insulating film formed on the bus shutter;
oxide semiconductor layer in the shape of the island, formed on the first insulating film, and in the oxide semiconductor layer in the shape of the island has a channel region and has Itokawa region and a drain region located at opposite sides of the channel region;
a second insulating film provided in contact with the oxide semiconductor layer;
bus source provided on the second insulating film and electrically connected to stokovoj area;
a drain electrode provided on the second insulating film and electrically connected with the drainage area; and
piscivorous film provided on the bus the source and the drain electrode and covering the thin film transistor, and the contact pad contains:
the first coupling element, made of the same conductive film as the bus shutter;
the second coupling element formed on the first connecting ale is NTE and made of the same conductive film, as the bus of the source and the drain electrode; and
the third coupling element formed on the second connecting element, and
in the first window provided in the first insulating film and the second insulating film, the second coupling element is in contact with the first connecting element;
in the second window provided in the passivating film, the third coupling element is in contact with the second connecting element; and
the second connecting member covers the end surface of the first insulating film and the second insulating film in the first window, but does not cover the end surface passivating film in a second window.

2. The semiconductor device according to claim 1, in which the second window is located inside the first box, when viewed from a direction normal to the substrate surface.

3. The semiconductor device according to claim 1 or 2, additionally containing a pixel electrode electrically connected with the drain electrode, in which the third coupling element is made of the same conductive film as the pixel electrode.

4. The semiconductor device according to claim 3, additionally containing a storage capacitor formed on the substrate,
moreover, the storage capacitor includes:
bus storage capacitor, made of the same PR is leading film, as the bus shutter;
the first insulating film covering the storage capacitor bus;
the semiconductor layer for forming the storage capacitor, and the semiconductor layer is made of the same oxide semiconductor film, and the oxide semiconductor layer; and
the storage capacitor electrode provided on the semiconductor layer for forming the storage capacitor, and
the storage capacitor electrode is in contact with the semiconductor layer for forming the storage capacitor in the window formed in the second insulating film.

5. The semiconductor device according to claim 4, in which
the storage capacitor electrode is a part of the drain electrode; and a pixel electrode in contact with the electrode of the storage capacitor in the window formed in the passivating film.

6. The semiconductor device according to claim 4, in which the storage capacitor electrode is a part of the pixel electrode.

7. The semiconductor device according to claim 1, additionally containing the connecting element, the gate-source for electrical connection of the bus speed and bus source, while
in the connecting element, the gate-source bus source in contact with the bus gate in the first window provided in TRANS is Oh insulating film and the second insulating film.

8. The semiconductor device according to claim 1, additionally containing an organic insulating film between the passivating film and the pixel electrode.

9. The semiconductor device according to claim 1, in which at least one of the films - the first insulating film or piscivorous film contains SiO2.

10. The semiconductor device according to claim 9, in which the first insulating film has a multilayer structure comprising a film of SiO2and the film SiNxand the film of SiO2is the top layer of the multilayered structure and is in contact with the bottom surface of the oxide semiconductor layer.

11. The semiconductor device according to claim 9 or 10, in which piscivorous film has a multilayer structure comprising a film of SiO2and the film SiNxand the film of SiO2is the lower layer of the multilayer structure.

12. The semiconductor device according to claim 1, in which at least the first insulating film and the oxide semiconductor layer is provided between the upper surface and side wall of the tire valve and the tire source and between the upper surface and side wall of the tire valve and the drain electrode.

13. The semiconductor device according to item 12, which further include a second insulating film between the upper surface and the side is Tenkai bus speed and bus source and between the upper surface and side wall of the tire valve and the drain electrode.

14. The semiconductor device according to claim 1, in which within the surface of the oxide semiconductor layer, the second insulating film covers the totality of the upper surface and the side wall, with the exception of the area of source and drain, and is in contact with the top surface of the first insulating film near the side wall oxide semiconductor layer.

15. The semiconductor device according to claim 1, in which the width of the oxide semiconductor layer in the direction along the width of the channel is greater than the width of the tires of the shutter in the direction along the width of the channel.

16. A method of manufacturing a semiconductor device according to any one of claims 1 to 15, which includes:
(A) a step of forming a conductive film for bus gate on a substrate and forming a pattern of a conductive film for forming the tire valve and the first coupling element;
(B) a step of forming a first insulating film on the bus speed and the first connecting element;
(C) a step of forming on the first insulating film oxide semiconductor layer, which should become the active layer of the thin-film transistor;
(D) a step of forming a second insulating film covering the oxide semiconductor layer and the first insulating film;
(E) a step of etching the first and second insulating films by using oxide-semiconductor is of nikolovo layer as an etching stopper for forming the second insulating window film to form a contact source and open to form a contact flow thus that the oxide semiconductor layer exposed through the Windows, and forming a first window in the second insulating film and the first insulating film so that the surface of the first conductive element exposed through the first window;
(F) a step of forming a conductive film for the electrode and source/drain of the second insulating film and forming a pattern of a conductive film for forming tires of the source, which is in contact with the oxide semiconductor layer within the window for the formation of the contact of the source, the drain electrode which is in contact with the oxide semiconductor layer within the window for the formation of the drain contact, and a second coupling element which is in contact with the first connecting element within the first window;
(G) a step of forming a passivating film on the bus the source, the drain electrode and the second connecting element;
(H) a step of forming a second window in the passivating film so that the second coupling element exposed through the second window; and
(I) the step of forming the third coupling element in the passivating film, and the third coupling element is in contact with the second connecting element within the second window.

17. A method of manufacturing a semiconductor device is TBA on P16, in which
step (H) includes the step of forming a passivating film window for influencing the drain electrode; and
step (I) is a step of forming a transparent conductive film on the passivating film and the deposition of a transparent conductive film for formation of the third coupling element and the pixel electrode, and a pixel electrode in contact with the drain electrode within the window to expose the drain electrode.



 

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6 cl, 6 dwg, 1 tbl

FIELD: electricity.

SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value.

EFFECT: improvement in electric parameters of powerful silicone generating SHF LDMOS transistors, increase of their resistance to ionising radiation exposure and increase of production output in percents.

7 dwg

FIELD: electricity.

SUBSTANCE: in the method for manufacturing of a semiconductor device including formation of a semiconductor substrate of the first type of conductivity, a gate electrode formed above a subgate dielectric and separated with interlayer and side insulation from a metal source electrode (emitter), a channel area of the second conductivity type and a source area of the first conductivity type, formed by serial ion alloying of admixtures into windows of the specified shape in the gate electrode, and the metal source electrode, a subgate dielectric is developed, as well as a gate electrode and interlayer insulation above the gate electrode in a single photplithographic process by plasma-chemical feeble anisotropic etching with ratio of vertical and horizontal components of etching speed making (3÷5)/1.

EFFECT: reduced resistance in open condition without increasing dimensions of a crystal and improved efficiency without deterioration of other characteristics.

11 cl, 4 dwg

FIELD: electronic engineering.

SUBSTANCE: device provided with short channel for controlling electric current has semiconductor substrate to form channel. Doping level of channel changes extensively in vertical direction and keeps to constant values at longitudinal direction. Electrodes of gate, source and discharge channels are made onto semiconductor substrate in such a manner that length is equal or less than 100 nm. At least one of source and discharge electrodes form contact in shape of Schottky barrier. Method of producing MOS-transistor is described. Proposed device shows higher characteristics at lower cost. Reduction in parasitic bipolar influences results to lower chance of "latching" as well as to improved radiation resistance.

EFFECT: improved working parameters.

24 cl, 11 dwg

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