Modulo adder-accumulator

FIELD: information technology.

SUBSTANCE: device has an n-bit adder, an (n+1)-bit adder, a multiplexer and a register.

EFFECT: broader functional capabilities due to introduction of the modulo addition operation.

1 dwg

 

The invention relates to computer technology and can be used in digital computing devices, and devices digital signal processing and cryptographic applications.

Known for accumulating adder (Tarabrin BV Reference integrated circuits / BV Tarabrin, S. Jakubowski, N.A. Barkanov, etc. Ed. BV Tarabrina. - 2nd ed., Rev. and supplementary): Energy, 1981., Fig.5-250, str)containing 3 adder and 3 of the register.

The disadvantage of this adder is limited functionality, namely the absence of the accumulation operation for the module.

The closest to the technical nature of the claimed invention is a cumulative adder, containing the register and the adder (Naumkin L.G. Digital circuitry. Abstract of lectures on discipline "Circuitry" - M: "Mountain book". Publishing house of Moscow state mining University, 2008, RIS, str).

The disadvantage of this device is limited functionality, namely the absence of the accumulation operation for the module.

The purpose of the invention is the extension of the functionality of the device due to the introduction of the accumulation operation for the module.

To achieve this goal in the accumulating adder module containing n-bit adder n-bit p is gistr, and second information inputs of the adder are information input device, and an information output registers are informational outputs of the device and connected with the first information input n-bit adder, a clock input of the register is clocked by the input device, the input to the reset register is input reset of the device, and the carry-in input n-bit adder is a carry-in input device, put (n+1)-bit adder n-bit multiplexer, and 1...n information outputs n-bit adder is connected with the first 1...n information inputs (n+1)-bit adder and the second 1...n information inputs of the multiplexer, the output of transfer n-bit adder connected to the first (n+1) informational log (n+1)-bit adder, the second 1...n+1 information inputs which are the inputs of the module code in inverted form to the input of the transfer (n+1)-bit adder is supplied logical unit, the output transfer (n+1)-bit adder is connected with the control input of the multiplexer, and 1...n information outputs are connected with the first 1...n information inputs of the multiplexer, the information outputs of which are connected with the inputs of the register entries.

The invention consists in the implementation of the following method, the cumulative summation of isel And imodulo R. at the input of accumulating adder integers Ai(i=1,2,3,...), 0≤Ai<P, potuckova added up the numbers written in his memory at the previous time step. Before the first beat of the memory device reset. The result of summing Ai+Ai-1given modulo P as follows. If (S=Ai+Ai-1)<P, is the usual sum S=Ai+Ai-1and this sum S is the result. If (S=Ai+Ai-1)≥P, and the initial condition for the sum of S cannot exceed 2P-2, then the sum S is subtracted the value of R and the result is the sum of (Ai+Ai-1) mod P. the result is written to the device memory and on the next cycle is used as the value of Ai-1.

Figure 1 presents the scheme of the accumulating adder module.

Accumulating adder module contains 2 adder 1 and 2, and the adder 1 is n-bit, and the adder 2 is (n+1)-bit multiplexer 3 and the case 4. Input 5 sequentially, synchronously with a clock pulse applied to the input 9, is supplied sequence of integers Andion input 6 is fed a zero signal to the input 7 is supplied code module in inverted form to the input 8 is supplied to a logic unit, input 10 is used to reset the accumulating adder before you begin. The outlet 11 is closed the house device. The outputs of the register 4 is connected to the output 11 of the device and with the first inputs of the adder 1, the outputs of the adder 1 is connected with the first inputs of the adder 2 and the second inputs of the multiplexer 3. Information outputs of the adder 2 is connected with the first inputs of the multiplexer 3, and the output of the transfer of the adder 2 - with the control input of the multiplexer 3. The outputs of the multiplexer 3 is connected to the inputs of register entries 4. Inputs 5 supply code number of the device connected with the second information input of the adder 1.

Accumulating adder module works as follows.

Before working on the input 10 of the device is a pulse which clears the contents of register 4. Input device 9 receives clock pulses which synchronize the operation of the device. With each clock pulse on input 5 enter codes numbers Andiarriving at the inputs (In1...Inn) adder 1. The bit width of the input number is equal to n. The first inputs of the adder 1 enters a code number from the output of the memory element device - register 4. On the first beat of this number is "0". From the output of the adder 1 code amount supplied to the first inputs of the adder 2 and the second input (Y1...Yn) multiplexer 3. On the second inputs of the adder 2 (B1...Bn+1) gets the inverse of the code module, and the input transfer 8 - logical unit. The adder 2 performs the OPE is the situation subtracting from the code number, coming from the output of the adder 1, the code module R coming from input 7 devices. If reducing the number greater than or equal to R, the outputs of the adder 2 (S1...Snappears the difference of numbers, and the output transfer RAboutadder 2 appears logical unit, which is supplied to the control input of the multiplexer 3, under the influence of which on the output of the multiplexer are connected to the second inputs (Y1...Yn). If reducing the number less than R, then the output transfer RAboutproduces a zero signal, and the outputs of the multiplexer are connected to its first input (X1...Xn). Under the influence of the clock pulse number from the output of the multiplexer is recorded in the register 4. This number on the next cycle of operation acts as a first addend And adder 1 and the result of evaluating S at this stage, arriving at the output 11 of the device. Thus, at each stage in the register is formed by the sum of all received in the previous cycles of numbers Andimodulo R.

Accumulating adder module containing n-bit adder n-bit register, and the second information inputs of the adder are information input device, and an information output registers are informational outputs of the device and connected with the first info is made use of inputs n-bit adder, the clock input of the register is clocked by the input device, the input to the reset register is input reset of the device, and the carry-in input n-bit adder is a carry-in input device, characterized in that it introduced the (n+1)-bit adder n-bit multiplexer, and 1...n information outputs n-bit adder is connected with the first 1...n information inputs (n+1)-bit adder and the second 1...n information inputs of the multiplexer, the output of transfer n-bit adder connected to the first (n+1) information input (n+1)-bit adder, the second 1...n+1 information inputs which are the inputs of the module code in inverted form to the input of the transfer (n+1)-bit adder is supplied logical unit, the output transfer (n+1)-bit adder is connected with the control input of the multiplexer, and 1...n information outputs are connected with the first 1...n information inputs of the multiplexer, the information outputs of which are connected to the inputs of register entries.



 

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